Current Mirror Circuit

The current mirrors which shown in Fig. 4.9 are basic and critical circuit in analog integrate circuit. For current mirror design, the match of transistor pair is important. The mismatch of device influence the reference current and output current value and result in the variation of circuit operation. The analytical formula for the ratio of reference current and output current is expressed as below:

(IREF Vth,M2 are the parameters of transistors M1 and M2. If M1 and M2 is matched, the cor-responding values are the same, the current ratio is 1. However, these parameters will be different for each device if considering device intrinsic parameter fluctuation. Here we assume μ^_n, C_ox^ , W , L, and VGS are constant with respect to work-function fluctuation, the only term which affects the current mismatch is the threshold voltage fluctuation. To investigate the current mismatch, we define the normalized IOU T fluctuation:

N ormalized IOU T f luctuation(%) = σ(IREF − IOU T) IREF

× 100%, (4.8)

where the IREF and IOU T are the reference and output currents, as shown in Fig. 4.9. In Fig. 4.10, the WKF induces about 8% normalized IOU T fluctuation due to the drain current of transistor is strongly relative to threshold voltage.

74 Chapter 4 : Circuits Characteristic Fluctuations

,

,

5

5

9

9

D

9

E

5

,

,

5

0 0

9

0 0



Figure 4.9: The (a) NMOS and (b)PMOS current mirror circuits used in this work.

4.2 : Analog Circuits 75

1R UPDO L]HG ,

)OXFXWDW LR Q  

















1026



3026

Figure 4.10: The summarized normalized IOU T fluctuations induced by work-function fluctuation for NMOS and PMOS current mirrors.

76 Chapter 4 : Circuits Characteristic Fluctuations

4.3 Summary of this Chapter

This chapter has estimated the influences of the work-function fluctuation in 16-nm nanoscale circuits. The WKF significantly affect the device threshold voltage fluctuation;

and therefore impact the timing of inverter circuit, static noise margin of SRAM circuit, and current mismatch of current mirror circuit. The fluctuations of rise time, fall time, and de-lay time fluctuations follow the trend of Vthfluctuation. The power fluctuations consisting of dynamic power, short circuit power, and static power have been estimated. The dynamic power and short circuit power are the most important power dissipation sources. However, the static power fluctuation dominates the total power fluctuation due to the exponential relationship between the leakage current and the Vth. For current mirror, the circuit per-formance variability caused by device mismatch is also clearly shown. For SRAM, static noise margin fluctuations have been explored and the WKF brings significant variations.

For the high frequency characteristics of common source amplifier, the circuit gain, 3dB bandwidth, and unity-gain bandwidth have been explored. Similar to the trend of the device AC characteristics, the WKF shows less impact on high frequency characteristic owing to the small gate capacitance fluctuation. It is necessary to include the WKF effects in study-ing digital circuit reliability; however, for high frequency applications, the influence of WKF may neglect.

Chapter 5

The Total Effects of All Fluctuations

The random dopant fluctuation (RDF) and process variation effect (PVE) are important variation sources of state-of-art CMOS device [7-45]. It is necessary to compare the WKF with RDF and PVE. This chapter investigates and compares the characteristic fluctuations induced by RDF, PVE, and WKF for CMOS devices and circuits, then the dominant fluc-tuation sources are identified.

5.1 Device Characteristics

The RDF-, PVE-, and WKF-fluctuated Vthof CMOS devices are first explored. Figure 5.1 shows the σVth induced by RDF, PVE, and WKF. The total Vthfluctuation ( σVth,total)

77

78 Chapter 5 : The Total Effects of All Fluctuations

is given by according to the independency of the fluctuation components:

(σV^th,total)² ≈ (σV^th,RDF)²+ (σV^{th,P V E})² + (σV^{th,W KF})², (5.1)

where the σVth,RDF, σVth,P V E, and σVth,W KF, are the random-dopant-induced, process-variation-induced, and work-function-fluctuation-induced Vthfluctuation, respectively. The results show that WKF induced σVth are competitive with RDF and is one of the major variation sources of the Vth fluctuation. The σVth,total of NMOS and PMOS devices are 63 mV and 66 mV, respectively. Notably, the statistical addition of individual fluctuation sources herein simplifies the variability analysis of nano-devices and circuits. However, the dominant source of fluctuation will not be significantly altered.

5.1 : Device Characteristics 79

Figure 5.1: The summarized threshold voltage fluctuations for (a) NMOS and (b) PMOS devices, respectively.

80 Chapter 5 : The Total Effects of All Fluctuations

The RDF-, PVE-, and WKF-fluctuated CG with different gate bias are compares in Fig 5.2 for NMOS and PMOS devices. The different intrinsic parameter variability in-duced rather different C-V characteristics. Different to the results of Vth fluctuation, the WKF brought less impact on gate capacitance fluctuation. At low gate bias or negative gate bias, the accumulation layer screens the impact of RDF and WKF. The capacitive re-sponse is then dominated by increment of inversion in the moderate inversion. The device characteristics are then impacted by intrinsic parameter fluctuated electrostatic potentials.

The RDF is the largest variation source at this bias condition. If the high VGis achieved, the capacitive response becomes dominated by the inversion layer, the impact of the individual dopant or metal grain on the device electrostatics is screened by the inversion layer itself.

The impact of RDF- and WKF-induced electrostatic potential variations is therefore bring-ing less impact on channel surface. The PVE dominates the gate capacitance fluctuations at all gate bias conditions due to PVE brings direct impact on gate length and therefore influ-ences the gate capacitance. The PVE induced gate capacitance fluctuation is independent of screening effect and should be noticed when the transistor operated in high gate bias.

5.1 : Device Characteristics 81

Figure 5.2: The summarized gate capacitance fluctuations at different gate bias for (a) NMOS and (b) PMOS devices,

respectively.

82 Chapter 5 : The Total Effects of All Fluctuations

Figures 5.3(a) and 5.3(b) show the cutoff frequency (fT = vsat/ 2πLg = gm / 2πCG) fluctuations versus the gate voltage for NMOS and PMOS devices, respectively. The results show that RDF play the dominating factor in the σfT at low gate bias, and PVE become the most important parameter when the transistors operate at high gate bias. For RDF, similar to the threshold voltage and gate capacitance fluctuations, it is reduced at high gate bias;

however, the carrier-impurity scattering alters the saturation velocity at high gate bias (high-field); therefore σfT does not diminish in high-field region. The trend of WKF induced σfT

is similar to the RDF, it is larger at low gate bias and reduced at high gate bias; however, the impact of WKF on σfT is insignificant. The PVE-induced σfT is increase with gate bias increased owing to the direct influence of gate length on gate capacitance and PVE become dominates σfT as VG larger than 0.6V due to the screening effect in RDF and WKF fluctuations.

5.1 : Device Characteristics 83

Figure 5.3: The summarized cutoff frequency fluctuations as a function of gate bias for (a) NMOS and (b) PMOS devices,

respectively.

84 Chapter 5 : The Total Effects of All Fluctuations