6.2 Suggestions on Future Work
The nanoscale technology in now facing great challenge and provide abundant chances in new semiconductor application. For more realistic partitions on the shape of metal grains, we can generate them with voronoi diagram as shown in Fig. 6.1. The characteriza-tion and measurement of metal-gate work-funccharacteriza-tion on high-κ dielectrics are required. The multi-layer structure in high-κ/metal gate should be further considered. The future work is suggested from device and circuit viewpoints. From the device viewpoint, study more fluctuation source, such as oxide thickness variation, interface trap variability as shown in Fig. 6.2 [73] and so on are necessary. The simulation of multi variation sources at the same time and find their correlation may be required. Another important issue is the suppres-sion of intrinsic parameter fluctuations. The suppressuppres-sion may result in some drawbacks, which should be addressed properly. From the circuit viewpoint, it is imperative to de-rive a well-established compact model consisting of the randomness effect to realize the nanoscale device and circuit design. The coupled device-circuit simulation may provide an effective way to obtain circuit characteristics without use of compact model. However, there is still a lot of room to improve the numerical stability and numerical method in the coupled device-circuit simulation. To improve the reliability of VLSI circuits and systems, the development of fluctuation suppression approach from circuit topology is necessary.
98 Chapter 6 : Conclusions and Future Work
Figure 6.1: The voronoi diagram generated by MATLAB could beR considered to describe the random shape of metal grains in the LWKF simulation method.
6.2 : Suggestions on Future Work 99
Figure 6.2: The illustration of interface trap at oxide/Si interface.
Oxygen up-diffuse from SiO2 interfacial layer to passivate the O-vacancies in high-κ and generation of positive charges associated with the oxygen vacancies near SiO2/Si interface. The generated positive charge causes Vth
reduction, thinner the SiO2 more efficient to generate O-vacancy near the SiO2/Si interface [73].
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Appendix A
VITA
Name:
Ming-Hung Han, ឌᎮព
Permanent address: No.37, Ln. 121, Xiangcun Rd., Xiangshan Dist., Hsinchu City 300, Taiwan
Date of birth: May 14th, 1983 Place of birth: Hsinchu, Taiwan
Collegiate institutions attended Degree Date of graduate Department of Communications Engineering,
National Chiao Tung University, Hsinchu, Taiwan BS June, 2006 Institute of Communications Engineering,
National Chiao Tung University, Hsinchu, Taiwan MS August, 2010
Master thesis title:
Random-Metal-Gate-Work-Function-Induced Electrical Characteristic Fluctuation in 16-nm-Gate CMOS Devices and Circuits
Awards and Honors:
2009ഏ୮ۏցٙኔ᧭(NDL)ሽᆰ᎖ܗᑓᚵፖૠຌ᧯፹܂ᤁᚌ
2009 International Electron Devices and Material Symposia (IEDMS) Best Paper Award 98ڣ৫ઔߒس࠴ᑻ(Academic Achievement Award)ፖᑻᖂ८
Selected Publication List:
Journal papers
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VITA 117
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VITA 118
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