隨機金屬閘極功函數導致之16奈米金氧半場效應電晶體元件及電路特性擾動之研究

(1)

!

୯!ҥ!Ҭ!೯!ε!Ꮲ!

!

ႝߞπำࣴز܌!

!

ᅺ!γ!ፕ!Ў!

!

ᒿᐒߎឦ႔ཱུфڄኧᏤठϐ16ڼԯߎ਼ъ

൑ਏᔈႝ඲ᡏϡҹϷႝၡ੝܄ᘋ୏ϐࣴز!

!

Random-Metal-Gate-Work-Function-Induced

Electrical Characteristic Fluctuation in 16-nm-Gate

CMOS Devices and Circuits

!

ࣴ!ز!ғǺᗬሎᗶ!

!

ࡰᏤ௲௤Ǻ׵ကܴ!௲௤!

!

ύ! ๮! ҇! ୯! ΐΜΐ! ԃ! Ζ! Д

!

(2)

(3)

ᒿᐒߎឦ႔ཱུфڄኧᏤठϐ16ڼԯߎ਼ъ൑ਏᔈႝ඲ᡏ

ϡҹϷႝၡ੝܄ᘋ୏ϐࣴز!

Random-Metal-Gate-Work-Function-Induced

Electrical Characteristic Fluctuation in 16-nm-Gate

CMOS Devices and Circuits

ࣴ ز ғǺᗬሎᗶ StudentǺMing-Hung Han

ࡰᏤ௲௤Ǻ׵ကܴ റγ AdvisorǺDr. Yiming Li

୯ ҥ Ҭ ೯ ε Ꮲ

ႝ ߞ π ำ ࣴ ز ܌

ᅺ γ ፕ Ў

A Thesis

Submitted to Institute of Communications Engineering College of Electrical Engineering and Computer Engineering

National Chiao Tung University in partial Fulfillment of the Requirements

for the Degree of Master in

Electrical Engineering Augest 2010 Hsinchu, Taiwan

(4)

(5)

!

© Copyright by Ming-Hung Han 2010

All Rights Reserved

!

(6)

(7)

ᒿᐒߎឦ႔ཱུфڄኧᏤठ 27 ڼԯߎ਼ъ൑ਏᔈႝ඲ᡏϡҹϷႝၡ੝܄ᘋ୏ϐࣴز!

!

ᏢғǺᗬሎᗶ ࡰᏤ௲௤Ǻ׵ကܴ!റγ!

୯ҥҬ೯εᏢႝߞπำࣴز܌ᅺγ੤

ᄔ

ा

! ! ! ! ! !

ߎឦ႔ཱུᆶଯϟႝ߯ኧ႔๊ཱུጔ׷਑ޑ٬Ҕ٬ளነᅟۓࡓૈ୼ۯុǴЪ

ςԋࣁڼԯႝ඲ᡏϡҹ໒วόё܈લϐख़ाמೌǶฅԶӧᇙำ΢Ǵߎឦ׷਑

ӧ่඲ޑၸำύǴ඲਱ᗭಈޑελᆶБӛࣁ΋ঁᒿᐒޑၸำǴΞҗܭߎឦ඲

਱௨ӈޑόӕ೷ԋߎឦ߄य़চηኧໆϷႝଽཱུமࡋޑόӕǴ೷ԋόӕޑ඲਱

௨ӈ཮Ԗόӕޑ߄य़ႝՏǴ຾ԶቹៜߎឦޑфڄኧॶǴԜ΋фڄኧॶޑόڰ

ۓǴஒ஥ٰཥޑᘋ୏ٰྍǶࣁΑ௖૸Ԝ΋ᘋ୏ٰྍޑख़ा܄аϷჹܭڼԯϡ

ҹᆶႝၡ੝܄ޑቹៜǴԖձܭЎ᝘ύගрޑԖਏфڄኧᘋ୏ϩ݋ݤǴҁፕЎ

ᔈҔᆾӦьᛥБݤΟᆢࡋႝ඲ᡏϡҹኳᔕБԄǴ२Ӄஒ႔ཱུߎឦಒϩԋ೚ӭ

ޑλ༧Ǵӆ٩ྣόӕ඲਱р౜ޑᐒ౗ǴϩձᒿᐒӦ๏ϒ؂΋λ༧࣬ჹᔈޑф

ڄኧॶǴᙖԜኳᔕр႔ཱུߎឦ߄य़඲਱ᒿᐒ௨ӈޑ౜ຝǴ٠ᙖԜቶݱޑϩ݋

ߎឦ႔ཱུфڄኧᘋ୏ჹܭ 16 ڼԯߎឦ႔ཱུߎ਼ъ൑ਏႝ඲ᡏ੝܄ᄤځႝၡ

ϐቹៜǶ

ӧϡҹ੝܄ᘋ୏Бय़ǴҁፕЎϩ݋Αߎឦ႔ཱུфڄኧᘋ୏ჹܭϡҹᖏࣚႝ

ᓸǴ႔ཱུႝ৒ǴаϷᄒЗᓎ౗ޑ੝܄ᘋ୏Ǵ٠௖૸Αځނ౛ᐒڋǴኳᔕ่݀

ว౜ځჹܭϡҹᖏࣚႝᓸ೷ԋόё۹ౣޑቹៜǴࣴزว౜όӕޑߎឦ඲਱௨

ӈޑελǴኧໆǴаϷՏ࿼ޑόӕǴ཮೷ԋᖏࣚႝᓸॶޑᘋ୏ǴԜ౜ຝᙖҗ

೯ၰ߄य़ޑႝՏǴႝ಻ǴаϷૈ஥ޑϩѲளаှញǶӧϡҹ႔ཱུႝ৒аϷᄒ

Зᓎ౗ޑ੝܄ϩ݋΢Ǵࣴزว౜ߎឦ႔ཱུфڄኧᘋ୏ѝ཮ӧ১ϸᙯ୔೷ԋၨ

εޑᘋ୏Ǵӧᆫ໣୔аϷமϸᙯ୔ޑ௃׎ΠǴԜ΋ᘋ୏ஒ཮Ӣ߄य़ႝ಻໣ύ

೷ԋޑࡀጨਏᔈԶ೏ᓸ׭Ƕ

ӧႝၡ੝܄ᘋ୏Бय़ǴҁፕЎ௖૸Αߎឦ႔ཱུфڄኧᘋ୏ჹܭኧՏႝၡа

ϷᜪКႝၡޑቹៜǴӧϸ࣬ᏔႝၡύǴว౜фڄኧᘋ୏ჹܭځۯᒨਔ໔аϷ

ф౗੃઻֡Ԗ࣬྽ޑ੝܄ᘋ୏ቹៜǴځύӧф౗੃઻ύǴᓉᄊф౗੃઻٠ό

i

(8)

ࢂЬाޑф౗੃઻ٰྍǴՠࢂځᘋ୏ࠅࢂΜϩख़ाЪሡाԵໆޑ΋໨ǴќѦǴ

фڄኧᘋ୏ჹܭᓉᄊᒿᐒӸڗ૶Ꮻᡏႝၡޑᓉᄊᚇૻ৒ज़аϷႝࢬ᜔ႝၡޑ

ႝࢬϰଛ֡཮೷ԋᝄख़੝܄ᘋ୏ǴՠӧଯᓎႝၡޑᔈҔύǴӢࡀጨਏᔈޑᜢ

߯Ǵфڄኧᘋ୏ჹଯᓎ୏ᄊ੝܄ࠅό཮೷ԋܴᡉޑቹៜǴа΢ޑࣴزჹܭႝ

ၡ೛ीϷځന٫ϯǴ֡Ԗ࣬྽ޑշ੻Ƕ

ᕴϐǴҁፕЎςϩ݋Αߎឦ႔ཱུфڄኧჹܭႝ඲ᡏޑቹៜǴ٠௖૸Α׎ԋ

ޑচӢϷϩ݋ځङࡕޑނ౛ᐒڋᆶቹៜǶԜፕЎ่݀ჹܭႝ඲ᡏᘋ୏ᓸ׭ϐ

௢՗аϷΠШжႝ඲ᡏ੝܄ᘋ୏ϩ݋ཱུԖଅ᝘Ƕ

ii

(9)

Abstract (in English)

H

igh-κ/metal gate technology has been recently recognized as the key to sub-45-nanometer transistor fabrication because of the improvement of device perfor-mance and reduction of intrinsic parameter fluctuation. However, the use of metal as the gate material introduced a new source of variation. Recently, the averaged work-function fluctuation method was reported to estimate the fluctuation; however, the effective work-function may over- or under- estimate the variability. This thesis computationally study the work-function fluctuation on emerging high-κ/metal gate devices and investigate such variation source induced characteristic fluctuation using experimental validated three-dimension device simulation. In our simulation methodology, we directly partition the device gate metal material into many sub-regions according to the measurement averaged grain size, and then we randomly generate the work-function to each sub-region according to the material properties and map them into device gate for our device simulation. Both the device and circuit characteristic fluctuation are investigated.

(10)

For device characteristics, the fluctuations of threshold voltage (Vth), gate capacitance (CG), cutoff frequency (fT) of complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) devices are comprehensively analyzed. The result show that WKF will induce significant Vth fluctuation (σVth) which can not be neglected. However, the impacts of WKF on device AC (CGand fT) fluctuations are reduced at zero and high gate voltage due to the screening effect of inversion layer or accumulation layer of device.

The implications of device variability in nanoscale transistor circuits are also advanced. The digital circuit (CMOS inverter and static random access memory (SRAM)) and analog circuit (common source amplifier and current mirror) are examined. In CMOS inverter cir-cuit, the fluctuations of rise time, fall time, and delay time fluctuations follow the trend of

Vth fluctuation. The power fluctuations consisting of dynamic power, short circuit power, and static power are estimated. The dynamic power and short circuit power are the most important power dissipation sources. However, the static power fluctuation dominates the total power fluctuation due to the exponential relationship between the leakage current and the Vth. For SRAM, static noise margin fluctuations are explored and the WKF bring sig-nificant variations. For current mirror, the circuit performance variability caused by device mismatch is also clearly shown. However, in common source amplifier, the WKF shows less impact on high frequency characteristic owing to the small gate capacitance fluctuation. It is necessary to include the WKF effects in studying digital circuit reliability; however,

(11)

for high frequency applications, the influence of WKF could be neglected.

In summary, we have studied the random work-function fluctuations on nano-CMOS devices and circuits variability. The result of this study is useful for the next generation CMOS circuits and systems.

(12)

(13)

ᇞ!!!!!!!!!!!!ᖴ!

ᒿ๱ҁፕЎޑֹԋǴӧႝߞπำࣴز܌ޑ؃ᏢғࢲǴΨջஒ֋΋ঁࢤပǴ

ЈύନΑଯᑫǴനख़ाޑࢂૈ୼ӧ೭ออޑٿԃǴᏢډӵՖޑᏢಞǴှ،ୢ

ᚒޑБݤǴаϷΑှᏢคЗᅰǴ೭όࢂ΋ঁಖᗺǴԶ໻໻ࢂΓғޑ΋ঁၸำǴ

Զ೭΋Ϫ೿ाགᖴ೚ӭΓޑ௲ᏤǵЍ࡭ᆶႴᓰǶ!

ӧ؃ᏢޑၸำύǴ२ӃाགᖴࡰᏤ௲௤!׵ကܴԴৣ஼ЈޑࡰᏤǵᡣךᏢ

ಞډᙦ൤ޑ஑཰ޕ᛽ǵࣴزБݤޑ௢ᄟǵаϷࣁᏢೀШࡑΓௗނޑᄊࡋǴᡣ

ךӧݯᏢБݤϷೀШᄊࡋ΢ڙ੻ؼӭǶךाགᖴֆᓄ㮂௲௤Ǵ೾Ϙ଄௲௤Ǵ

஭דඦ௲௤Ǵጰ჏ܴ௲௤ӧ༾ݢᜪКႝၡ೛ी΢ޑޕ᛽໺௤ǴڬൺޱǴഋ߷

ૈԴৣჹܭъᏤᡏϡҹނ౛ޑ஼ЈှᇥǴᗋԖ෠ᜐ੏ד௲௤ӧໆηΚᏢޑᢀ

ۺឲᒡǴ٬ךჹܭъᏤᡏϡҹङࡕޑ୷ҁޕ᛽Ԗ׳ుڅޑᕕှǶќѦӧፕЎ

α၂຾Չය໔Ǵགᖴα၂ہ঩Ҭ೯εᏢႝηπำࣴز܌ޑഋܴণ௲௤Ǵஞޚ

✒௲௤ǴаϷమ๮εᏢπำᆶس಍ࣽᏢسޑ஭ᄃ຦ೌ௲௤๏ϒ೚ӭᆒ៘ޑཀ

ـаϷ਺ϪޑࡰᏤǴᡣךޑፕЎޑϣ৒ૈ୼׳уޑֹ๓Ƕ!

ࡑӧѳՉࣽᏢीᆉჴᡍ࠻ޑٿԃය໔Ǵ੝ձाགᖴԿᗶǵ࠹ሎǵڂⳮǵ

ඁЎǵ۸၈ǵ൤ੇ฻Ꮲߏۆޑྣ៝ᆶᜢᚶǴаϷӕืӳ϶୯ᇶǵ྆๔ǵइᏣǵ

मണǵӧᏢಞၸำύޑϕ࣬ઉ᝝Ǵϕ࣬ᔅԆǴ٠གᖴℱঅǵߪᒆǵৎ፵ǵӵ

ᖚǵࡏ፵ǵ߿ۢӧࣴز΢ޑӝբᆶڐշǴ೭٤ᐕำ೿ుుӧךޑတੇ္Ǵᜤ

аבᚶǶനࡕाགᖴךޑৎΓǴᖴᖴգॺӧङࡕᓨᓨޑЍ࡭ᆶႴᓰǴգॺࢂ

ךനεޑΚໆٰྍǴᡣךӧੲᏩޑਔং๏ךനεޑᜢЈᆶуݨѺ਻Ǵፎᡣך

᝘΢ЈύനుޑགᖴǶ!

ҁ ፕ Ў ག ᖴ Չ ࡹ ଣ ୯ ৎ ࣽ Ꮲ ہ ঩ ཮ ( ी ฝ ጓ ဦ Ǻ NSC-

97-2221-E-009-154-MY2)

ǵဂബӀႝިҽԖज़Ϧљ2008-2011ౢᏢࣴزीฝǵ

аϷѠ᡼ᑈᡏႝၡᇙ೷ިҽԖज़ϦљౢᏢࣴزीฝ2008-2010ϐ࿶຤ံշǶ

! !

ᗬሎᗶ!ᙣᇞ!

ύ๮҇୯ΐΜΐԃΖД!!

୯ҥҬ೯εᏢႝߞπำࣴز܌!

ѳՉᆶࣽᏢीᆉჴᡍ࠻!

vii

(14)

(15)

List of Figures

1.1 The major sources of intrinsic parameter fluctuations: (a) the gate length deviation, (b) line edge roughness, and (c) random dopant fluctuation. The gate length deviation and line edge roughness are form the variation of lithography technology. The random dopant fluctuation comes from the ion-implantation, diffusion and thermal annealing. . . 3

1.2 The intrinsic parameter fluctuation induced threshold voltage fluctuation versus equivalent oxide thickness, the threshold voltage fluctuation can be reduced using high-κ/metal gate technologies. . . . 4

(19)

LIST OF FIGURES xiii

1.3 (a) The SEM pictures and illustration of TiN surface, which containing numbers of grain with various grain orientation. (b) An illustration of crys-tal structure with TiN <200>, and TiN <111> orientation. (c) Each grain orientation has its own strength of dipoles and therefore different work-function. Therefore, the combination of device work-function will become a probabilistic distribution rather than a deterministic value. . . 6

2.1 (a) The metal properties used in this work. For PMOS device, we use Al incorporation to tune the effective work-function. (b) The illustration of band diagram shows the work-function offset of TiN with adding Al is fixed for different orientation, where the green solid lines are original work-function of TiN, after Al incorporation, the work-function becomes larger, as the red dash lines. . . 11

2.2 The formula in AWKF method to calculate the work-function fluctuation for TiN gate containing 4 grains. . . 14

2.3 The simulation flow of MAWKF method. The gate area is partitioned into several square pieces according to the average grain size. The work-function of each partitioned area W Ki is a random value. The summation of W Kiis then averaged to obtain the effective work-function of each tran-sistor and then used for WKF induced characteristic fluctuations estimation. 17

(20)

xiv LIST OF FIGURES

2.4 The obtained probability distributions of TiN work-function for devices with (a) 1, (b) 4, and (c) 256 grains on the gate area. (d) Dependence of TiN metal-gate induced σVth versus the average grain length, where the grain length is square root of grain size. The gate area is 16 nm× 16 nm. . 18 2.5 (a) The residual area which should be considered when estimating

work-functions. (b) Work-function fluctuation induced threshold voltage fluctua-tion versus average grain length with and without taking residual gate area into consideration. . . 20

2.6 The illustration of 3D localized work-function fluctuation simulation. We directly partition the device gate metal material into many sub-regions ac-cording to the grain size. The sub-regions are square or rectangle. There are total 216work-function combinations for 16 grains. . . 23 2.7 The mathematical formulation to describe the 3D localized work-function

structure. . . 24

2.8 Simulation flow chart of 3D localized work-function fluctuation method. We randomly generate the work-function to each sub-region according to the material properties and map them into device gate for our experimen-tally calibrated 3D quantum-corrected device simulation. . . 25

(21)

LIST OF FIGURES xv

2.9 The illustration of coupled device circuit simulation with an inverter circuit as example. The characteristics of the devices and circuit are considered simultaneously. . . 27

2.10 The coupled device circuit simulation flow chart. The characteristics of the devices of the circuit are first estimated by solving the device transport equations. The obtained result is then used as initial guesses in the coupled device-circuit simulation. The nodal equations of the test circuit are for-mulated and then directly coupled to the device transport equations, which are solved simultaneously to obtain the devices and circuit characteristics. . 28

2.11 The (a) inverter, (b) static random access memory, (c) common source am-plifier, and (d) current mirror circuits as examples for digital/analog char-acteristics fluctuation exploration. . . 29

3.1 The device parameters setting and performance used in this work. . . 34

3.2 Extracted nonstrain mobility versus doping concentration at 0.3 and 1 MV/cm vertical field. . . 35

(22)

xvi LIST OF FIGURES

3.3 The ID-VG curves of localized work-function fluctuation method for (a) NMOS and (b) PMOS devices, where the nominal curve with effective work-function of 4.52 eV (NMOS) and 4.76 eV (PMOS) are the red thick symbol lines. The Vth, and the normalized ION and IOF F fluctuations are shown in the inset. . . 39

3.4 Comparison of threshold voltage fluctuation among averaged work-function fluctuation method, modified averaged work-function fluctuation method and localized work-function fluctuation method for grain size equal to (a) 4 nm× 4 nm (the gate area contain integer number of grain case) and (b) 5 nm× 5 nm (the gate area contain non-integer number of grain case). . . . 40

3.5 (a) Threshold voltage distribution as a function of number of TiN <200> contained. The on-state (VG= 0.8 V and VD = 0.8 V) potential distribution of (b) higher Vth and (c) lower Vth devices with the same number of TiN

<200>. . . 41

3.6 (a) The charge distribution and the metal grain distribution extracted from Fig. 3.5(b) at VG = 0.8 V and VD = 0 V. (b) The band diagram in the semiconductor and the metal gate. . . 42

(23)

LIST OF FIGURES xvii

3.7 (a) The charge distribution and the metal grain distribution extracted from control device at VG = 0.8 V and VD = 0 V. (b) The band diagram in the semiconductor and the metal gate. . . 43

3.8 The fluctuated CG-VG curves with (a) localized work-function fluctuation and (b) modified averaged work-function fluctuation methods. The results are significantly different at high gate bias. . . 46

3.9 The summarized gate capacitance fluctuations at different gate bias with modified averaged work-function fluctuation and localized work-function fluctuation method. . . 47

3.10 The charge distributions extract from (a) the largest and (b) the smallest gate capacitance devices. . . 48

3.11 The fluctuated fT-VG curves with (a) localized work-function fluctuation and (b) modified averaged work-function fluctuation methods. The results are significantly different at high gate bias. . . 50

3.12 The summarized cutoff frequency fluctuations at different gate bias with modified averaged work-function fluctuation and localized work-function fluctuation method. . . 51

(24)

xviii LIST OF FIGURES

3.13 The channel surface potential distributions extracted from the devices with (a) averaged effective work-function, (b) the largest and (c) the smallest cutoff frequency in LWKF method. . . 52

3.14 The electron velocity distributions extracted from the devices with (a) av-eraged effective work-function, (b) the largest and (c) the smallest cutoff frequency in LWKF method. . . 53

4.1 (a) The input and output signals for the fluctuated inverter. The magnified plots show (b) the falling and (c) the rising transitions, where the rise time, fall time, high-to-low delay time, and low-to-high delay time are defined. . 58

4.2 Summary of the variations of rise time, fall time, high-to-low delay time, and low-to-high delay time induced by the metal gate work-function fluc-tuation. . . 60

4.3 The nominal values of the inverter circuit’s dynamic power, short circuit power, static power, and total power. The total power is the summation of dynamic power, short circuit power, and static power. . . 62

4.4 The dynamic power, short circuit power, static power, and total power fluc-tuations for the explored inverter with work-function fluctuation. . . 64

(25)

LIST OF FIGURES xix

4.5 (a) The six transistors SRAM (b) The static noise margin is defined as the minimum noise voltage present at each of the cell storage nodes necessary to flip the state of the cell. (c) Graphically, this may be seen as moving the static characteristics vertically or horizontally along the side of the maxi-mum nested square until the curves intersect at only one point. . . 66

4.6 The butterfly curves of SRAM circuit with work-function fluctuation. . . . 68

4.7 The common-source circuit is used to explore the fluctuation of high-frequency characteristics. The input signal is a sinusoid input wave with 0.5 V offset. The frequency is sweep from 1×108 Hz to 1×1012Hz. . . 70 4.8 The (a) frequency response and (b) summarized high-frequency circuit

gain, 3dB bandwidth, and unity-gain bandwidth fluctuations induced by work-function fluctuation. The relation between device and circuit charac-teristics are shown in the inset. . . 72

4.9 The (a) NMOS and (b)PMOS current mirror circuits used in this work. . . . 74

4.10 The summarized normalized IOU T fluctuations induced by work-function fluctuation for NMOS and PMOS current mirrors. . . 75

5.1 The summarized threshold voltage fluctuations for (a) NMOS and (b) PMOS devices, respectively. . . 79

(26)

xx LIST OF FIGURES

5.2 The summarized gate capacitance fluctuations at different gate bias for (a) NMOS and (b) PMOS devices, respectively. . . 81 5.3 The summarized cutoff frequency fluctuations as a function of gate bias for

(a) NMOS and (b) PMOS devices, respectively. . . 83 5.4 Comparison of the variations of (a) fall time, (b) high-to-low delay time,

(c) rise time, and (d) low-to-high delay time with respect to RDF, PVE, and WKF. . . 85 5.5 The (a) dynamic power, (b) short circuit power, (c) static power, and (d)

inverter power fluctuations for the explored inverter with RDF, PVE, and WKF. . . 87 5.6 The summarized static noise margin fluctuations induced by RDF, PVE,

and WKF. . . 89 5.7 The (a) frequency response, (b) 3dB bandwidth, (c) high-frequency circuit

gain, and (d) unity-gain bandwidth fluctuations induced by RDF, PVE, and WKF. . . 91 5.8 The summarized normalized IOU T fluctuations induced by RDF, PVE, and

WKF for (a) NMOS and (b) PMOS current mirror circuits. . . 93 6.1 The voronoi diagram generated by MATLAB could be considered toR

(27)

LIST OF FIGURES xxi

6.2 The illustration of interface trap at oxide/Si interface. Oxygen up-diffuse from SiO₂interfacial layer to passivate the O-vacancies in high-κ and gen-eration of positive charges associated with the oxygen vacancies near SiO₂/Si interface. The generated positive charge causes Vth reduction, thinner the SiO₂ more efficient to generate O-vacancy near the SiO₂/Si interface. . . . 99

(28)

(29)

Chapter 1 Introduction

Intrinsic parameter fluctuation including gate length deviation, line edge roughness, and random dopant fluctuation is a critical issues for nanosclae device. Although the use of high-κ/metal gate is one of important device technology to deal with the aforementioned problem, the metal material introduces a new source of variation, the so-called metal work-function fluctuation (WKF). In this chapter, we first point out some interesting research topics of WKF, then present the background and review recent reports on WKF. Then, we state the purpose of this study. Finally, we outline the whole thesis.

(30)

2 Chapter 1 : Introduction

1.1 Motivation

Evolution of complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) technology in the past 40 years has followed the path of device scaling for achieving density, speed and power improvements [1-6]. However, the fluctuation is intrinsically increased with the scaling of transistor feature size, Fig. 1.1 shows the major sources of intrinsic parameter fluctuations, including the gate length deviation [30,31,37-45], line edge roughness [30,31,37-45], and random dopant fluctuation [7-45]. High-κ/metal gate technology has been recently recognized as the key technology to nanometer transistor, Fig. 1.2 illustrates the use of high-κ/metal gate to suppress the intrinsic parameter fluctuation along the CMOS devices scaling [23]. However, the use of metal as the gate material introduced a new source of variation due to the dependency of metal work-function on the orientation of the metal grains [46-53]. It is crucial to estimated such variation induces devices and circuits characteristic fluctuations.

(31)

1.1 : Motivation 3 6RXUFH*DWH'UDLQ ;3RVLWLRQPPPPP < 3 RV LWL RQ PPPP P

5DQGRPGRSLQJIOXFWXDWLRQ

*DWHOHQJWKGHYLDWLRQ

XP

X

P

*DWHOHQJWKGHYLDWLRQ

XP

X

P

/LQHHGJHURXJKQHVV

D

E

F

Figure 1.1: The major sources of intrinsic parameter fluctuations: (a) the gate length deviation, (b) line edge roughness, and (c) random dopant fluctuation. The gate length deviation and line edge roughness are form the variation of lithography technology [30,31,37-45]. The random dopant fluctuation comes from the ion-implantation, diffusion and thermal annealing [7-45].

(32)

(TXLYDOHQW2[LGH7KLFNQHVV

7KUHVKROG9ROWDJH

)OXF

WXDWLRQ

DX

+LJKNNNNPHWDO*DWH

Figure 1.2: The intrinsic parameter fluctuation induced threshold voltage fluctuation versus equivalent oxide thickness, the threshold voltage fluctuation can be reduced using high-κ/metal gate technologies [23].

(33)

1.2 : The Background and Literature Review 5

1.2 The Background and Literature Review

It is known that metal grains usually grow up to few nanometers in size under tempera-tures used in IC fabrication. The crystal orientation of nanosized metal grain is uncontrol-lable during growth period, the use of metal as gate material will introduce work-function fluctuation [46-53]. Figure 1.3(a) shows the scanning electron microscope (SEM) pic-tures of titanium nitride (TiN) [50], which containing numbers of grain with various grain orientation. TiN is a sodium chloride (NaCl) structure compound consisting of Ti atoms filled in FCC-based lattice with all octahedral sites filled with nitrogen atoms, as shown in Fig. 1.3(b). Since the different grain orientation has its own strength of dipoles, the work-function in each grain orientation is different, as shown in Fig. 1.3(c). The device’s threshold voltage will become a probabilistic distribution rather than a deterministic value. Additionally, the WKF induced characteristic fluctuations are one of major variation source in emerging high-κ/metal gate technology compare with the existance of random dopant fluctuation (RDF) and process variation effect (PVE) [46-53]. However, the sim-ulation using a modified averaged work-function fluctuation method (the details will be examined in the next chapter), which may misestimate the WKF induced device/circuit fluctuations. Although the appearance were also found by other literature [51], they used a compact model method [54], which also could not accurately describe nanoscale grain orientation due to no well established compact model for such small transistor.

(34)

6 Chapter 1 : Introduction D 1D&O 6WUXFWXUH D D D 6XUIDFH'HQVLW\ ! ! D QP 1 7L $WRPVDW WKHVXUIDFH 1D&O 6WUXFWXUH D D D 6XUIDFH'HQVLW\ ! ! D QP 1 7L $WRPVDW WKHVXUIDFH F E 7L1 ! 7L1 !

Figure 1.3: (a) The SEM pictures and illustration of TiN surface [50], which containing numbers of grain with various grain orientation. (b) An illustration of crystal structure with

<200>, and <111> orientation. (c) Each grain orientation has its own strength of dipoles and therefore different work-function [48,49]. Therefore, the combination of device work-function will become a probabilistic distribution rather than a deterministic value.

(35)

1.3 : The Study of this Thesis 7

1.3 The Study of this Thesis

To deal with the aforementioned problems, this work thus highlights the work-function fluctuation on emerging high-κ/metal gate technology on nano CMOS devices and circuits by experimentally calibrated three dimensional (3D) device simulation [23], called 3D lo-calized work-function fluctuation method. The impact of work-function fluctuation on the device’s DC / AC fluctuation are first investigated, and the physical mechanism are dis-cussed. For the device characteristic fluctuations, the localized work-function fluctuation approach has its advantage to capture not only the number of different metal grain orienta-tion but also the grain placement induced device variability. To accurately characterize the device variability in circuits, the circuit characteristic fluctuations are obtained by solving the both device transport and circuit nodal equations called coupled device-circuit simula-tion [55-67]. Unlike the compact model simulasimula-tion approach, the coupled device-circuit simulation approaches solves the device transport characteristics in circuit simulation and therefore provide the most device physics inside circuit fluctuation. The extensive study assesses the fluctuations on circuit characteristics, which can in turn be used to optimize nanoscale MOSFET devices and circuits.

(36)

1.4 Outline

This thesis is organized as follows. Chapter 2 introduces the various simulation methods for studying the effect of metal gate work-function fluctuation. The averaged work-function fluctuation method [48,49], our modified averaged work-function fluctuation method, and experimentally calibrated 3D localized work-function fluctuation device simulation are stated. Chapter 3 compares the modified averaged work-function fluctuation and localized work-function fluctuation methods induced device DC and AC characteristic fluctuations. The physical mechanism to explain the difference of these two method are discussed. The implications of device variability in circuits are explored in Chapter 4, in which the cou-pled device-circuit simulation approach is used instead of compact modeling approach for pursuing best accuracy. Chapter 5 compares the work-function fluctuation with the ran-dom dopant fluctuation and the process variation effect in devices and circuits variability. Finally, conclusions are drawn including suggestions on future work.

(37)

Chapter 2 Methods for Metal Gate Work-Function

Fluctuation Simulation

This chapter presents the simulation technique for work-function fluctuation. The av-eraged work-function fluctuation (AWKF) method which presented in the previous litera-ture [48,49] used a probability density function to estimate the WKF induced Vth fluctu-ation. Such estimation approach is fast, but can not consider the residual blocks during the discretization procedure. We revise and call it modified AWKF (MAWKF) method to estimated the WKF. However, the AWKF and MAWKF methods use the effective work-function for each device, which may lose some physical phenomena. Therefore, the 3D localized work-function fluctuation (LWKF) approach is thus proposed to analyze WKF.

(38)

10 Chapter 2 : Methods for Metal Gate Work-Function Fluctuation Simulation

Figure 2.1(a) shows the material properties used in this work for n-type MOSFET (NMOS) and p-type MOSFET (PMOS) devices [48,49,50,53]. For PMOS device, we use aluminum (Al) incorporation to tune the function to the desired value [53]. Due to the work-function is tuned by the dipole formation of high-κ/SiOx interface, the Al incorporation will give a fixed offset of work-function for different grain orientation, as shown in Fig. 2.1(b).

(39)

11

D

(IIHFWLYH:.H9

:RUNIXQFWLRQH9

3UREDELOLW\

7L1 !

$O

7L1 !

$O

7L1

!

7L1

!

0DWHULDO

3026

1026

'HYLFH7\SH

(IIHFWLYH:.H9

:RUNIXQFWLRQH9

3UREDELOLW\

7L1 !

$O

7L1 !

$O

7L1

!

7L1

!

0DWHULDO

3026

1026

'HYLFH7\SH

E

6L

$O

6L2

_[

+LJKNNNN

(

_YDF

:.RI7L1

:.RI

7L1 $O

(

_&

(

₉L

Figure 2.1: (a) The metal properties used in this work. For PMOS device, we use Al incorporation to tune the effective work-function. (b) The illustration of band diagram shows the work-function offset of TiN with adding Al is fixed for different orientation [53], where the green solid lines are original work-function of TiN, after Al incorporation, the work-function becomes larger, as the red dash lines.

(40)

2.1 The Averaged Work-Function Fluctuation Simulation

Method

The AWKF method [48,49] was reported in 2008. They used an analytical formula to calculated WKF. There are several parameters that have been used in their model and should be introduced. The symbols Φ₁, Φ₂, ...,ΦN and P1, P2, ..., PN are used to iden-tify the work-function values of grains with different orientations and their corresponding probabilities (percentage share of a particular grain orientation in the total population of grains). Assuming fixed probability values (Pi) for different devices (with identical gate metal) is reasonable because these values remain constant for each particular process con-ditions. It is also assumed that the grain size (G) of each type of metal film can be obtained by identifying grain boundaries on transmission electron microscope (TEM) pictures of the surface of the metal-gate. Hence, for a transistor with gate length of L and width W, the total number of grains (N) within the metal-gate area can be calculated as (L/G)× (W/G), assuming square shaped grains, for simplicity. Assuming X₁, X₂, ..., XN to be the ran-dom variables that represent the number of grains with work-function values of Φ₁, Φ₂, ...,ΦN, respectively, one can calculate the effective work-function of the metal-gate (ΦM) as a weighted average of work-function of the all existing grains on the gate. Hence, the

(41)

2.1 : The Averaged Work-Function Fluctuation Simulation Method 13

formula forΦM can be written as follows:

ΦM = X₁ N Φ1+ X₂ N Φ2+ ... + XN N ΦN, (2.1) where the X1

N is the percentage of gate area covered with grains whose work-function isΦ1 and so forth. Given the probabilities and work-function values associated with each grain orientation, the goal is to calculate the mean and standard deviation values for the random variable ΦM. Figure 2.2 shows the calculation formula of TiN gate for gate area contain 4 grains. Since the threshold voltage (Vth) is a linear function of gate work-function, the threshold voltage fluctuation (σVth) is equal to the standard deviation ofΦM.

Notably, the AWKF method in literature [48,49] did not mention how to calculate WKF if the gate area does not contain the integer value of grains. This part will be described in the next section.

(42)

14 Chapter 2 : Methods for Metal Gate Work-Function Fluctuation Simulation 3UREDELOLW\ 3UREDELOLW\ ) ) ) )0 H9 3UREDELOLW\ ₎₎₎₎ 0 H9 ) ) ) )0 H9 1XPEHURI 7L1 ! ) ) ) )0 H9 3UREDELOLW\ ) ) ) )0 H9 3UREDELOLW\ 1XPEHURI 7L1 ! 3UREDELOLW\ 3UREDELOLW\ ) ) ) )0 H9 3UREDELOLW\ ₎₎₎₎ 0 H9 ) ) ) )0 H9 1XPEHURI 7L1 ! ) ) ) )0 H9 3UREDELOLW\ ) ) ) )0 H9 3UREDELOLW\ 1XPEHURI 7L1 ! _u _u ¸¸ ¹ · ¨¨ © § _¸_u ¹ · ¨ © § u ¸ ¹ · ¨ © § u u ¸¸ ¹ · ¨¨ © § _u _u ¸¸ ¹ · ¨¨ © § _u _u ¸¸ ¹ · ¨¨ © § _u _u ¸¸¹ · ¨¨© § _u ¸ ¹ · ¨ © § u ¸ ¹ · ¨ © § _¸_u ¹ · ¨ © § u ¸ ¹ · ¨ © § _¸_u ¹ · ¨ © § u ¸ ¹ · ¨ © § _¸_u ¹ · ¨ © § u ¸ ¹ · ¨ © § N 1 N 1 N 1 ¸¸¹ · ¨¨© §

)

1

Figure 2.2: The formula in AWKF method to calculate the

work-function fluctuation for TiN gate containing 4 grains [48,49].

(43)

2.2 : The Modified Averaged Work-Function Fluctuation Simulation Method 15

2.2 The Modified Averaged Work-Function Fluctuation

Sim-ulation Method

Due to the gate area will not always fortunately include the integer value of grains, we revise the AWKF method and call the MAWKF method to examine the work-function fluctuation. The simulation flow is shown in Fig. 2.3. At first, the gate area is partitioned into several parts according to the average grain size, here we assume the grain is square for simplification. Then the grain orientation of each parts and total gate work-function are randomly generated based on properties of metal as shown in Fig. 2.1(b). The work-function of each partitioned area (W Ki) is a random value. The summation of W Ki is then averaged to obtain the effective work-function of transistor and then used for WKF induced characteristic fluctuations estimation. Figures 2.4(a)-2.4(c) show the probability distributions of work-function for devices with one and nine grains on the gate area. The distribution is similar to the normal distribution as the numbers of grain increases. In other words, in nanoscale transistor with scaled gate area, the distribution is not a normal distribution and therefore the WKF induced σVth may not be a normal distribution as the gate area scales. Figure 2.4(d) examines the dependence of WKF induced σVthversus the average grain length (the square root of grain size) on a 16 nm × 16 nm gate area. The WKF induced σVthincreases significantly as the average grain size increases, which imply

(44)

the importance of controlling metal-gate grain size in reducing WKF effect. The trend of the results is valid with experimental data [47]. Additionally, when the metal grain size is larger than devices gate area, the σVthsaturated due to the number of grain in a device gate area unchanged (contain only one grain). Notably, the different process of gate formulation, gate first or replacement gate, may change the thermal budget and changes the grain size of metal material.

(45)

RIDVLQJOH

WUDQVLVWRU

1 HIIHFWLYH L L

:.

¦

:. 1

.H\SDUDPHWHUV

DWH DUHD$$YHUDJHJUDLQVL]H

3UREDELOLW\3DQGZRUNIXQFWLRQ

:.RIRULHQWDWLRQ

:. :. :. :. :. :. :.L :. « :. :. «

3DUWLWLRQRIGHYLFHJDWHDUHD

$YHUDJHQXPEHURIJUDLQRQGHYLFH

JDWHDUHD1 $*

5DQGRPJHQHUDWLRQRI:.LQHDFK

SDUWVDFFRUGLQJWR3

:.)LQGXFHGGHYLFHFLUFXLW

FKDUDFWHULVWLFIOXFWXDWLRQV

Figure 2.3: The simulation flow of MAWKF method. The gate area is partitioned into several square pieces according to the average grain size [47]. The work-function of each

partitioned area W Ki is a random value. The summation of

W Kiis then averaged to obtain the effective work-function of each transistor and then used for WKF induced

(46)

18 Chapter 2 : Methods for Metal Gate Work-Function Fluctuation Simulation :RUN )XQFWLRQ H9 3U RE DE LOLW\ :RUN)XQFWLRQH9 3U RE DE LOLW \

:RUN)XQFWLRQH9

3UR

ED

ELOL

W\

JUDLQ

JUDLQV

$YHUDJH*UDLQ/HQJWKQP :.) ,Q GXFH G V9 WK P9 *DWHDUHDQP[QP

E

F

_G

D

JUDLQV

Figure 2.4: The obtained probability distributions of TiN work-function for devices with (a) 1, (b) 4, and (c) 256 grains on the gate area. (d) Dependence of TiN metal-gate induced σVth versus the average grain length, where the grain length is square root of grain size. The gate area is 16 nm× 16 nm.

(47)

In the proposed MAWKF method, the results are similar to AWKF method. How-ever, the AWKF method can not consider the residual blocks as shown in Fig. 2.5(a) due to the limitation of the used formula. In the MAWKF method, we also randomly gen-erate the work-function for each residual grain, and consider their weight related to their area when calculating averaged work-function. Figure 2.5(b) compares the AWKF and MAWKF methods with TiN metal gate. The solid triangle and dash cross lines show the results with and without considering the residual area. The trend of σVthis the same as the other; however, there are several flat area existing in the dash line, which may mislead the impact of WKF.

(48)

5HVLGXDO$UHD

:.

_L

:.

«

:.

«

$YHUDJH*UDLQ/HQJWKQP

:.

),

QG

XFH

G

V9

WK

P9

ZFRQVLGHULQJ UHVLGXDODUHD ZRFRQVLGHULQJ UHVLGXDODUHD

*DWHDUHDQP[QP

D

E

Figure 2.5: (a) The residual area which should be considered when estimating work-functions. (b) Work-function fluctuation induced threshold voltage fluctuation versus average grain length with and without taking residual gate area into consideration.

(49)

2.3 : The 3D Localized Work-Function Fluctuation Simulation Method 21

2.3 The 3D Localized Work-Function Fluctuation

Simu-lation Method

The AWKF and MAWKF use the effective work-function, and may lack physically best accuracy [51]. This was pointed out in 2009. They assumed that devices are composed of smaller transistors both in parallel and in series over the gate area. Each small transis-tor with gate electrode has a metal grain with a specific work function and thus its own inversion carrier density in the channel. Using the physical model in [54] for each of the small transistor, then impose Kirchhoff’s law on the resulting mesh of them, and finally nu-merically solve for the device behavior. However, the method may not accurately describe nanoscale grain orientation due to the model probably not work well for such small tran-sistor. Therefore, to characterize the metal-gate induced work-function fluctuation more preciously, we use 3D device simulation to examine such phenomenon, LWKF method. Figure 2.6 illustrates the work-function fluctuation source of CMOS device and the simu-lation method for LWKF. The boundary condition is derived form Gauss’s law:

s

∂φ ∂z − ox

∂φox

∂z = Qs, (2.2)

and the relation of the metal/oxide/semiconductor [1]:

φ = χ + Eg 2e + φf p− Qs tox ox − W K e − φox, (2.3)

(50)

where the φox, tox, and ox are the potential, thickness and dielectric constant of oxide,

s, χ, Eg are dielectric constant, electron affinity, and bandgap of semiconductor, φf p is the difference between intrinsic fermi level and fermi level, and Qs is the fixed charge at silicon/oxide interface. In our structure, since the work-function is a grain area re-lated step function WKχA_i(x,y), as shown in Fig. 2.7, the random grain distribution is therefore considered in LWKF method, where the total work-function on the metal gate =

N i=1

W KχA_i(x, y). Figure 2.8 presents the simulation flow chart of LWKF. To describe the WKF induced characteristic fluctuations, in contrast to AWKF, MAWKF methods or com-pact model [38-45,48,49,51], we directly partition the device gate metal material into many sub-regions according to the grain size [47], and then we randomly generate the work-function to each sub-region according to the material properties and map them into device gate for our experimentally calibrated 3D quantum-corrected device simulation [23]. Two hundred statistically random devices are generated to examine the WKF induced character-istic fluctuations. This method can capture the different work-function of grain orientation position effect, which can not predict by previous methods.

(51)

6XEVWUDWH

' 6

«

Figure 2.6: The illustration of 3D localized work-function fluctuation simulation. We directly partition the device gate metal material into many sub-regions according to the grain size [47]. The sub-regions are square or rectangle. There are total 216work-function combinations for 16 grains.

(52)

6XEVWUDWH

'

6 6XEVWUDWH

'

6 [

\

]

[

\

]

:.F

_$L

[\

Figure 2.7: The mathematical formulation to describe the 3D localized work-function structure.

(53)

3DUWLWLRQPHWDOJDWHLQWR

PDQ\VXEUHJLRQV

VTXDUHRUUHFWDQJOH

5DQGRPO\JHQHUDWH:.IRU

HDFKVXEUHJLRQDFFRUGLQJWR

WKHPDWHULDOSURSHUWLHV

*HQHUDWHGHYLFHVDQG

VROYHDVHWRI'TXDQWXP

WUDQVSRUWHTXDWLRQV

Figure 2.8: Simulation flow chart of 3D localized work-function fluctuation method. We randomly generate the

work-function to each sub-region according to the material properties and map them into device gate for our

experimentally calibrated 3D quantum-corrected device simulation [23].

(54)

2.4 The Coupled Device-Circuit Simulation Technique

Due to lack well-known compact model for 16-nm-gate CMOS devices, the charac-teristics of the devices of the circuit are first estimated by solving the device transport equations. The obtained result is then used as initial guesses in the coupled device-circuit simulation. The nodal equations of the test circuit are formulated and then directly coupled to the device transport equations (in the form of a large matrix that contains both circuit and device equations), which are solved simultaneously to obtain the circuit characteristics. The device characteristics, such as distributions of potential and current density, obtained by device simulation are input in the circuit simulation through device contacts. The illus-tration of coupled device-circuit simulation is shown in Fig. 2.9, here we use an inverter circuit as example. The coupled device-circuit simulation flow chart is shown in Fig. 2.10 [38-45]. Figure 2.11 shows the inverter, static random access memory (SRAM), common source amplifier, and current mirror circuits as examples for digital/analog characteristic fluctuations exploration.

(55)

2.4 : The Coupled Device-Circuit Simulation Technique 27 9'' 9287 9_,1

3026

1026

6XEVWUDWH ' 6

3026

1026

6XEVWUDWH ' 6 6XEVWUDWH ' 6 6XEVWUDWH ' 6 6XEVWUDWH ' 6 6XEVWUDWH ' 6 6XEVWUDWH ' 6 6XEVWUDWH ' 6 6XEVWUDWH ' 6 6XEVWUDWH ' 6 6XEVWUDWH ' 6 6XEVWUDWH ' 6

Figure 2.9: The illustration of coupled device circuit simulation with an inverter circuit as example [38-45]. The characteristics of the devices and circuit are considered simultaneously.

(56)

Figure 2.10: The coupled device circuit simulation flow [38-45,55-67]. The characteristics of the devices of the circuit are first estimated by solving the device transport equations. The obtained result is then used as initial guesses in the coupled device-circuit simulation. The nodal equations of the test circuit are formulated and then directly coupled to the device transport equations, which are solved

simultaneously to obtain the devices and circuit characteristics.

(57)

2.4 : The Coupled Device-Circuit Simulation Technique 29 :/ %/¶ _%/ 9_RXW 9_RXW 9'' 'ULYHU 'ULYHU $FFHVV $FFHVV /RDG /RDG :/ %/¶ _%/ 9_RXW 9_RXW 9'' 'ULYHU 'ULYHU $FFHVV $FFHVV /RDG /RDG 9'' 9287 9,1 9'' 9_,1 3ODQDU 026)(7 9287 & 5 5 9'' 9_,1 3ODQDU 026)(7 9287 & 5 5 9'' 9_,1 3ODQDU 026)(7 9287 & 5 5 9'' 9_,1 3ODQDU 026)(7 9287 & 5 5

D

E

G

F

5RXW 55() 9'' 9''

Figure 2.11: The (a) inverter, (b) static random access memory, (c) common source amplifier, and (d) current mirror circuits as examples for digital/analog characteristics fluctuation exploration.

(58)

2.5 Summary of this Chapter

This chapter has presented the AWKF, MAWKF, and 3D LWKF methods. The AWKF used an analytical formula to calculate WKF. However, the method does not consider the residual area of gate due to the limitation of the formula. The MAWKF method revised the AWKF method to improve the usage of estimating WKF induced characteristic fluctuation. In 3D LWKF method, we directly partition the device gate metal material into many sub-regions and then randomly generate the work-function to each sub-region into device gate for our 3D quantum-corrected device simulation. Additionally, based on the coupled device circuit simulation, the fluctuation of circuit characteristics can be obtained with more device physics inside.

(59)

Chapter 3 Devices Characteristic Fluctuations

This chapter estimates and compares the influences of the work-function fluctuation with MAWKF and LWKF methods on 16-nm-gate planar MOSFET devices. The DC char-acteristics are examined in threshold voltage, on-state current (ION) and off-state current (IOF F). The AC characteristics are investigated in terms of gate capacitance (CG) and cut-off frequency (fT).

3.1 DC Characteristic Fluctuations Comparison

The control devices in this study are the 16-nm-gate bulk planar MOSFETs (width: 16 nm) with amorphous-based TiN/HfO₂gate stacks with an equivalent oxide thickness of 0.8

(60)

32 Chapter 3 : Devices Characteristic Fluctuations

nm and 4.52 eV and 4.76 eV work-functions for NMOS and PMOS devices, respectively. The nominal channel doping concentrations are 1.5×1018 cm−3, the source/drain doping concentrations are 2×1020cm−3, and the lightly doped drain (LDD) doping concentrations are 4×1019cm−3. The junction depth of LDD region is 8 nm. The threshold voltages are calibrated to 250 mV following ITRS roadmap [2,23,25,27]. The details of device setting are shown in Fig. 3.1. The subthreshold slope (SS) could be improved by tuning the channel doping shape profile or metal work-function. The properties of metal are shown in Fig. 2.1(a) and the average grain size is 4 nm × 4 nm [47]. Additionally, to compare fairly the NMOS- and PMOS-induced characteristic fluctuation and eliminate the effect of transistor size on fluctuation, the dimensions of the PMOS devices are the same as those of the NMOS ones.

The mobility model used in our 3D device simulation is is given by:

1 μ = D μsurf aps + D μsurf rs + 1 μbulk , (3.1)

where D= exp (x/lcrit), x is the distance from the interface and lcritis a fitting parameter. The mobility consists of three parts: (1) the surface contribution due to acoustic phonon scattering, μsurf aps = B_E +

C(N_i/N₀)τ

E1/3_(T/T₀₎K, where Ni = NA+ ND, T0 = 300 K,E is the trans-verse electric field normal to the interface of semiconductor and insulator, B and C are parameters which based on physically derived quantities, N₀ and τ are fitting parameters,

(61)

3.1 : DC Characteristic Fluctuations Comparison 33

T is lattice temperature, and K is the temperature dependence of the probability of sur-face phonon scattering; (2) the contribution attributed to sursur-face roughness scattering is

μsurf rs = ((E/Eref) Ξ δ + E 3 η )−1, whereΞ = A + α·(n+p)N_refv (Ni+N1)v , Eref = 1 V/cm is a reference

electric field to ensure a unitless numerator in μsurf rs, Nref = 1 cm−3 is a reference dop-ing concentration to cancel the unit of the term raised to the power v in the denominator of Ξ, δ is a constant that depends on the details of the technology, such as oxide growth conditions, N₁ = 1 cm−3, A, α, and η are fitting parameters; (3) and the bulk mobility is μbulk = μL(_TT

0)

−ξ_{, where μ}

L is the mobility due to bulk phonon scattering and ξ is a fitting parameter. The parameters of mobility were calibrated with the measurement of experimentally fabricated CMOS devices [23], as shown in Fig. 3.2.

(62)

1026

9

_W

P9

3026

66 P9GHF

,

_RII

Q$PPPPP

,

_RQ

PPPP$PPPPP

3HUIRUPDQFH

)RU/23

1026

9

_W

P9

3026

66 P9GHF

,

_RII

Q$PPPPP

,

_RQ

PPPP$PPPPP

3HUIRUPDQFH

)RU/23

[

_FP

/''GRSLQJ

$URXQG/

_J

QPWRPDLQWDLQ

VXEWKUHVKROGOHDNDJH

-XQFWLRQGHSWK

H9 1026H9 3026

:RUNIXQFWLRQ

[

_FP

6'GRSLQJ

QP(27+I2

2[LGHWKLFNQHVV

[

_FP

&KDQQHOGRSLQJ

[

_FP

/''GRSLQJ

$URXQG/

_J

QPWRPDLQWDLQ

VXEWKUHVKROGOHDNDJH

-XQFWLRQGHSWK

H9 1026H9 3026

:RUNIXQFWLRQ

[

_FP

6'GRSLQJ

QP(27+I2

2[LGHWKLFNQHVV

[

_FP

&KDQQHOGRSLQJ

Figure 3.1: The device parameters setting and performance used in this work.

(63)

Figure 3.2: Extracted nonstrain mobility versus doping concentration at 0.3 and 1 MV/cm vertical field.

(64)

Figure 3.3 shows the threshold voltage fluctuation, the normalized on- and off-state current fluctuations (σION and σIOF F) induced by WKF of NMOS and PMOS devices with LWKF method, the values are 36.7 mV, 5%, 57%, 42.5 mV, 10%, 46%, respectively. We note that the Vthis determined form the current criterion when drain current is 10−7 A. The ION is the drain current at on-state (gate voltage (VG) and drain voltage (VD) are equal to 0.8 V), and the IOF F is the drain current at off-state (VG = 0 V and VD = 0.8 V). Figure 3.4 compares σVth among AWKF, MAWKF method and LWKF methods for the gate area is 16 nm× 16 nm with grain size equal to 4 nm × 4 nm (gate area contain integer number of grain), and 5 nm× 5 nm (gate area does not contain integer number of grain). The AWKF and MAWKF method significantly underestimated the WKF induced σVth. To further un-derstanding the physical mechanism of WKF induced device characteristic fluctuations; we investigate the on-state potential, charge distribution at channel surface, and band diagram. Due to the probabilistic distribution of work-function, the effective work functions of 200 devices are not a deterministic value and results in device to device performance variation. This variation can also estimated by MAWKF method. However, the position of different metal grain orientation position effect can further induce device characteristic fluctuations. Figure 3.5(a) shows the large-scale statistically computed results of Vth as a function of the number of TiN <200> (higher work-function) contained for NMOS device. From the number of high work-function grain orientation point of view, the effective work-function

(65)

of a single device increases as the number of TiN <200> increases, result in a higher Vth. Moreover, it is found that even for devices with the same numbers of TiN <200> inside the gate, the effect of nanoscale grain orientation position induces different fluctuations of characteristics in spite of there being the same number of TiN <200>. To explore the grain orientation-position-induced Vth fluctuation, the on-state potential distributions with con-taining nine TiN <200> but different position inside the gate are investigated, as shown in Figs. 3.5(b) and (c). The potential distributions are at the channel surface. For a device with TiN <200> located near the source and at the middle of channel, the corresponding potential distributions are significant decreased in these areas, which significantly changes the electron conducting path and induce larger Vth. The importance of grain position effect is found for the first time. Figure 3.6(a) presents the charge distribution of the channel sur-face extracted from Fig. 3.5(b) at VG= 0.8 V, and VD= 0 V; we can clearly find the charge distribution is strongly governed by different local work-function of gate metal orientation, such phenomenon can not be predicted by MAWKF method. The MAWKF model uses an effective work function for each device to calculate the performance, which assumes a uniform inversion charge density at the channel surface. The difference between these two methods can be considered in terms of the band diagram, as shown in Fig. 3.6(b) and Fig. 3.7, which leads to different substrate band bending and varying throughout the channel. Since the threshold voltage is determined by the work-function difference between metal

(66)

and semiconductor [1], as shown below:

Vth = (|QSD(max)| − Qss)/Cox+ φms+ 2φf p, (3.2) where the|QSD(max)| is the maximum charge density of depletion region, Qssis the oxide surface charge, Coxis the oxide capacitance, φmsis work-function difference between metal and semiconductor, and 2φf pis the surface potential. The difference of threshold voltage fluctuation is therefore result form work-function difference induced by the localized metal grain. Since the on-state channel inversion charge density distribution is above1019cm−3, the charge screening length in the channel is about several nanometers. Therefore, for nanoscale grains, the band edges in the channel will be affected by the grain directly above a given region, and will fluctuate throughout the channel surface.

(67)

9

_*

9 ,

'

$

9

_*

9 ,

'

$

1026

3026

VVVV9

_WK

P9

VVVV9

_WK

P9

VVVV,

₂₁

VVVV,

₂₎₎

VVVV,

₂₁

VVVV,

₂₎₎

D

E

Figure 3.3: The ID-VGcurves of localized work-function fluctuation method for (a) NMOS and (b) PMOS devices, where the nominal curve with effective work-function of 4.52 eV (NMOS) and 4.76 eV (PMOS) are the red thick symbol lines. The Vth, and the normalized ION and IOF F fluctuations are shown in the inset.

(68)

9

WK

)O

XFWXDWL

RQ

P9

$:.)_0$:.) /:.)

9

WK

)OX

FW

XDW

LRQ

P9

$:.)_0$:.) /:.)

1026

3026

D

E

1026

3026

Figure 3.4: Comparison of threshold voltage fluctuation among averaged work-function fluctuation method, modified averaged work-function fluctuation method and localized work-function fluctuation method for grain size equal to (a) 4 nm× 4 nm (the gate area contain integer number of grain case) and (b) 5 nm× 5 nm (the gate area contain

(69)

3.1 : DC Characteristic Fluctuations Comparison 41 1XPEHURI7L1!FRQWDLQHG 9WK 9 3RWHQWLDOH9 3RWHQWLDOH9 7L1 ! :. H9 7L1 ! :. H9

D

E

F

6 '

9

_WK

P9

6 '

9

_WK

P9

6 '

Figure 3.5: (a) Threshold voltage distribution as a function of number of TiN <200> contained. The on-state (VG= 0.8 V and VD = 0.8 V) potential distribution of (b) higher Vthand (c) lower Vthdevices with the same number of TiN <200>.

(70)

42 Chapter 3 : Devices Characteristic Fluctuations [_FP _[ _[

6RXUF

H

'U

_DLQ

(_YDFB0

$

$¶

7L1 !:. H9 7L1 !:. H9 7L1 !:. H9 7L1 !:. H9

%

%¶

D

E

(YDFB6 H9

$

$¶

%

%¶

()B06 (& (9 :.H9 :.H9 6HPLFRQGXFWRU(OHFWURQ$IILQLW\H9 %DQGJDS H9

Figure 3.6: (a) The charge distribution and the metal grain distribution extracted from Fig. 3.5(b) at VG= 0.8 V and VD = 0 V. (b) The band diagram in the semiconductor and the metal gate.

(71)

E

(_& (₉ (_YDFB0 (_YDFB6 $YHUDJHG(IIHFWLYH:RUN)XQFWLRQ 6HPLFRQGXFWRU(OHFWURQ$IILQLW\H9 (_)B06 %DQGJDS H9

D

[_FP _[ [

6 RXUFH

'UDLQ

$

$¶

(IIHFWLYH

:RUN)XQFWLRQ

%

%¶

H9

$

$¶

%

%¶

Figure 3.7: (a) The charge distribution and the metal grain distribution extracted from control device at VG= 0.8 V and VD = 0 V. (b) The band diagram in the semiconductor and the metal gate.

(72)

3.2 AC Characteristic Fluctuations Comparison

In this section, the device AC characteristics including CG and fT are investigated. The MAWKF and LWKF fluctuated CG-VG curves are compares in Figs 3.8(a) and (b). And the summarized gate capacitance fluctuation (σCG) at different gate bias are shown in Figs 3.9. At zero gate bias or negative gate bias, the accumulation layer screens the impact of WKF. Additionally, at low gate bias, the total capacitance decreases because of the in-creased depletion region. The associated value of CG fluctuation is small. The capacitive response is then dominated by increment of inversion in the moderate inversion. The de-vice characteristics are then impacted by work-function fluctuated electrostatic potentials. However, if the high VG is achieved, the result are significant different between these two methods. In MAWKF method, the capacitive response becomes dominated by the inversion layer, the impact of the work-function difference on the device electrostatics is screened by the inversion layer itself. The variation of capacitance is now again becomes the variation of gate oxide. The impact of WKF induced electrostatic potential variations is therefore bringing less impact on channel surface. In LWKF method, although the inversion layer screen effect also happened, the grain position effect still influences the charge distribution of inversion layer for different device, as shown in Figs 3.10, results in a larger σCG. The importance of LWKF method are also shown for device AC characteristics. However, it should be notice that even in the result of LWKF method, the largest fluctuation of σCG

(73)

3.2 : AC Characteristic Fluctuations Comparison 45

is less than 3% of it’s nominal value. The WKF bring less impact on gate capacitance fluctuation, it is different with device DC characteristic fluctuations.

(74)

9

_*

9 &

*

[

I)

9

_*

9 &

J

[

I)

/:.)

0$:.)

D

E

Figure 3.8: The fluctuated CG-VGcurves with (a) localized work-function fluctuation and (b) modified averaged work-function fluctuation methods. The results are significantly different at high gate bias.

(75)

3.2 : AC Characteristic Fluctuations Comparison 47

V&

J

[

I)

9

_*

91RPLQDO&

_*

[

I)

9

_*

91RPLQDO&

_*

[

I)

9

_*

91RPLQDO&

_*

[

I)

/:.)

0$:.)

Figure 3.9: The summarized gate capacitance fluctuations at different gate bias with modified averaged work-function fluctuation and localized work-function fluctuation method.

(76)