All the device fabrications mentioned in this thesis were accomplished at the National Nano Device Laboratories (NDL).
2-1 Device Fabrication and Process Flow
In this chapter, we take the asymmetric PMOSFET with drain-side only halo as an example to illustrate the process flow in Fig. 2.1.
The devices were fabricated on 6-inch n-type bare Si wafers with resistivity of 15~25 ohm-cm. N-type well was formed by phosphorus ion (P+) implantation (at 120 keV, 7.5E12 cm-2), Vth was adjusted by arsenic ion (As+) implantation (at 80 keV, 1E13 cm-2), anti-punchthrough implantation was formed by P+ implant (at 120 keV, 4E12 cm-2), and channel stop implantation for local oxidation of silicon (LOCOS) isolation was done by As+ implant (at 120 keV, 3E12 cm-2).
After the above standard MOSFET LOCOS and n-well processes, thermal gate oxide with a thickness of 3 nm was grown in N2O ambient, followed by a 170 nm-thick undoped polycrystalline silicon (poly-Si) deposition performed in a vertical furnace by low-pressure chemical vapor deposition (LPCVD). Subsequently, undoped
poly-Si was implanted with boron-fluoride ion (BF2+) at 15 KeV, 5E15 cm-2. Then a 50 nm-thick LPCVD TEOS oxide was deposited as a hard mask layer.
The DP technique uses two masks denoted as G1 and G2, respectively, as shown in Fig. 2.2 to define the gate. During fabrication the gate etching steps were done with a Lam-TCP9400 operated with end point detection mode. An annealing was employed using rapid thermal anneal (RTA) at 900 oC for 10 second (s) after the G1 formation process. Then asymmetric source and drain extensions were formed separately after G1 and G2 definitions, respectively. Meanwhile, according to the demand of experimental conditions, the 45 o tilted angle halo-implantation was done with As+ (at 15 to 30 keV, 5E12 cm-2) at drain side only, as shown in Fig. 2.1. For the split with source-side-only halo, such implant was done immediately after the source-side extension implant. Additional split with symmetrical halo structure was also fabricated. For that split and control samples which was with symmetric S/D extension and no halo implemented, the S/D extension and halo (optional) implants were done together after G2 gate definition.
After halo implantation, 100 nm sidewall spacer was formed with LPCVD TEOS oxide, followed by deep S/D implant with BF2+ (at 40 keV, 5E15 cm-2).
Afterwards, the regions of substrate windows were formed and implanted with P+ (at 40 keV, 5E15 cm-2). Then the wafers were annealed using spike rapid thermal anneal
(SRTA) at 1000 oC to activate the dopants in the preceding implantation processes.
Finally, standard backend flow was executed to complete the fabrication.
The major split conditions explored in this work are listed in Table 2.1. Other implant conditions, including well implantation, threshold voltage adjustment implantations, channel stop implantation, and anti punch-through implantation are shown in Table 2.2.
2-2 Feasibility of the Double Patterning Technique
After finishing the G1 and G2 gate etching steps, we employed in-line scanning electron microscope (SEM), and focused ion-beam (FIB) SEM imaging techniques to check the test structures as well as the practical gate electrodes which were formed by either DP or single patterning technique. For all lithographic steps, we used an I-line stepper to generate the photoresist (PR) patterns, and the design of the DP masks is shown in Fig. 2.2. In this figure, the G1 mask covers the right side of the active region which is capped with the poly-Si as the gate material, and then the G2 mask covers the left side of the active region. After the two-step gate mask processes, the overlapped region of the G1 and G2 masks defines the gated region, and the gate length can be smaller than the resolution limit of single patterning technique (~0.35 μm) with conventional I-line steppers.
Figure 2.3 shows the gate length images which were formed by conventional single patterning technique. In the pictures, in order to evaluate the gate length error caused by the process and instrumental factors, we compare the difference between the designed or nominal length (Lmask) on mask and the practical physical length (Lgate) of the etched poly-Si gate measured by the in-line SEM.:
mask gate
In Fig. 2.3, it is observed that the error of gate length formed with conventional I-line scheme is less than 10 %. Nonetheless, the feature size of the line is larger than 0.3
m. Figure 2.4 shows that the shortest gate length is around 32 nm with designed length of 50 nm. Figures 2.5 ~ 2.12 show the in-line SEM images of the etched poly-Si gates formed with the DP method with Lmask ranging from 60 to 300 nm. From these figures it is confirmed that the DP can significantly shrink the feature size of the poly-Si gate down to sub-100 nm regime. Generally, the error percentage increases with decreasing Lmask. Such trend is reasonable as far as the overlay accuracy of the i-line stepper is concerned. As shown in Table 3, the overlay accuracy is larger than 45 nm. This implies that the gate length designed below 80 nm is out of control and difficult to reproduce. Anyway, the present DP method is useful for generation of line patterns down to 80 nm with reliable control of critical dimensions, as shown in Fig.
(2-1) (2-2)
2.13.
2-3 Electrical Measurement Setup
In this study, the electrical characteristics of the fabricated devices were evaluated by using a precision semiconductor parameter analyzer HP 4156A for I-V measurements and an LCR meter HP 4284 for C-V measurements. The device characteristics were measured on the 6 inch probe station at various gate voltages (Vg
= 1 ~-2V) and drain voltages (Vd = 0 ~ -2V). Fig. 2.14 shows the measurement setup used in this experiment.
In addition to basic electrical measurements, we also analyze the device degradation and reliability, including test on static negative-bias-temperature instability. Details about the test conditions are given in the thesis as the results are presented.
Table 2.1 Split conditions of the PMOSFETs fabricated with the DP process.
Symmetric Extension BF2+
With Drain Halo Implantation
As+ / Title 45° Twist 27° Drain halo implantation 5 x1012cm-2, 30 keV S/D Extension 5 x1014cm-2, 10 keV Type
D
With S/D Halo Implantation
As+ / Title 45° Twist 27° S/D halo implantation 5 x1012cm-2, 30 keV
Asymmetric S/D Extension BF2+
Type
B without halo implantation
Source Extension 5 x1014cm-2, 10 keV Drain Extension 5 x1014cm-2, 5 keV
Table 2.2 Other major implantation conditions used in the PMOSFET fabrication.
Table 2.3 Specifications of Canon FPA-3000i5+ Stepper.
(Data are courtesy of NDL)