3-1 Nano-Scale Device Performance and End-Point-Detection Issue
Figure 3.1 shows the cross-sectional view of a poly-Si gate with Lmask of 0.1 μm.
The figure shows that the practical gate length Lgate is measured to be 85 nm. Figure 3.2 shows the characteristics of electrical measurements performed on this device.
The device was fabricated with source extension formed with BF2+ implant (at 10 keV, 5E14 cm-2), drain extension formed with BF2+ implant (at 5 keV, 5E14 cm-2), and drain-side-only halo formed with As+ implant (at 30 keV, 5E12 cm-2, 45 degree).
With the aid of the proposed DP method, well-behaved characteristics are demonstrated in the nano-scale device.
One issue encountered in our previous work [1] is illustrated in Fig. 3.3(a), which schematically shows the layout of original device design regarding G1 and G2 masks mentioned in Chap. 2. Figure 3.4 shows the cross-sectional view of a device taken in the prior study [1]. In the figure we can observe the substrate recess at the right side of the poly-Si gate. Such a phenomenon was induced during the second poly-Si etching step (with G2 mask) and had been identified to be caused by the ineffectiveness of end-point detection (EPD) technique. In the original mask design
shown in Fig. 3(a), most of the poly-Si film area will be removed during the first etching step. Therefore the EDP signal is too weak to be detected in the second etching step. The mismatch in etched profile results in high series resistance and low driving current [1]. To address this issue, in this work we modify the G1 mask by adding additional dummy regions, as shown in Fig. 3.3(b), so the total area of the poly-Si film present during the second etching step is sufficiently large for effective EPD. As the new scheme in mask design is implemented, the above issue is well resolved as evidenced in Fig. 3.1.
3-2 Basic Electrical Characteristics
Basic electrical characterization was performed on four types of devices fabricated with the DP process, as shown in Figs. 3.5 and 3.6 and denoted as Types A, B, C, and D, respectively. Details about the implant conditions of extension and halo for the four splits of devices are listed in Table 2.1. In brief, Type A has symmetrical S/D extensions, Type B has asymmetrical S/D extensions, Types C and D both have the same symmetrical S/D extensions as that of Type A, but Type C has on-side-only halo while Type D has symmetrical halo.
Figure 3.7 shows the CV curves of the PMOSFET measured at 100 kHz. The electrical effective oxide thickness (EOT) is 4.2 nm as estimated from the inversion
capacitance, in good agreement with the physical thickness of 3.5 nm. The result also indicates that the poly depletion effect is negligible.
3-2-1 Electrical Characteristics of P-channel MOSFETs with Asymmetric S/D Extension
In this section, we analyze and compare the electrical characteristics of Type A and Type B shown in Figs. 3.5 (a) and (b), respectively.
As transistors are made smaller, the junctions that form the source and drain regions of the transistor must be made shallower in order to improve performance and provide adequate breakdown characteristics. In particular, the region known as the drain extension must be extremely shallow to suppress the short-channel effects. Figures 3.8(a) and (b) show and compare the transfer and output characteristics, respectively, of Type A and Type B devices with channel length of 0.1 μm and width of 10 μm. With a shallower drain extension in the Type-B device, we can see in Fig. 3.8(a) that subthreshold swing of this device is slightly improved as compared with the Type-A sample. Nonetheless, the shallower drain also introduces additional resistance, resulting in degraded drive current performance illustrated in Fig. 3.8(b). Impact of the increased series resistance also reflects on the transconductance (gm) performance, as shown in Fig. 3.9.
We also inspect threshold voltage (Vth) as a function of channel length with
(W/L)．10nA, where L is the channel length and W is the channel width. The figure shows that one of the familiar short-channel effects, the Vth roll-off phenomenon, owing to the charge sharing at source and drain junctions [25].
While the drain extension becomes shallower for the Type B split as compared with the Type A, the roll-off is improved due to the decreased depletion region which reduces the charge sharing effect.
Figure 3.11 shows the extracted external S/D resistance of the two types of devices. Extraction of the parameter is based on the method proposed and developed previously [25]. From the results, we confirm that the shallower junction indeed results in a larger parasitic resistance,.
3-2-2 Electrical Characteristics of P-channel MOSFETs with Halo-implant
In this section, we compare and analyze the electrical characteristics of Type A, Type C, and Type D devices shown in the Fig. 3.5(a), Fig. 3.6(a), and Fig.
3.6(b), respectively. Major differences among those types of devices are the implementation of halo.
Figures 3.12, 3.13, 3.14 show the transfer characteristics of Types A, C, and D devices, respectively, with various channel length ranging from 80 nm to 10 μm.
When the channel length scales down to 80 nm, although the use of halo
becomes obvious and results in degradation of subthreshold characteristics in the devices This indicates the S/D extension condition used in the fabrication of these types of devices needs further optimization. The device characterized in Fig. 3.2 was fabricated with a shallower drain extension as compared with the Types, A, C, and D devices, and drain-side-only halo. As a result, the bulk punchthrough is dramatically suppressed.
Figure 3.15 shows and compares the Vth roll-off characteristics of the three splits of devices with channel length ranging from 0.1 to 10 μm. We can observe that devices with halo shows improved control over short-channel effect, especially for the Type D devices which have symmetrical halo. This is reasonable since halo increases the substrate doping locally near the edge of the channel.
Figure 3.16 shows the DIBL effects. While a high drain bias is applied to the short-channel device, the depletion region of the drain junction further penetrates into the channel, leading to lowering of potential barrier height at channel surface [25]. In the figure it is clearly seen that the implementation of halo can reduce DIBL significantly, especially for the Type-D split. Nonetheless, the halo may degrade the drain current due to degradation carrier mobility in the channel [25].
Figure 3.17 shows that the on-current of devices as a function of the channel length. It can be seen that the Type D and Type A devices have the lowest and the
highest current, respectively. With one-side-only halo, Type C devices show improved performance as compared with the Type D ones.
3-3 Negative Bias Temperature Instability Characteristics
Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design, because of the use of ultra-thin gate oxides as well as the rise in operation temperature.
In general, the standard reaction-diffusion (R-D) model [29] is used to explain NBTI phenomenon. The physical model is based on modification in structure of the SiO2/Si interface due to electrochemical reactions during the stress, as schematically depicted in Fig. 3.18. The mechanism of NBTI electrochemical reactions is given as follows:
where ≣SiH is a hydrogenated trivalent silicon, p+ is a hole at the silicon surface, and Si3≣Si* is an interface trivalent silicon atom (Nit) with an unsaturated (unpaired) valence electron (a dangling bond) at the Si–SiO2 interface, H+ is a positively charged interstitial hydrogen ion, and O3≣Si+ is a positive fixed oxide charge (Nox) in the oxide. Therefore, Equation (3-1) is used to explain for Nit generation while Equation (3-1) (3-2)
(3-2) for Nox generation. It should be noted here that (3-1) and (3-2) are reversible.
NBTI effect damages the PMOSFETs by causing the shift of Vth, and the degradation of saturation current and transconductance. Vth shifts during NBT stress are modeled by considering the generation of interface defects [30] and the generation of positive charges relating to the diffusion of released hydrogen into the gate dielectric [31], induced by the injection of holes presenting at the interface. NBT stress causes a negative shift of Vth (ΔVth) that shows a power-law dependence on stress time:
n
Vth A t
,
where A is a constant and t is the stress time. The exponential value, n, of the power-law equitation is around 0.25 when diffusion-controlled electrochemical reactions are considered [32, 33].
In this thesis we also investigate the static NBTI of the fabricated p-MOS devices.
Figure 3.19 shows and compares the Vth shift-versus-stress time curves at 125 oC for Type A devices with various channel length of 0.14 μm, 1μm and 10 μm. We can observe that, at a fixed stress time, the Vth shift is larger for the device with a longer length. For the above channel length-dependent NBTI phenomenon, fluorine atom incorporation may play a role. Note that, in these devices, gate and S/D were doped with BF2+ implant. It has been shown previously that improvement in interfacial stability can be achieved with F incorporation, attributing to relaxation of the strain at
(3-3)
the interface or replacement of the Si–H bonds with the more robust Si–F bonds [34].
Moreover, additional fluorine atoms diffusing from the gate-S/D extension overlap regions to the channel region alleviate the distortion of the strained Si–O–Si or Si–N–Si bonds and reduce the interface states and fixed oxide charges in the fabrication process [35]. Consequently, the short-channel devices may have more Si-F bonds at Si/SiO2 interface in the channel as compared with the long-channel ones, as indicated in Fig 3.20, because of the shorter distance between the channel center and the S/D extension. Figure 3.21 shows that subthrehold characteristics for Type A devices with channel length of 0.14 μm and 10 μm measured at 125 oC, 25 oC, before and after stress under gate voltage -3.3 V for 5000 seconds. As shown in Fig. 3.21, we can see that the SS is slightly smaller for the short-channel device before stress, while the difference becomes even larger after stress. This evidences the effect of fluorine atoms from S/D extension in reducing the interface states and improving the NBTI immunity for the short-channel device as compared with the long-channel one. As a result, long-channel devices have more interface states, which the distance between the channel center and the S/D extension of device is too long to generate more Si-F bonds at Si/SiO2 interface in the channel, exhibit a larger value of ΔVth under NBTI stressing.
Figure 3.22 shows and compares theΔVth -versus-stress time curves for Type A
device with channel length of 0.14 μm stressed at 25 oC, 75 oC and 125 oC. Figure 3.23 shows and compares the Vth shift-versus-stress time curves for Type A device at 125oC and channel length 0.14 μm with various stress gate voltage -2.3V, -2.8V, and -3.3V. We can observe that a higher temperature or gate voltage shows higher Vth shift.
While NBT stress at higher temperature, it may accelerate the release of hydrogen from the interface by breaking the Si-H bonds and form H+ (see (3-1)) [29]). It may also accelerate the hydrogen ions diffusion away from the interface into the oxide bulk where some are trapped, causing more Vth shift. Figure 3.24 shows and compares theΔVth-versus-stress time curves for Type A and Type D devices with channel length of 0.14 μm at 25 oC, 75 oC and 125 oC. Figure 3.25 shows and compares the Δ Vth-versus-stress time curves for Type A and Type D devices at 125 oC and channel length of 0.14 μm with various stress gate voltage -2.3V, -2.8V, and -3.3V. Basically the difference between the two splits of devices is small, indicating that the implementation of the halo in the devices would not results in a great impact.
Chapter4 Conclusion and Future Work
4-1 Conclusions
In this thesis, we have successfully fabricated and studied p-channel MOSFETs with channel length down to 85 nm with an I-line double patterning process.
Evaluation and comparison of device characteristics among different splits of devices having symmetric or asymmetric S/D extension and halo structures have also been done. Several results are summarized as follows:
1. Capability of the developed double patterning process in forming asymmetrical S/D structure is demonstrated. Devices with a shallower extension depth can help alleviate the short-channel effects such as Vth roll-off and bulk punchthough. Nonetheless, it may also introduce additional resistance, resulting in degraded drive current performance.
2. Devices with halo-implanted structures can improve DIBL effect as well as bulk punchthough. This is reasonable since halo increases the substrate doping locally near the edge of the channel to suppress the depletion region of the drain junction and thus prevent further penetration of electric field into the channel.
However, the halo may degrade the drain current due to degraded carrier
mobility in the channel.
3. PMOSFETs’ NBTI results show that NBT stress aggravates characteristics of devices. While stress at a higher temperature, it may accelerate the release of hydrogen from the interface by breaking the Si-H bonds. It may also accelerate the hydrogen ions diffusion away from the interface into the SiO2 where some are trapped, causing more Vth shift. However, as compared with the long-channel devices, the short-channel devices show less ΔVth under NBTI stressing. This is attributed to the formation of more Si-F bonds at Si/SiO2
interface in the channel due to the diffusion of fluorine atoms from the S/D extension, thus reducing the interface states and improving the NBTI immunity.
Because of a much shorter distance for the above diffusion process, the short-channel devices exhibit a much improved immunity than the long-channel ones. Furthermore, a comparison has been made between the devices with and without halo implemented. The results indicate that the implementation of the halo in the devices would not result in a great impact as long as NBTI stressing is concerned.
4-2 Future Work
There are some important and interesting topics that are valuable for the future
1. In order to reduce the bulk punchthrough and DIBL effects, it is important to optimize the conditions of halo implantation and S/D junction regions by using TCAD simulation.
2. To raise the output current, we can use silicide to decrease junction resistance.
3. Beside NBTI, we can measure channel hot carrier (CHC) and drain avalanche hot carrier (DAHC) to analyze devices characteristics.
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Fig.1.1. Cross sectional view of a device with nominal gate length (Lmask ) of 0.2 μm fabricated with I-line DP process developed by our group in previous year [1]. Si recess resulted in the 2nd poly etch step was found at one side of the gate.
Si recess
Silicon
Undopand Poly-Si (170nm) Oxide (3nm)
Silicon Poly-Si (BF2 doping, unannealing)
Oxide
Hard mask Oxide (50nm)
Silicon Poly-Si Oxide
Hard mask Oxide
Silicon
Poly-Si (after annealing ) Oxide
Poly-Si
Fig.2.2. Design of the double-patterning masks, (a) Top view and (b) Cross-sectional
(a) Top view (b) Cross-section view
Hard Mask Oxide Poly -Si Gate Oxide
Silicon
PR (defined by G1 mask) Hard Mask Oxide
Type: Single Patterning
Fig. 2.3. Top-view SEM images of poly-Si gates formed by single patterning process.
0.35 m
Type: Double Patterning
Type: Double Patterning
Fig 2.4. SEM image of a poly-Si gate with 32 nm in line width, formed by DP process with designed line width of 50 nm.
Fig. 2.5. Top-view SEM image of a poly-Si gate with designed line width of 50 nm
Fig. 2.5. Top-view SEM image of a poly-Si gate with designed line width of 50 nm