1-1 Background
With the first commercial Si transistor announced by Texas Instruments (TI) in 1954 [2], Si quickly replaced Ge as the most important semiconductor for manufacturing. In 1970s, the “Si-based” technology had been well established. To increase the device density and reduce the fabrication cost, the IC industry had concentrated on scaling down the devices’ dimensions and enlarging the wafer size since the early 1960s. Today, the mainstream of wafer diameter has been shifted from 8 inch (200 mm) to 12 inch (300 mm), and the microprocessor unit (MPU) physical gate length of device has scaled down to nano era (< 29 nm) according to the International Technology Roadmap for Semiconductors (ITRS) 2009 (Table. 1-1) [3].
Moreover, the physical gate length of device is scaling down to 22 nm for the requirements of high-performance logic technology in 2012 [3].
Major purposes of shrinking the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) dimension are to enhance the driving capability and increase the device density. However, as the MOSFET dimensions are reduced, there are many issues obstructing the progress of the semiconductor device. The most well known issue is the occurrence of short channel effects (SCE) that cause the threshold voltage
(Vth) roll-off, drain-induced barrier lowing (DIBL), and bulk punch-through, etc [4]-[16]. These effects become more difficult to suppress as the channel length decreases continuously.
Another issue is related to the lithography techniques for generating the fine patterns. Current 45 and 32 nm nodes of manufacturing need water-based 193nm immersion (193i) lithography to generate the most critical patterns. However, the cost of 193i lithography machine is above 60 million U.S. dollars [17] which is too high and not affordable for most academic organizations. Concurrently, although e-beam exposure technique is feasible to scale device gate length down to 0.1 μm, it suffers from the low throughput. To relieve these concerns, recently our group proposed the use of double patterning technique (DPT) with an i-line stepper to realize the fabrication of sub-0.1 μm devices [1] which could take advantage of much reduced cost as compared to the 193i techniques and much faster throughput as compared to the e-beam counterparts.
To alleviate the SCEs and other degradation effects caused by scaling, many researchers have devoted themselves to inventing new device structures to enhance the device performance. For example, devices with lightly-doped drain (LDD) [18]
structures were utilized to decrease the hot-carrier effects (HCEs). Even with the scaled supply voltage nowadays, LDD structures are still important in input/output
(I/O) devices. Other devices with double implanted LDD (DI-LDD) [18] structures, which are also called “halo implant” structures [10]. Such structures are added with an oppositely type of dopants located near the channel and underneath the source and drain junctions to meliorate the SCEs. Thanks to the development of those structures, great advancement in semiconductor technology has been achieved and the progress is still going.
Furthermore, in order to lower process cost and simplify device fabrication, standard manufacture schemes are devised with the symmetric structure. That is, the source and drain doping profiles are the same. However, theoretically symmetric structures are not ideal for device performance, and, with an appropriate design, asymmetric structures should outperform the symmetrical counterparts.
1-2 Double Patterning Technique
As mentioned above, 193i lithography is being used for 45 nm and 32 nm nodes of manufacturing [3]. The Rayleigh equation applicable for immersion lithography can be written as
IF
HP K
N NA
,
where HP is the minimum printable half pitch feature size, NIF is the immersion fluid index of refraction at the lithographic wavelength, NA is the numerical aperture of the (1-1)
stepper lens, λ is the lithographic wavelength, and K is a measure of the lithographic process capability. Since the NIF of a liquid (e.g., water) is much larger than that of air, the resolution can be improved with the wet lithographic techniques.
However, it’s very difficult for 193i to push further into 22 nm node and beyond, so finding a succeeding technique is urgent. One of the possible solutions is extreme ultra-violet (EUV) method which uses a much shorter wavelength of 13.4 nm with an NA of ~0.25. Another way is the 3rd generation immersion 193 nm system which has
~1.55 NA requiring higher refractive index (RI) (RI > 1.8) fluids, lens and photo-resists materials. Nevertheless, none of these techniques are ready for production yet to this date [20].
Double patterning (DP) is a resolution improvement technique that can potentially cut the pitch of patterns in half [21]. Double patterning lithography (DPL) has already shown its feasibility to the 22nm node [22]. Consequently, DP is viewed as a bridge to EUV lithography technology, which is not expected to be available for volume production until approximately 2011 or later.
1-3 Halo Implantation and Source/drain Extension Structure
For the purposes of performance enhancement and cost reduction, MOSFET scaling is inevitable. Certainly there are a number of critical problems lying ahead that
need to be carefully addressed [23]-[24].
Nowaday the most general method to restrain the SCE-induced drain-induced barrier lowing (DIBL), Vth roll-off, and bulk punch-through, is to perform the halo implantation (also called the pocket implantation) [19], which was first presented in 1985 and also called DI-LDD [18].
Halo implantation structure is formed using a titled angle implantation to form the high counter doping regions at the drain/substrate and source/substrate junctions and below the channel. The dopant type is the same as that of the substrate. Because of the relatively high doping concentration, the depletion regions of both source and drain extensions can be suppressed efficiently, resulting in a significant reduction in the subthreshold leakage current and the bulk punch-through, hence alleviating the SCE-induced degradations.
LDD structure [18] is used to improve HCE for devices working under a high operation voltage (e.g., I/O devices). As the applied drain voltage is sufficiently high that the maximum electric field along the channel exceeds a certain value, significant impact ionization may occur near the drain side. Fortunately, we can utilize the LDD structures to relieve the concern somewhat by decreasing the peak electric field in the channel of the MOSFET [25]. Actually LDD structures [18] have been commonly used to improve hot-carrier reliability [26]-[28] for MOSFETs operated under a high
voltage.
However, when MOS devices are scaled to nano-scale regime, the LDD regions will contribute more parasitic resistance and result in drain current degradations.
Moreover, operation voltage of the core devices in most advanced chips has been lowered to around 1V. This means the HCEs is no longer a major concern for these devices. Therefore the doping concentration of the regions is increased to a level comparable to that in the deep source/drain S/D regions for reducing the parasitic resistance but the junction depth is retained ultra-shallow for good control of the SCEs. In those nano-scale devices the previous “LDD” regions are renamed as
“extension” since they are no longer “lightly doped.” Furthermore, the use of asymmetric source/drain (S/D) extension (i.e., the two extensions have different doping concentration and/or junction depth) structures can be adopted for optimizing the current-drive capability, SCE control, and hot-carrier reliability [26]-[28].
1-4 Motivation and Objectives of this Thesis
As mentioned in Sec. 1-2, our group proposed the implementation of double patterning technique (DPT) into the i-line photolithographic process to realize the fabrication of nano-scale devices [1]. Basically the concept has been proved to be useful and feasible for generating patterns with critical dimension (CD) down to 0.1
μm. However, most of the devices fabricated in the previous work were found to be with poor performance and leaky. Origins for such outcome are found to be related to the etch-induced recess occurring at one side of the gate during the second gate etch step. An example is shown in Fig. 1-1. Occurrence of such phenomenon is due to the failure of end point detection during the second gate etch step. This issue has been addressed [1] and is expected to be solvable with a modified mask design. In this study, we examine the feasibility of the DP process with aforementioned modification in mask layout design and aim at fabrication and characterization of p-channel devices with channel length down to 0.1 μm and even shorter.
1-5 Organization of This Thesis
This thesis is divided into four chapters and each chapter is introduced briefly as below.
In Chapter 1, we show a brief overview of the background and the motivation.
In Chapter 2, we describe and evaluate the DP process developed in this work, and then we describe the DP technique for device fabrication. Finally, we present the measurement setup and characterization scheme.
In Chapter 3, we present the experimental results on characterizing the fabricated PMOSFET devices. Transfer and output current-voltage (I-V), and
capacitance-voltage (C-V) characteristics are examined and discussed. We also explore the effects of the halo-implant, symmetric and asymmetric extension structures on the device characteristics, device reliability issue like NBTI performance.
Finally, in Chapter 4, we conclude the results and suggest the future work.