Dickson Charge Pump

(a) (b)

Fig. 4.6 (a) Stage schematic of the two-phase charge pump[25]. (b) Complete schematic of the tree-stage two-phase charge pump.

4.2 Dickson Charge Pump

The four-stage diode charge pump circuit using the diodes as the charge transfer devices shows in Fig. 4.7(a) [27]. It is hard to carry out the fully independent diodes in the common silicon substrate. The charge pump circuit with diodes is shown in cannot be integrated into the standard CMOS process. Thus, most charge pump circuits are based on the circuit proposed by Dickson. Fig. 4.7(b) [27] shows the four-stage Dickson charge pump circuit, where the diode-connected MOSFETs are used to converter the charges from the present stage to the next stage. Thus, it can be suitable integrated into standard CMOS processes. Although, the voltage difference between the drain terminal and source terminal of the diode-connected MOSFET is the threshold voltage when the diode-connected MOSFET is turned on. Hence, the output voltage of the four-stage Dickson charge pump circuit has been derived as

5

( )

1

( )

out DD t Mi

i

V V V

=

= ∑ −

Vt(Mi) denotes the threshold voltage of the diode-connected MOSFET Mi. In the traditionally, the body terminals of the diode-connected MOSFETs in the Dickson charge pump circuit are connected to ground. The threshold voltage (Vt(Mi)) of the diode-connected MOSFET increased due to the body effect. The threshold voltage will enlarge when the source of NMOS is pumped up. Thus, the pumping efficiency will decrease as the pumping stage is increased. For solving this problem, solutions such as CTS, dynamic body bias scheme and four-phase clock scheme are proposed.

Fig. 4.6 (a) Stage schematic of the two-phase charge pump[25]. (b) Complete schematic of the tree-stage two-phase charge pump.

4.2.1 Charge Transfer Switch

For improving pumping up efficiency, the CTS use NMOS as switch to convert charge. This will ideally increase the pumping up efficiency of every stage by one VT.

The structure is shown in Fig. 4.8[28].

The Φ1 and Φ2 are CLK and CLKB. When voltage is pumped up, the source voltage of next stage will turn on the switch and help previous stage to convert charge directly. But that results the reverse charge sharing problem. For the switches always turn on, the charge of stage will flow back to previous stage when switching. Thus, the dynamic CTS scheme is proposed in Fig. 4.9[28].

When CLK is low, node 1 will be VDD and node 2 will be 3 VDD, then MN1 is turned off and MP1 is turned on. Therefore, the MS1 will turn on to transfer charges from the power supply to node1.When CLK is high, node 1 and node 2 will be 2 VDD, then MN1 is turned on and MP1 is turned off. Thus, the MS1 will turn off to avoid the charges back to the power supply. The problem is that the maximum gate to source voltage will be 3VDD, this will result the MOS breakdown. Thus, a design for prevention of gate oxide reliability is proposed.

Fig. 4.8 A four-stage charge pump using static CTS’s.

Fig. 4.9 A four-stage charge pump using dynamic CTS’s.

Fig. 4.10 Charge pump circuit with consideration of gate oxide reliability.

4.2.2 Charge Pump With Consideration of Gate Oxide Reliability

For avoiding gate oxide breakdown problem, the charge pump with consideration of gate oxide reliability is shown in Fig. 4.10[27]. For avoiding the body effect, the body of the devices in this charge pump circuit is advocated to be connected to their sources respectively. As shown in Fig. 4.10, there are two charge transfer branches, branch A and branch B. Branch A is composed of transistors MN1, MN2, MN3, MN4, MP1, MP2, MP3, and MP4 with the capacitors C1, C2, C3, and C4. Branch B is composed of transistors MN5, MN6, MN7, MN8, MP5, MP6, MP7, and MP8 with the capacitors C5, C6, C7, and C8. The control signals of branches A and B are entwined. Moreover, clock signals of branches A and B are out-of-phase.

When the clock signals of the first and the third pumping stages in the branch A are CLK, those in the branch B are CLKB. Similarly, when the clock signals of the second and the forth pumping stages in the branch A are CLKB, those in the branch B are CLK. Thus, branches A and B can see as two independent charge pump circuits but their output nodes are connected together. Because the clock signals of the branch A and those of the branch B are out-of-phase, the voltage waveforms of nodes 1–4 and those of nodes 5–8 are also out-of-phase. Therefore, branches A and B can pump up the output voltage to high, alternately. The operations of the new proposed charge pump circuit are described as below.

In the first half cycle, the CLK is low, V51 will be VDD, then MN1 will turn on to transfer charges from power supply to node 1, but the MN5 will turned off to cut off the path from node 5 to the power supply. Thus, the node 1 will be charged to VDD-Vtn. When CLK is high in first cycle, the node 1 will be 2VDD-Vtn and the node 5 will be charged to VDD. Thus, the V51 will be – (VDD-Vtn), then MP1 and MN2 will turn on to transfer charges from node 1 to node 2. In the second half cycle, the node 1 will be

discharged to VDD and node 2 will be 2VDD. When CLK is high in second cycle, the node 1 will be 2VDD and node 2 will be VDD. Thus, the output voltage of this charge pump will be 5VDD.

4.2.3 Dynamic Bias Scheme

For solving body effect problem, the technique of dynamically biasing body node is carried out. The architecture shows in Fig. 4.11[29]. Its detail operations are described as below.

In first half cycle, the CLK=low and the M1, M2 are turned on, the M3 is turned off.

Thus, the body of M1 is connected to terminal VDD. When CLK=high in first cycle, the M1 and M2 are turned off and the M3 is turned on. Thus, the body of M1 is connected to node 1. In the following stage, when the charge-transfer MOSFET is ON, the body of the charge-transfer MOSFET is connected to the source; otherwise, connected to the drain. When the voltage is pumped up, the body will be pumped up too. Thus, the pumping efficiency will not be decreased with increasing pumping stage.

Fig. 4.11 Charge pump circuit with dynamically biasing body node.