Switched Capacitor DC-DC Converter & Voltage Regulator

3.4.1 Reference Voltage Circuit

The voltage regulator needs a reference voltage to bias the output voltage. The reference voltage circuit is shown in Fig. 3.13[17]. The reference voltage circuit is composed of a startup circuit and a reference voltage generator. The design concept is shown in Fig. 3.13[17]. The M5 and M8 are operated at saturation region as the current source which is shown in Fig. 3.13. M4, M6 and M7 are operated at linear region as the resistor. In this reference voltage generator, there are two control paths, path1 (P1) and path2 (P2). P1 is a supply-independent skill to reduce the dependency between M2 current and supply voltage. P2 is a negative feedback compensation to increase the V_ref stability.

Fig. 3.13 Reference voltage circuit [17].

In order to improve the stability of reference voltage under different temperature, we change the devices of M1 and M7. As shown in Fig. 3.14, M7 is NMOS, and its gate is biased by gate of M2. For biasing M7, the M1 is changed to PMOS.

Fig. 3.14 The design of reference voltage circuit [17].

(a)Temperature variation analysis:

The temperature variation affect the threshold voltage of M1~M8 in Fig. 3.13 [17]

and Fig. 3.15. In Fig. 3.13, as the temperature going up, the voltage of M3’s gate is decreased and M7’s threshold voltage is decreased. Thus, the temperature affects the M3 and M7 to increase the current of M7. In Fig. 3.16, as the temperature going up, the voltage of M3’s gate is decreased and M7’s threshold voltage is decreased.

Because the M7 is NMOS, so the temperature affects the M3 to decrease the current of M7. Therefore, the circuit in Fig. 3.15 will more stable in different temperature.

The simulation results are shown in Fig. 3.16. The results are simulated in UMC 90nm CMOS technology.

Fig. 3.15 Reference voltage circuit in this work.

Temperature Variation

1.10 1.12 1.14 1.16 1.18 1.20 Power Supply (V)

Reference Voltage (mV)

Ref.[17]

This work

(b)

Fig. 3.16 (a) Temperature variation. (b) Power supply variation.

Table 3.1 Comparison 600mV generator of Ref.[17] and this work.

Ref.[17] This work

Technology 90 nm 90 nm

Supply voltage (Vsupply) 1.2V 1.2V

Reference voltage (Vref) 700mV 600mV

Supply variation (1.2V~1V) 729mV~650mV 600mV~513mV

ΔVref / ΔVsupply (mV/V) 0.395 0.435

Temperature variation (-40°C~140°C) 752mV~693mV 622mV~588mV

ΔVref / ΔTemperature (mV/°C) 0.32 0.18

Power consumption 74.5uW 4.5uW

(b) Variable voltage reference generation by resistor-string DAC:

The variable voltage reference is generated by resistor-string DAC in Fig. 3.17. The decoder selects the output voltage for variable voltage reference. Fig. 3.18 and Table 3.2 are shown the Variable voltage reference generation with temperature variation.

Fig. 3.17 Resistor-string DAC for variable voltage reference generation.

Variable Voltage Reference

Fig. 3.18 Variable voltage reference generation with temperature variation.

Table 3.2 Temperature variation

Temperature -40°C 30°C 140°C Variation

1V 1.02 1.0 1.04 0.04V

0.9V 0.92 0.9 0.94 0.04V

0.8V 0.82 0.8 0.83 0.03V

0.7V 0.71 0.7 0.73 0.03V

0.6V 0.61 0.6 0.62 0.02V

0.5V 0.51 0.5 0.52 0.02V

0.4V 0.41 0.4 0.42 0.02V

0.3V 0.31 0.3 0.31 0.01V

3.4.2 Switched Capacitor DC-DC Converter

The switched capacitor DC-DC converter is composed of a comparator (comp.), a non-overlapping clock generator and a switched capacitor matrix as shown in Fig.3.13.

The system sends the voltage control signal to change the topology of switched capacitor matrix and controls the DAC for settling the desire output voltage. The non-overlapping clock generator as shown in Fig.3.19 generates the non-overlapping clock (Φ1 and Φ2) to prevent the short circuit current path. And the proposed switched capacitor DC-DC converter can provide voltage form 0.3V~0.6V for low power SoC applications.

Fig. 3.19 Schematic of switched capacitor DC-DC converter.

Because of the low voltage detection such as 0.3V, the conventional architecture comparator will consume the voltage range Vds+Vtn. So the input signal should larger then Vds+Vtn which is unsuitable for low voltage detection. Therefore, we proposed a new architecture of comparator as shown in Fig.3.20 By replacing the clock controlled current tail NMOS, and using low Vth NMOS as differential input, and the clock controlled switches are inserted between differential input and comparator latch.

They are same function at small signal operation, but the proposed scheme can sense the voltage signal lager than Vtn which is suitable for low voltage sensing. Fig. 3.21 shows the transient response of voltage down conversion which can convert voltage to 0.3V and provide system for dynamic voltage scaling.

Fig. 3.20 Schematic of switched capacitor DC-DC converter.

Fig. 3.21 transient response of voltage down conversion.

3.4.3 A Voltage Regulator using Dynamic-Biased OP Amp

In order to decrease the bias current of op amp and stabilize the transient response of regulator simultaneous, we use a dynamic-biased control scheme for biasing op amp. The schematic of proposed voltage regulator is shown in Fig. 3.22.

Fig. 3.22 Voltage regulator with dynamic-biased op amp.

The voltage regulator is composed of op amp, a voltage buffer, a POWER PMOS transistor (MPOUT) and dynamic-biased circuit. The op amp is composed of MP1, MP2, MP3, MN1, MN2, MN3, and MN4. The voltage buffer is composed of MP4 and MN5. The dynamic-biased circuit is MP6. The current of MP6 is mirrored by MP5. When there is supplied the surfeit of load current, the current of MN7 will mirror the current to MP6

and turn off MPOUT. As the load current increase suddenly, the current of MN6 will decrease. Thus, the MP6 will decrease the supply current to help turn on MPOUT. With the control of MP6, MPOUT can turn on or turn off depend on the loading change.

The simulation results of voltage regulator using dynamic-biased OP amp. are shown in Fig. 3.23. When load current is 20mA, the voltage regulator outputs 1.06V and the quiescent current is 1mA. When load current is 150mA, the output voltage of voltage regulator will drop down and is stable in 963mV. The current efficiency is 99%. The comparison of the dynamic-biased voltage regulator with previous work ([15] and [16]) is shown in Table 3.3 and has better figure of merit.

1

Fig. 3.23 Output voltage of voltage regulator under different Load current.

Table 3.3 Comparison of [15], [16] and proposed voltage regulator.

Ref.[15] Ref.[16] This work

Technology (nm) 90 90 90

Input Voltage 1.2V 2.4V 1.2V

Output Voltage 0.9V 1.2V 1V

Output droop ΔVOUT 90mV 120mV 96mV

Rise time of Step Load current 100ps 50ps 250ps

MAX Load Current 100mA 1A 150mA

IQ (quiescent current) 6mA 25.7mA 1mA Current Efficiency 94.3% 97.5% 99%

Decoupling Cap. 0.6nF 2.4nF 0.4nF

Response time 540ps 288ps 256ps

FOM (figure of merit) 32ps 7.4ps 1.7ps

3.4.4 Switched Capacitor DC-DC Converter and Voltage Regulator

Because of the switched capacitor DC-DC converter is easy to convert down voltage for low voltage operation, but it is unable to provide high output current when the system at high voltage operation. Therefore, while the system at high voltage operation we use the voltage regulator to supply high voltage and high output loading current. The schematic of switched capacitor DC-DC converter and voltage regulator is shown in Fig.3.24. The switched capacitor DC-DC converter contains dual switched matrixes which can alternative charge the output voltage. There is a finite state machine (FSM) for controlling the dual switched matrixes and the state diagram is shown in Fig.3.25. When output voltage is lower then control voltage, the comparator sends the control signal (c) to change the dual switched matrixes. And the switched capacitor matrix 1 (SC1) is twice larger than switched capacitor matrix 2 (SC2), because of the SC2 is the auxiliary switched capacitor for supporting output voltage when SC1 is storing energy.

Switched

Fig. 3.24 Schematic of switched capacitor DC-DC converter and voltage regulator.

Fig. 3.25 The state diagram of the finite state machine.

The schematic of switched capacitor matrix is shown in Fig.3.26, and the topology of switched capacitor matrix shows in Fig.3.27. T1 and T0 are the control signal of switched capacitor topology selection as shown in Fig.3.26. When T1 T0 =10, the topology output voltage is 2/3 VDD (VDD=1.2V) and supplies 0.5V and 0.6V output voltage. When T1 T0 =11, the topology output voltage is 1/2 VDD and supplies 0.4V and 0.3V output voltage. When T1 T0 =01, the topology output voltage is 1/3 VDD and supplies 0.3V output voltage for system standby and data retention. When T1 T0 =00, the SC DC-DC converter is disabled.

SO

Fig. 3.26 The schematic of switched capacitor matrix.

2

Fig. 3.27 The topology of switched capacitor matrix.

The efficiency comparison of linear regulator and switched capacitor DC-DC converter is shown in Table 3.4. Because of the power MOS consumes the Vds voltage range, the efficiency of linear regulator is decreased with the low output voltage. Thus, the switched capacitor DC-DC converter is more suitable for supply low output voltage. The transient response of voltage down conversion is shown in Fig.3.28.

Table 3.4 Comparison of linear regulator and SC DC-DC converter.

Technology UMC 90nm CMOS Technology Output

Fig.

3.28 The transient response of voltage down conversion from 1V~0.3V.

3.5 Summary

In this chapter, the operation of switched capacitor type voltage conversion is specified. The ac stability, transient response scheme of voltage regulator is described.

The voltage regulator using digital buffer is also introduced. We improve the output loading capability of the switched capacitor by using dual switched capacitor matrixes.

We use the switched capacitor DC-DC converter provide the voltage from 0.6V~0.3V and use the voltage regulator provide the voltage from 1V~0.7V for low power SoC applications. For the low voltage comparison, we propose a low voltage comparator which has the lower input range then the conventional architecture. And a finite state machine is used in switched capacitor DC-DC converter for control the dual switched capacitor matrixes which is utilized to improve the output loading capability. The switched capacitor DC-DC converter and voltage regulator can provide the voltage range from 1V~0.3V and the conversion efficiency of switched capacitor DC-DC converter is better than voltage regulator at low output voltage.