Stability Scheme of Voltage Regulator

3.2.1 The Dynamic-Biased Shunt Feedback Buffer

A typical structure of a low-dropout regulator shows in Fig. 3.5 which consists of an error amplifier comparing the output voltage to the bandgap voltage V_bg, a PMOS pass transistor M_p, and the output buffer stage driving M_p. There are three different poles in the voltage regulator structure located at the output node of the error amplifier (N1), the output node of the buffer (N2), and the output node of the voltage regulator (V_out). In particular, these poles are given by

1 1 1 1

Fig. 3.5 Typical structure of a low-dropout regulator with an intermediate buffer stage.

The r_o1 is the output resistance of the error amplifier, C₁ is the equivalent capacitance at N₁ which is dominated by the input capacitance of the buffer C_ib, r_ob, is the output resistance of the buffer, C is the input capacitance of M , and R is the

equivalent resistance seen at the output of the voltage regulator. Ideally, both C_ib and r_ob should be very small in order to achieve single-pole loop response by locating both p₁ and p₂ at frequencies much higher than the unity-gain frequency of the regulation loop.

Fig. 3.6 Source-follower implementation of the intermediate buffer stage.

In order to construct the required output buffer stage, a simple PMOS source-follower is first considered for implementing the output buffer and its structure is shown in Fig. 3.6[10]. The PMOS source-follower provides near complete shutdown of the pass device when under the light-load conditions. Because of the output resistance r_ob of the source-follower is given by 1/g_m21, it is necessary to increase g_m21 in order to decrease the value of r_ob and allow p₂ to be located at frequencies much higher than the unity-gain frequency of the regulation loop.

Transconductance g_m21 can only be increased either through using a larger W/L ratio of transistor M₂₁, or through increasing the DC biasing current I₂₁ through M₂₁, or both. However, increasing I₂₁ would increase the total quiescent current of the regulator, and the current efficiency of the voltage regulator is degraded. Using a larger W/L ratio of M₂₁ would increase the input capacitance C_ib of the buffer, which

is in turn pushes p₁ to a lower frequency and the stability would be poorly affected. A simple PMOS source-follower is, therefore, not a suitable implementation of the output buffer stage in the voltage regulator.

Fig. 3.7 (a) Source-follower with shunt feedback. (b) The buffer with dynamically-biased shunt feedback for output resistance reduction under different

load currents.

For minimizing W/L ratio of M₂₁ and the quiescent current required to reach a given r_ob, the source-follower with negative feedback shown in Fig. 3.7(a)[10] is used.

In particular, the npn transistor Q₂₀ is the feedback device connected in parallel to the output of the source-follower M₂₁ in order to reduce r_ob through shunt feedback.

When the input voltage at N₁ is constant and the output voltage increases, the magnitude of the drain current of M₂₁ also increases, which in turn increases the base current of Q₂₀. As a result, the collector current of Q₂₀ increases, reducing the output resistance r_ob by increasing the total current that flows into the output node. The output resistance looking into the follower is then given by

21

Equation 3.2 shows that the output resistance of the follower is reduced by the current gain β of the shunt feedback device Q₂₀. For example, when an npn transistor with β more higher then 1 is used, the value of r_ob would be decreased and the frequency of p₂ at the gate of the pass device is then pushed to a decade higher. As a result, the quiescent current needed through M₂₁ is greatly reduced to realize g_m21 for a given r_ob. Similarly, the required transistor size of source-follower M₂₁ is also reduced. The input capacitance of the buffer C_ib is then decreased, which allows p₁ given in (3.1) to be located at a higher frequency without dissipating additional quiescent current. It should be noted that the shunt feedback device Q₂₀ can also be implemented by a NMOS transistor to achieve a similar reduction in the output resistance.

Because of the unit-gain frequency of the regulation loop increases with the load current, the output resistance of the buffer should decrease when the load current increases in order to maintain p₂ far away the unit-gain frequency under the entire load current range. The buffer with dynamically-biased feedback shows in Fig.

3.7(b)[10]. Two PMOS transistors M₂₄ and M₂₅ and the npn transistor Q₂₀ realize dynamically-biased shunt feedback to decrease r_ob under different load current conditions. The output resistance of the buffer is then given by

21 24

The g_m24 is the transconductance of the diode-connected transistor M₂₄. As shown in Fig. 3.7(b), when the load current flowing through the pass device M_p increases, both voltages at N₁ and N₂ decrease. The gate-source voltage of M₂₄ is increased and hence more current flows through M₂₄. This current then mirrors through M₂₅ such

that the current through the follower device M₂₁ dynamically increases with the load current. This boosts the value of g_m21, thereby further reducing the output resistance of the buffer according to (3.3). In addition, the increase in g_m24 with the load current can reduce the value of r_ob. This effect is significant under heavy load current conditions. Besides, when the load current increases, part of the dynamically-increased current through M₂₁ flows into the base of Q₂₀ and increases its collector current. The current gain β of the vertical parasitic npn transistor slightly increases with the collector current, which also helps on reducing the value of r_ob when the load current increases.

The dynamically-biased shunt feedback technique reduces both the input and output impedance of the buffer by decreasing the values of C_ib and r_obs. In particular, the reduction of r_ob increases with the change of load current. As a result of p₂ is located at sufficiently high frequencies under different load currents, while the voltage regulator only wastes low quiescent current at no-load condition. The benefit of having a smaller C₁ by using a smaller size of source-follower device in the buffer also improves the stability of the voltage regulator.

3.2.2 Zero-Pole Cancellation

A classical CMOS voltage regulator is shown in Fig. 3.8. This voltage regulator is composed of an error amplifier, a voltage buffer, a power PMOS transistor operating in saturation region, a feedback-resistor network and a voltage reference.

The three poles of this voltage regulator are generated at the output of the voltage regulator, the voltage buffer and the error amplifier, as mentioned in Section 3.2.1.

The stability of classical voltage regulator based on dominant-pole compensation with pole-zero cancellation as shown in Fig. 3.9. The second pole p₂ is cancelled by the zero z₁ created by the ESR of the output capacitor. With a large output capacitance,

the voltage regulator stability is achieved by locating p₃ beyond the unity-gain frequency of the loop gain for providing sufficient phase margin. However, when loop gain is too high, p₃ locates before the unity-gain frequency, and an even larger output capacitance is required to retain the voltage regulator stability.

Moreover, the power PMOS transistor in the classical voltage regulator must operate in saturation region for considering the stability problem at different input voltages. The change of the voltage gain due to different drain–source voltage is not substantial when the transistor operates in saturation region [12]–[13]. However, if the transistor operates in linear region at dropout, the transistor will operate in saturation region instead as the input voltage increases. As mentioned before, when the loop gain increases, the classical voltage regulator based on dominant-pole compensation may be unstable. Hence, the power PMOS transistor needs to operate in saturation region throughout the entire range of input voltage, so a large transistor size is required for providing a small saturation voltage at the maximum output current.

Fig. 3.8 Structure of classical voltage regulator.

Freq.

Fig. 3.9 Loop gain of classical voltage regulator.