Dickson Charge Pump

The four-stage diode charge pump circuit using the pn-junction diodes as the charge transfer devices is shown in Fig. 4.7(a) [27]. It is difficult to implement the fully independent diodes in the common silicon substrate. In other words, the charge pump circuit with diodes shown in cannot be easily integrated into the standard CMOS process. Therefore, most charge pump circuits are based on the circuit proposed by Dickson. Fig. 4.7(b) [27] shows the four-stage Dickson charge pump circuit, where the diode-connected MOSFETs are used to transfer the charges from the present stage to the next stage. Thus, it can be easily integrated into standard CMOS processes. However, the voltage difference between the drain terminal and source terminal of the diode-connected MOSFET is the threshold voltage when the diode-connected MOSFET is turned on. Therefore, the output voltage of the four-stage Dickson charge pump circuit has been derived as

5

where Vt(Mi) denotes the threshold voltage of the diode-connected MOSFET Mi.

Traditionally, the bulk terminals of the diode-connected MOSFETs in the Dickson charge pump circuit are connected to ground. The threshold voltage (Vt(Mi)) of the diode-connected MOSFET becomes larger due to the body effect. The threshold voltage will increase when the source of NMOS is pumped up. Thus, the pumping efficiency will degrade as the pumping stage is increase. To solve this problem,

solutions such as CTS (charge transfer switch), dynamic body bias scheme and four-phase clock scheme are proposed.

4.2.1 Charge Transfer Switch

To improve pumping efficiency, the CTS use NMOS as switch to transfer charge.

This will ideally increase the pumping efficiency of every stage by one VT. The structure is shown in Fig. 4.8[28].

1) Charge Pump Using Static CTS’s:

TheΦ₁andΦ₂ are CLK and CLKB. When voltage is pumped up, the source voltage of next stage will turn on the switch and help previous stage to transfer charge directly. But there is a reverse charge sharing problem. Because of the switches always turn on, the charge of stage will flow back to previous stage by switch. Thus, the dynamic CTS scheme is proposed in Fig. 4.9[28].

2) Charge Pump Using Dynamic CTS’s:

When CLK is low, node 1 will be VDD and node 2 will be 3vdd, then MN1 is turned off and MP1 is turned on. Thus, the MS1 will turn on to transfer charges from the power supply to node1.When CLK is high, node 1 and node 2 will be 2vdd, then MN1 is turned on and MP1 is turned off. Thus, the MS1 will turn off to prevent the charges back to the power supply. The problem is that the maximum gate to source voltage will be 3VDD, this will cause the MOS breakdown. Thus, a design with consideration of gate oxide reliability is proposed.

Fig. 4.7 (a) Four-stage diode charge pump circuit. (b) Dickson charge pump circuit.

Fig. 4.9 A four-stage charge pump using dynamic CTS’s.

Fig. 4.8 A four-stage charge pump using static CTS’s.

Fig. 4.10 Charge pump circuit with consideration of gate oxide reliability.

4.2.2 Charge Pump With Consideration of Gate Oxide Reliability

To avoid gate oxide breakdown problem, a new charge pump is proposed [27].

The charge pump is shown in Fig. 4.10[27]. To avoid the body effect, the bulks of the devices in the proposed charge pump circuit are recommended to be connected to their sources respectively. As shown in Fig. 4.10, there are two charge transfer branches, branch A and branch B, in the charge pump circuit. Branch A is comprised of transistors MN1, MN2, MN3, MN4, MP1, MP2, MP3, and MP4 with the capacitors C1, C2, C3, and C4. Branch B is comprised of transistors MN5, MN6, MN7, MN8, MP5, MP6, MP7, and MP8 with the capacitors C5, C6, C7, and C8. The control signals of branches A and B are intertwined. Besides, clock signals of branches A and B are out-of-phase. When the clock signals of the first and the third pumping stages in the branch A are CLK, those in the branch B are CLKB. Similarly, when the clock signals of the second and the forth pumping stages in the branch A are CLKB, those in the branch B are CLK. Thus, branches A and B can see as two independent charge pump circuits but their output nodes are connected together.

Because the clock signals of the branch A and those of the branch B are out-of-phase, the voltage waveforms of nodes 1–4 and those of nodes 5–8 are also out-of-phase.

Hence, branches A and B can pump the output voltage to high, alternately. The detailed operations of the new proposed charge pump circuit are described below.

In the first half cycle, the CLK is low, V51 will be VDD, then MN1 will turn on to transfer charges from power supply to node 1, but the MN5 will turned off to cut off

the path from node 5 to the power supply. Thus, the node 1 will be charged to VDD-Vtn. When CLK is high in first cycle, the node 1 will be 2VDD-Vtnand the node 5 will be charged to VDD. Thus, the V51 will be – (VDD-Vtn) (In this time, V62 will be VDD), then MP1 and MN2 will turn on to transfer charges from node 1 to node 2.

In the second half cycle, the node 1 will be discharged to VDD and node 2 will be 2VDD. When CLK is high in second cycle, the node 1 will be 2VDD and node 2 will be VDD. Thus, the output voltage of this charge pump will be 5VDD.

4.2.3 Dynamic Bias Scheme

To solve body effect problem, the technique of dynamically biasing body node is proposed. The architecture is shown in Fig. 4.11[29]. Its detail operations are described below.

In first half cycle, the CLK=low and the M1, M2 are turned on, the M3 is turned off.

Thus, the body of M1 is connected to terminal VDD. When CLK=high in first cycle, the M1 and M2 are turned off and the M3 is turned on. Thus, the body of M1 is connected to node 1. In the following stage, when the charge-transfer MOSFET is ON, the body of the charge-transfer MOSFET is connected to its source side; otherwise, connected to its drain side. When the voltage is pumped up, the body node will be pumped up too. Thus, the pumping efficiency will not decrease with increasing pumping stage.

Fig. 4.11 Charge pump circuit with dynamically biasing body node.

4.2.4 Four-Phase Clock Scheme

A charge pump employs special dual branch substrate connection technique to eliminate the body effect and avoid p-n junction forward conduction is shown in Fig. 4.12(a)[30]. The 4-phase clocks from [a] to [d] given in Fig. 4.12(b).

(a)

(b)

Fig. 4.12 (a) Charge pump circuit with four face clock. (b) The four-phase clocks for the charge pump divided into 6 time slots.

Before the charge pump starts to work, an initial setup to prevent from p-n junction forward conduction is attained by precharging the wells of all transistors. The pre-charge procedures are as follows:

1) The node x is charged by an NMOS transistor with the source connected to x and the drain connected to the supply voltage. The substrate capacitor (Csn) holds the voltage level around Vdd-Vtn, where Vth is the threshold voltage of NMOS transistors.

2) The NMOS transistors are turned off using the signal [e]. In the mean time, another node of the substrate capacitor (Csn) is raised from the original ground level to Vdd using inverters. Hence, the wells will hold at least the value of 2Vdd-Vtn.

After that the four phase clocks are applied to the pump, the detailed operations for the upper branch in the third stage with respect to the 6 time slots illustrated in Fig. 4.12(b) are follows:

1) The First time slot: Clock [a] (Low) and clock [c] (High) turn on the substrate transistor (Ms3) which charges the well of the main pass transistors (M3 and M3’) to the high potential level. Clock [b] (High) and clock [d] (High) turn off the main pass transistors of the upper and lower branches.

2) The second time slot: Clock [b] (Low) turns on the main pass transistor (M3), so the upper branch performs charge-sharing operation.

3) The third time slot: Clock [b] is high and clock [a] is low. Vgs of the main pass transistor (M3) is higher than Vtp (negative value) to make sure the main pass transistor (M3) to be off before clock [a] goes to high.