Comparison

The comparison of these two voltage regulator with previous work ([15] and [16]) is shown in table 3.2.

Table 3.2 Comparison of [15], [16] and proposed voltage regulator.

[15] [16] Voltage regulator I

Voltage regulator II

Technology (nm) 90 90 90 90

Input Voltage 1.2V 2.4V 1V 1V

Output Voltage 0.9V 1.2V 0.7V 0.7V

Output droop ΔVOUT 90mV 120mV 110mV 120mV

Rise time of Step Load

current 100ps 50ps 100ps 100ps

MAX Load Current 100mA 1A 100mA 100mA

IQ (quiescent current) 6mA 25.7mA 1mA 0.65mA

Current Efficiency 94.3% 97.5% 99% 99.4%

Decoupling Cap. 0.6nF 2.4nF 0.4nF 1.1nF

Response time 540ps 288ps 440ps 1320ps

FOM 32ps 7.4ps 4.4ps 8.58ps

* Voltage regulator I: the voltage regulator using dynamic-biasing op amp.

* Voltage regulator II: the voltage regulator using Schmitt trigger.

MAX

I

MAX

: Maximum load current

IQ : Quiescent current

3.6 Summary

In this chapter, the stability scheme, transient response scheme of voltage regulator is introduced. The voltage regulator using digital buffer is also introduced. A reference voltage circuit is introduced. We improve the temperature coefficient of the reference voltage circuit and apply it to our voltage regulator.

We proposed two voltage regulators that are voltage regulator using dynamic-biased scheme op amp and voltage regulator using Schmitt trigger. The voltage regulator using dynamic-biased scheme op amp has only 1mA quiescent current when no load current. Its current efficiency is 99% and the FOM is 4.4ps. The voltage regulator using Schmitt trigger has only 0.65mA quiescent current when no load current. Its current efficiency is 99.4% and the FOM is 8.58ps.

Chapter 4

Charge Pumps

To programming the information of nonvolatile memory like flash memory, the voltage adding to the gate must higher than power supply voltage as shown in Fig. 4.1(a) [18]. And negative voltage will add to gate when erasing the information of flash memory as shown in Fig. 4.1(b). Charge pump is used to generating such high voltage and negative voltage. Also, the high voltage can be used to improve the performance of the circuit.

There are many types of charge pump such as voltage doubler, voltage multiplier and Dickson charge pump. The Dickson charge pump is usually used to generate ultra high voltage like ten times of power supply voltage. The Dickson charge pump also can generate negative voltage.

In this Chapter, the voltage doubler is introduced and analysis in section 4.1.

Ultra high voltage can be generated by Dickson charge pump. The techniques of improving the pumping efficiency of Dickson charge pump will be introduced in Section 4.2. The negative voltage generator is also introduced in Section 4.3. In Section 4.4, we proposed a simple architecture of Dickson charge pump of generating ultra high voltage. And a novel connect scheme of charge pump is proposed for generating ultra high voltage with using CMOS as pumping capacitor. All results are simulated in UMC 90nm CMOS technology model.

(a) (b)

Fig. 4.1 (a) Programming: channel hot electron (CHE) injection in the floating gate at the drain side. (b) Erasing: Fowler-Nordheim (FN) electron tunneling current through the tunnel oxide from the floating gate to the silicon surface.

4.1 Voltage Doubler

The voltage doubler can generate twice the magnitude of supply voltage. A voltage doubler is illustrated in Fig. 4.2[22].

During clock phase , switches S1and S3are closed and the capacitor is charged to the supply voltage, VDD. Next switch S2is closed and the bottom plate of the capacitor assumes a potential VDD, while the capacitor maintains its charge of VDDC from the previous phase. This means that during

( )

Thus, in the absence of a dc load, an output voltage has been generated that is twice the supply voltage.

4.1.1 Voltage Multiplier

Voltage multiplication greater than twice the supply voltage can be achieved by cascading more than one capacitor in series. This voltage multiplier technique is proposed by Cockroft and Walton. The Cockroft-Walton multiplying circuit is shown in Fig. 23. Three capacitors, CA, CB and CC, each of capacity C, are connected in series and capacitor CA is connected to the supply voltage VDD. During phase capacitor C1is connected to CAand charge to voltage VDD. When the switches change position during the next cycle,, capacitor C1will share its charge with capacitor CB

and both will be charged to VDD/2 if they have equal capacity. In the next cycle,

Fig. 4.2 Voltage doubler.

C2 and CB will be connected and share a potential of VDD/4 while C1 is once again charged to VDD. It is thus obvious that if this process continues for a few cycles, charge will be transferred to all the capacitors until a potential of 3VDD is developed across the output Vout.

4.1.2 Analysis of Voltage Doubler

A state-of-the art charge pump for flash-EEPROM high-voltage generation is shown in Fig. 4.4[23]. It is a boosted charge pump with a four-phase clocking scheme.

This circuit shows a very good power efficiency at low output currents (65% at 40 uA), but the efficiency is very low at high current loads (20% at 200 uA).

The reason is that in boosted charge pumps, the transistors must withstand a voltage drop of twice the supply voltage; special (high-voltage) transistors are used to avoid breakdown. The main drawback is that these transistors have higher voltage threshold and parasitic capacitances in comparison to standard ones, therefore, their behavior when used as switches is not very good. This causes the efficiency drop at high current loads and limits the switching frequency, which is usually around 10–20 MHz.

The use of standard transistors is highly desirable to reduce voltage threshold and parasitic capacitances and to increase current drive capability. Reduced voltage thresholds will permit a better behavior of transistors when used as switches, which will increase efficiency and voltage gain; reduced parasitic capacitances will permit switching frequency to increase, which will reduce capacitor area.

Fig. 4.3 Cockcroft-Walton voltage multiplier

Fig. 4.4 Four stage boosted charge pump for positive high voltage generation with n-MOS transfer gates and conventional four-phase clocking scheme: Φ1 andΦ2 for charging the pump capacitors, Φb1 andΦb2 for boosting the gates during charge transfer.

On the other hand, standard transistors cannot stand voltages higher than the supply;

this dictates the use of a different architecture. A simple two-phase voltage doubler is presented in Fig. 4.5[24], achieving a 70% power efficiency at 2-mA current load with 100-pF capacitors and 10-MHz switching frequency. Unfortunately, these voltage doublers cannot be cascaded because of breakdown in nMOS transistors. This problem can be solved with a triple-well process, which allows changing the nMOS bulk voltage, as shown in Figs. 4.6(a)[25]. In this way, the voltage drop across each transistor is never higher than V_dd. Then the pump is a cascade of voltage doubler stages with nMOS transistors in triple well; each stage can be realized with standard transistors and is driven by a simple two-phase clocking scheme; the final stage is the same as the others, i.e., no specific output stage is needed. This solution has been proposed in [26] for a step up with no current load and a low (2-MHz) switching frequency. Here, we to use it also with a current load and increasing the switching frequency to 100 MHz to reduce the capacitors; 2.5-pF capacitors are used.

In Fig. 4.6(a), suppose that I_out=0. After the initial transient, a stationary situation is reached. During the first half cycle, CK=Vdd, CKneg=0, M0 and M3 are

on, M₁ and M₂ are off; C₁ is discharged to V_low through M₀, while C₀is charged to V_high, which is V_low+V_dd, through M₃. During the second half cycle, CK=0, CKneg=Vdd, M0and M3are off, M1and M2are on; C0is discharged to Vlowthrough M1, while is C1 charged to Vhigh, which is Vlow+Vdd, through M2. A voltage gain is therefore obtained between Vlowand Vhigh. When IOUT≠0, the voltage gain is reduced because of the stage output resistance and its value can be approximated by the following expression: the stage output resistance and Rswitch is the on-resistance of the transistor switches.

Routhas a nonlinear dependence on fCand Rswitch, symbolized by the function f. Cpar2is the bottom plate parasitic capacitance of capacitors C0, C1 shown in Fig. 4.6(a).

Cascading n stages as shown in Fig. 4.6(b), gives:

o u t d d

V  V    n V

The main current contribution to the load is given by the stage drivers. Drivers and switches must be carefully dimensioned so that at every clock cycle the power transfer is efficient. The proposed values have been chosen for maximum power efficiency at f = 100MHz. The following expression is used to evaluate power efficiency, Where V_out and I V( _dd) are the mean values of Voutand I(Vdd).

100%

_out

/

_in

100%

_{out out}

/

_dd

(

_dd

) Eff   P P   V  I V  I V

Fig. 4.5 Voltage doubler[24].

Fig. 4.6 (a) Stage schematic of the two-phase charge pump[25]. (b) Complete schematic of the tree-stage two-phase charge pump.

4.2 Dickson Charge Pump

The four-stage diode charge pump circuit using the pn-junction diodes as the charge transfer devices is shown in Fig. 4.7(a) [27]. It is difficult to implement the fully independent diodes in the common silicon substrate. In other words, the charge pump circuit with diodes shown in cannot be easily integrated into the standard CMOS process. Therefore, most charge pump circuits are based on the circuit proposed by Dickson. Fig. 4.7(b) [27] shows the four-stage Dickson charge pump circuit, where the diode-connected MOSFETs are used to transfer the charges from the present stage to the next stage. Thus, it can be easily integrated into standard CMOS processes. However, the voltage difference between the drain terminal and source terminal of the diode-connected MOSFET is the threshold voltage when the diode-connected MOSFET is turned on. Therefore, the output voltage of the four-stage Dickson charge pump circuit has been derived as

5

where Vt(Mi) denotes the threshold voltage of the diode-connected MOSFET Mi.

Traditionally, the bulk terminals of the diode-connected MOSFETs in the Dickson charge pump circuit are connected to ground. The threshold voltage (Vt(Mi)) of the diode-connected MOSFET becomes larger due to the body effect. The threshold voltage will increase when the source of NMOS is pumped up. Thus, the pumping efficiency will degrade as the pumping stage is increase. To solve this problem,

solutions such as CTS (charge transfer switch), dynamic body bias scheme and four-phase clock scheme are proposed.

4.2.1 Charge Transfer Switch

To improve pumping efficiency, the CTS use NMOS as switch to transfer charge.

This will ideally increase the pumping efficiency of every stage by one VT. The structure is shown in Fig. 4.8[28].

1) Charge Pump Using Static CTS’s:

TheΦ₁andΦ₂ are CLK and CLKB. When voltage is pumped up, the source voltage of next stage will turn on the switch and help previous stage to transfer charge directly. But there is a reverse charge sharing problem. Because of the switches always turn on, the charge of stage will flow back to previous stage by switch. Thus, the dynamic CTS scheme is proposed in Fig. 4.9[28].

2) Charge Pump Using Dynamic CTS’s:

When CLK is low, node 1 will be VDD and node 2 will be 3vdd, then MN1 is turned off and MP1 is turned on. Thus, the MS1 will turn on to transfer charges from the power supply to node1.When CLK is high, node 1 and node 2 will be 2vdd, then MN1 is turned on and MP1 is turned off. Thus, the MS1 will turn off to prevent the charges back to the power supply. The problem is that the maximum gate to source voltage will be 3VDD, this will cause the MOS breakdown. Thus, a design with consideration of gate oxide reliability is proposed.

Fig. 4.7 (a) Four-stage diode charge pump circuit. (b) Dickson charge pump circuit.

Fig. 4.9 A four-stage charge pump using dynamic CTS’s.

Fig. 4.8 A four-stage charge pump using static CTS’s.

Fig. 4.10 Charge pump circuit with consideration of gate oxide reliability.

4.2.2 Charge Pump With Consideration of Gate Oxide Reliability

To avoid gate oxide breakdown problem, a new charge pump is proposed [27].

The charge pump is shown in Fig. 4.10[27]. To avoid the body effect, the bulks of the devices in the proposed charge pump circuit are recommended to be connected to their sources respectively. As shown in Fig. 4.10, there are two charge transfer branches, branch A and branch B, in the charge pump circuit. Branch A is comprised of transistors MN1, MN2, MN3, MN4, MP1, MP2, MP3, and MP4 with the capacitors C1, C2, C3, and C4. Branch B is comprised of transistors MN5, MN6, MN7, MN8, MP5, MP6, MP7, and MP8 with the capacitors C5, C6, C7, and C8. The control signals of branches A and B are intertwined. Besides, clock signals of branches A and B are out-of-phase. When the clock signals of the first and the third pumping stages in the branch A are CLK, those in the branch B are CLKB. Similarly, when the clock signals of the second and the forth pumping stages in the branch A are CLKB, those in the branch B are CLK. Thus, branches A and B can see as two independent charge pump circuits but their output nodes are connected together.

Because the clock signals of the branch A and those of the branch B are out-of-phase, the voltage waveforms of nodes 1–4 and those of nodes 5–8 are also out-of-phase.

Hence, branches A and B can pump the output voltage to high, alternately. The detailed operations of the new proposed charge pump circuit are described below.

In the first half cycle, the CLK is low, V51 will be VDD, then MN1 will turn on to transfer charges from power supply to node 1, but the MN5 will turned off to cut off

the path from node 5 to the power supply. Thus, the node 1 will be charged to VDD-Vtn. When CLK is high in first cycle, the node 1 will be 2VDD-Vtnand the node 5 will be charged to VDD. Thus, the V51 will be – (VDD-Vtn) (In this time, V62 will be VDD), then MP1 and MN2 will turn on to transfer charges from node 1 to node 2.

In the second half cycle, the node 1 will be discharged to VDD and node 2 will be 2VDD. When CLK is high in second cycle, the node 1 will be 2VDD and node 2 will be VDD. Thus, the output voltage of this charge pump will be 5VDD.

4.2.3 Dynamic Bias Scheme

To solve body effect problem, the technique of dynamically biasing body node is proposed. The architecture is shown in Fig. 4.11[29]. Its detail operations are described below.

In first half cycle, the CLK=low and the M1, M2 are turned on, the M3 is turned off.

Thus, the body of M1 is connected to terminal VDD. When CLK=high in first cycle, the M1 and M2 are turned off and the M3 is turned on. Thus, the body of M1 is connected to node 1. In the following stage, when the charge-transfer MOSFET is ON, the body of the charge-transfer MOSFET is connected to its source side; otherwise, connected to its drain side. When the voltage is pumped up, the body node will be pumped up too. Thus, the pumping efficiency will not decrease with increasing pumping stage.

Fig. 4.11 Charge pump circuit with dynamically biasing body node.

4.2.4 Four-Phase Clock Scheme

A charge pump employs special dual branch substrate connection technique to eliminate the body effect and avoid p-n junction forward conduction is shown in Fig. 4.12(a)[30]. The 4-phase clocks from [a] to [d] given in Fig. 4.12(b).

(a)

(b)

Fig. 4.12 (a) Charge pump circuit with four face clock. (b) The four-phase clocks for the charge pump divided into 6 time slots.

Before the charge pump starts to work, an initial setup to prevent from p-n junction forward conduction is attained by precharging the wells of all transistors. The pre-charge procedures are as follows:

1) The node x is charged by an NMOS transistor with the source connected to x and the drain connected to the supply voltage. The substrate capacitor (Csn) holds the voltage level around Vdd-Vtn, where Vth is the threshold voltage of NMOS transistors.

2) The NMOS transistors are turned off using the signal [e]. In the mean time, another node of the substrate capacitor (Csn) is raised from the original ground level to Vdd using inverters. Hence, the wells will hold at least the value of 2Vdd-Vtn.

After that the four phase clocks are applied to the pump, the detailed operations for the upper branch in the third stage with respect to the 6 time slots illustrated in Fig. 4.12(b) are follows:

1) The First time slot: Clock [a] (Low) and clock [c] (High) turn on the substrate transistor (Ms3) which charges the well of the main pass transistors (M3 and M3’) to the high potential level. Clock [b] (High) and clock [d] (High) turn off the main pass transistors of the upper and lower branches.

2) The second time slot: Clock [b] (Low) turns on the main pass transistor (M3), so the upper branch performs charge-sharing operation.

3) The third time slot: Clock [b] is high and clock [a] is low. Vgs of the main pass transistor (M3) is higher than Vtp (negative value) to make sure the main pass transistor (M3) to be off before clock [a] goes to high.

4.3 Negative Voltage Generator

The Dickson charge pump also can be used to generate negative voltage as shown in Fig. 4.13. The operation is described below:

In the first half cycle, CLK = high, the node 1 will be discharged to 0. When CLK = low in first cycle, the node 1 will be –VDD and the M1 is turned off state.

CLK

Fig. 4.13 Dickson charge pump generates negative voltage.

In this time, the M2 is turned on and the node 2 will be discharged to 0.

When CLK = high in second cycle, the node 2 will be –VDD and node 1 will be 0.

When CLK = low in second cycle, the node 2 and node 1 will be -0.5VDD. In the end of third cycle, the node 2 will be -0.75VDD. In the end of next cycle, the node 2 will be -0.875VDD. Thus, the node 2 will vary between –VDD and -2VDD. Then the OUT will be discharged to -4VDD.

4.4 Proposed Charge pump

4.4.1 A Solution of Improving Body Effect of Dickson Charge Pump

We proposed a solution to improve the body effect of Dickson charge pump. The circuit is shown in Fig. 4.14. In the first half cycle, when CLK = 0, the node 1 is charged to VDD-Vtn1(t), the Vtn1(t) is threshold voltage of MN1:

1 0

Thus, the Vtn1(t) is smaller than the threshold voltage of NMOS’s body connecting to ground. When CLK = VDD in first cycle, the node 1 is 2VDD-Vtn1(t). In this time, the threshold voltage of MN1 is Vtn1(t+1) :

1 0

Therefore, the leakage flow from node 1 to VDD is decreased. As the voltage pump up in following stages, the threshold voltage of NMOS in every stage is the same as Vtn1(t). So, the problem of body effect is improved.

Fig. 4.14 Proposed charge pump.

The comparison of proposed charge pump with previous works is shown in Fig. 4.15 and Fig. 4.16. Charge pumps in this comparison are four stage. The simulation results show that the proposed charge pump has better loading capability and highest power efficiency.

Fig. 4.15 Output voltage of charge pumps in different load current.

Power Efficiency Comparison

Fig. 4.16 Power efficiency of charge pumps in different load current.

4.4.2 A Novel Connect Scheme of Charge Pump

For flash memory applications, ten times power supply voltage is used. To generate ultra high voltage, the architecture in Fig. 4.17 is used. We can cascade more stage to generate higher voltage. Base on this architecture, we proposed a novel connect scheme for ultra high voltage generating. The proposed architecture is shown in Fig. 4.18.

Fig. 4.17 Charge pump generating ultra high voltage.

VDD

CLKB CLK

C_L VOUT

1 2

3 4

MC1 MC2 MC3 MC4

MC5 MC6 MC7 MC8

Fig 4.18 Proposed novel connect scheme for generating ultra high voltage.

In Fig. 4.17, we know that node 1 swings between VDD and 2VDD. The node 6 will swing between 2VDD and 3VDD due to the CLK signal swings between 0 and VDD. Base on this concept, we can connect the CLK node of C6 to node 1 due to node 1 swings between VDD and 2VDD. And we can connect the CLKB node of C2 to node 5 due to node 5 swings between 2VDD and VDD. So, the overall architecture is the same as Fig. 4.18. Furthermore, in the proposed architecture, we can use CMOS to replace capacitor. In Fig. 4.17, the maximum cross voltage of C2, C3 and C4 are

In Fig. 4.17, we know that node 1 swings between VDD and 2VDD. The node 6 will swing between 2VDD and 3VDD due to the CLK signal swings between 0 and VDD. Base on this concept, we can connect the CLK node of C6 to node 1 due to node 1 swings between VDD and 2VDD. And we can connect the CLKB node of C2 to node 5 due to node 5 swings between 2VDD and VDD. So, the overall architecture is the same as Fig. 4.18. Furthermore, in the proposed architecture, we can use CMOS to replace capacitor. In Fig. 4.17, the maximum cross voltage of C2, C3 and C4 are

在文檔中 應用於太陽能之有效率的電源管理系統 (頁 58-0)