Chapter 2 An Overview of Solar Energy Harvesting Applications 3
2.6 Summary
In this chapter, the characteristic of PV cell is introduced and its circuit mode is implemented. A maximum power point tracking technique was used for PV cell. The MPPT controller sensed the output voltage and current of PV cell and adjusted the reference voltage of dc/dc converter to keep the PV cell operating in maximum power point.
For ultra-low voltage energy harvesting application, a power management system with small battery to jump start was implemented. The power management system also contained a low power clock generator for a four stage 16x exponential charge pump circuit. Whit the unpredictable power source, the power management used a charge-base control unit to prevent the computation error.
A charge pump is usually used in solar energy harvesting applications. For efficiently using the energy, a micro power management system with maximum output power control was implemented. The system contained an optimal power tracking unit to monitor the output power of charge pump and generated the adjustment decision for the switching frequency of the charge pump so that the system was working around the optimal output power point. Finally, a micro battery model is introduced. Two battery management systems were designed to co-operate with the battery.
Chapter 3
Voltage Regulators
A voltage regulator is composed of an op amp, reference voltage generator and an output MOSFET. The ideal voltage regulator is low dropout voltage, low quiescent current, good loading capability and small output transient undershoots and overshoots.
To archive high output current and low dropout voltage, the output MOSFET must be very large. But the larger MOSFET will increase the intrinsic capacitor of its gate node. This will cause stability problem. To archive high-precision output voltage regulator, a high loop gain is required. But the stability is sacrificed when loop gain is too high. Good transient response is related to slew rate at the gate drive of the power transistor and the loop-gain bandwidth. This can be improved by a high slew-rate buffer and advanced frequency compensation technique.
In this Chapter, the techniques of improving stability of voltage regulator are introduced in Section 3.1. The techniques of improving transient response of voltage regulator are introduced in Section 3.2. A linear regulator using digital buffer is introduced in Section 3.3. The reference voltage circuit is described in Section 3.4.
Finally, we proposed two voltage regulators with high current efficiency and fast load regulation in Section 3.5. All results are simulated in UMC 90nm CMOS technology model.
3.1 Stability Scheme of Voltage Regulator 3.1.1 The Dynamic-Biased Shunt Feedback Buffer
A typical structure of a low-dropout regulator is shown in Fig. 3.1[10], which consists of an error amplifier comparing a scaled-down output signal to a bandgap voltage Vbg, a PMOS pass transistor Mp, and an intermediate buffer stage driving Mp. There are three poles in the LDO structure located at the output of the error amplifier (N1), the output of the buffer (N2), and the output of the LDO (Vout). In particular, these poles are given by
1 1 1 1
Fig. 3.1 Typical structure of a low-dropout regulator with an intermediate buffer stage.
The ro1 is the output resistance of the error amplifier, C1 is the equivalent capacitance at N1which is dominated by the input capacitance of the buffer Cib, rob, is the output resistance of the buffer, Cpis the input capacitance of Mp, and Roeq is the equivalent resistance seen at the output of the LDO. Ideally, both Cib and rob should be very small in order to achieve single-pole loop response by locating both p1and p2 at frequencies much higher than the unity-gain frequency of the regulation loop.
In order to construct the required intermediate buffer stage, a simple PMOS source-follower is first considered to implement the buffer and its structure is shown in Fig. 3.2[10]. The PMOS source-follower can provide near complete shutdown of the pass device under light-load conditions. Since the output resistance rob of the source-follower is given by 1/gm21, it is necessary to increase gm21 in order to decrease the value of rob and allow p2to be located at frequencies much higher than the unity-gain frequency of the LDO regulation loop. Transconductance gm21can only be increased either through using a larger W/L ratio of transistor M21, or through increasing the DC biasing current I21 through M21, or both. Increasing I21 would, however, increase the total quiescent current of the LDO, thereby degrading the current efficiency of the LDO. Using a larger W/L ratio of M21 would increase the input capacitance Cibof the buffer, which in turn pushes p1to a lower frequency and the stability can be poorly affected. A simple PMOS source-follower is, therefore, not a suitable implementation of the intermediate buffer stage in the LDO.
Fig. 3.2 Source-follower implementation of the intermediate buffer stage.
In order to minimize W/L ratio of M21and the quiescent current required to reach a given rob, the source-follower with negative feedback shown in Fig. 3.3(a)[10] is used.
In particular, the npn transistor Q20is the feedback device connected in parallel to the output of the source-follower M21in order to reduce robthrough shunt feedback. From a qualitative standpoint, when the input voltage at N1 is constant and the output voltage increases, the magnitude of the drain current of M21 also increases, which in turn increases the base current of Q20. As a result, the collector current of Q20 increases, reducing the output resistance robby increasing the total current that flows into the output node. The output resistance looking into the follower is then given by
21
Equation 3.2 shows that the output resistance of the follower is reduced by the current gain β of the shunt feedback device Q20. For example, when an npn transistor with β=10 is used, the value of rob would be decreased by about 10 times and the frequency of p2at the gate of the pass device is then pushed to a decade higher. As a result, the quiescent current needed through M21is greatly reduced to realize gm21for a given rob. Similarly, the transistor size of source-follower M21 required is also reduced. The input capacitance of the buffer Cib is then decreased, which allows p1 given in (3.1) to be located at a higher frequency without dissipating additional quiescent current. It should be noted that the shunt feedback device Q20can also be implemented by a NMOS transistor in single-well technologies to achieve a similar reduction in the output resistance.
Since the unity-gain frequency of the LDO regulation loop increases with the load current, the output resistance of the buffer should decrease when the load current increases in order to maintain p2far beyond the unity-gain frequency under the entire load current range. The buffer with dynamically-biased feedback
Fig. 3.3 (a) Source-follower with shunt feedback. (b) The buffer with dynamically-biased shunt feedback for output resistance reduction under different load currents.
is shown in Fig. 3.3(b)[10]. Two PMOS transistors M24 and M25 and the npn transistor Q20 realize dynamically-biased shunt feedback to decrease rob under different load current conditions. The output resistance of the buffer is then given by
21 24
The gm24 is the transconductance of the diode-connected transistor M24. As shown in Fig. 3.3(b), when the load current flowing through the pass device Mpincreases, both voltages at N1 and N2 decrease. The gate-source voltage of M24 is increased and hence more current flows through M24. This current then mirrors through M25 such that the current through the follower device M21dynamically increases with the load current. This boosts the value of gm21, thereby further reducing the output resistance of the buffer according to (3.3). In addition, the increase in gm24with the load current can reduce the value of rob. This effect is significant under heavy load current conditions. Moreover, when the load current increases, part of the dynamically-increased current through M21 flows into the base of Q20 and increases its collector current. The current gain β of the vertical parasitic npn transistor slightly increases with the collector current, which also helps on reducing the value of rob when the load current increases.
The dynamically-biased shunt feedback technique reduces both the input and output impedance of the buffer by decreasing the values of Ciband robs. In particular, the reduction in the value of rob increases with the load current. As a result, p2 is located at sufficiently high frequencies under different load currents, while the LDO
only dissipates low quiescent current at no-load condition. The benefit of having a smaller C1 by using a smaller size of source-follower device in the buffer also improves the stability of the LDO.
3.1.2 Zero-Pole Cancellation
A classical CMOS LDO is shown in Fig. 3.4[11]. This LDO is composed of an error amplifier, a voltage buffer, a power PMOS transistor operating in saturation region, a feedback-resistor network and a voltage reference.
The three poles of this LDO are generated at the output of LDO, the voltage buffer and the error amplifier, as mentioned in Section 3.1.1. The stability of classical LDO based on dominant-pole compensation with pole-zero cancellation as shown in Fig. 3.5[11]. The second pole p2is cancelled by the zero z1created by the ESR of the output capacitor. With a large output capacitance, the LDO stability is achieved by locating p3 beyond the unity-gain frequency of the loop gain to provide sufficient phase margin. However, when loop gain is too high, p3 locates before the unity-gain frequency, and an even larger output capacitance is required to retain LDO stability.
Moreover, the power PMOS transistor in the classical LDO must operate in saturation region due to the stability problem at different input voltages. The change in voltage gain due to different drain–source voltage is not substantial when the transistor operates in saturation region [12]–[13]. However, if the transistor operates in linear region at dropout, the transistor will operate in saturation region instead as the input voltage increases. As mentioned previously, when the loop gain increases, the classical LDO based on dominant-pole compensation may be unstable. Therefore, the power PMOS transistor needs to operate in saturation region throughout the entire range of input voltage, so a large transistor size is required to provide a small saturation voltage at the maximum output current.
Fig. 3.4 Structure of classical LDO.
Fig. 3.5 Loop gain of classical LDO.
3.1.3 Damping Factor Control Compensation
From the previous discussion, the classical LDO suffers from a stability problem.
This problem is due to the low-frequency poles, and hence, large off-chip capacitance and ESR are needed for closed-loop stability. In fact, this problem can be solved by pole splitting. However, classical two-stage-amplifier topology is not optimum since the power transistor cannot function as a high-gain stage in dropout condition. The pole-splitting effect is thus not effective and the output precision is also degraded.
Instead, an LDO can be viewed as a three-stage amplifier with the power transistor as the last stage. When using this approach, the positions of the nondominant poles depend on the transconductance of the power transistor and the output capacitance.
The larger transconductance and smaller output capacitance results in higher frequencies of the nondominant poles. Therefore, the worst case stability occurs at zero load-current condition as the transconductance is minimum (about 5–10 mA/V) when only a current equaled toVOUT /(RF1RF2) 1 5 uAdrains from the power transistor. Advanced frequency compensation techniques are required to generate a more effective pole-splitting effect incorporated with pole-zero cancellation. The pushed nondominant poles can be cancelled more effectively by extra zeros at higher frequencies. The required passive components to generate the zeros can be much smaller, and the coupling noise is, hence, reduced significantly. A stable and fast-response LDO with DFC frequency compensation is shown in Fig. 3.6[11].
Fig. 3.6 The schematic of LDO with DFC frequency compensation.
The DFC stage is composed of a negative gain stage with a compensation capacitor Cm2, and the DFC stage is connected at the output of first stage. Another compensation capacitor Cm1 is required to achieve pole-splitting effect. The feedback-resistive network creates a medium frequency zero for improving the LDO stability and its schematic is shown in Fig. 3.7[11]. The transfer function of feedback-resistive network is given by
From the above analysis, it is shown that one pole (pf) and one zero (zf) are created, and pfand zfare, respectively, given by
The zero frequency is lower than the pole frequency and can be used to cancel the effect of non-dominant pole created in the regulator. In order to have zf << pf, RF2
should be much smaller than RF1.
Due to the effective pole-splitting effect by DFC compensation, the non-dominant pole frequencies are high, and so the required CF1is small and is about 5pF.
In addition, the transient response will not be slowed by CF1 because it is small and is connected at the regulator output.
Fig. 3.7 Feedback-resistive network with first-order high-pass characteristic.
To enhance the DFC scheme to provide a wider loop-gain bandwidth, the gm boosting circuitry is used. The gm boosting circuitry is shown in Fig. 3.8[11]. The function of M17 and M18 is to create a signal –v1 from the input signal v1, and these two signals v1and -v1are applied to M21 and M22, respectively. With k-times current mirror, the effective transconductance is increased by 2k times.
Following discussion is the stability of LDO with and without off-chip capacitor.
1) Stability with off-chip capacitor:
The stability of the proposed LDO is considered for two cases:
OUT 0
I and IOUT . When0 IOUT , the transconductance g0 mp and the output resistance ropof the power PMOS is at the minimum and maximum, respectively. This is the worst case stability of the proposed compensation scheme. In this case, the DFC scheme provides a transfer function given by
( )
0Where Cgis the gate capacitance of the power PMOS and gm4is the transconductance of the DFC stage.
Lo, p1and zeare the low-frequency loop gain of the DFC scheme, the dominant pole and ESR zero respectively, and gm1, gm2, Ro1, Ro2and Reare the transconductance of
the error amplifier, the transconductance of the second gain stage, the output resistance of the error amplifier, the output resistance of the second gain stage, and the
Fig. 3.8 Transconductance-boosting circuitry.
ESR of the output capacitance, respectively.
WhenIOUT , the current drain from the power transistor is0 VOUT /(RF1RF2), which is less than 1–5 uA for low-power LDO designs. Therefore, gmp is very small, and this causes the effect of COUTRe in the s term at the denominator of (3.6) to be negligible. As a result, (3.6) is approximated to
( )
0Comparing the second-order function in (3.7) with a standard second-order function given by
where is the damping factor andp is the pole frequency of the complex poles. Thec value of p is given byc
The damping factor is given by
4
Fig. 3.9 Loop gain of the LDO with DFC scheme. (a) COUT and0 IOUT .0 (b)COUT and0 IOUT . (c)0 COUT and0 IOUT .0
The damping factor is critical to the LDO stability. If the damping factor is too small, a frequency peak occurs and pole-zero cancellation by separated zeros is not effective.
If the damping factor is too large, the complex poles become two separated real poles and the loop-gain bandwidth will be degraded. Therefore, the damping factor is set to 1/ 2 as a compromise under the conditions that
1 1
It is noted that Cm2=Cm1is set for proper operation of the DFC scheme.
As shown in Fig. 3.9(a), the effect of the complex poles can be cancelled by zeand zf. Since the complex poles are split to a high frequency by the DFC scheme, zeand zf are at high frequencies. This implies that a low ESR, which is the key to a better load transient response and PSRR, is required. Moreover, pf is designed to be higher than the unity-gain frequency of the loop gain for a good phase margin.
When there is a little increase of load current, as shown in (3.8), the complex poles will shift to a little higher frequency due to the increase of gmp. The LDO is still stable since the pole-zero cancellation is still effective for pole-zero separation of less than a half of a decade.
When the load current increases significantly, gmp also increases significantly and
the second-order function at the denominator of (3.6) is altered. The transfer function
In this case, the ESR zero has no effect since an ESR pole is created simultaneously.
The LDO is reduced to a one-zero three-pole system, where the new pole
2 ( m2 mp e) /( g)
p g g R C is created. As shown in Fig. 3.9(b), zf can be used to cancel p2 to make the system stable.
2) Stability without off-chip capacitor:
When the proposed LDO is used in system-on-chip designs without an off-chip capacitor, the LDO is also stable. There is a minimum load current such that the LDO is still stable. The output capacitance comes from the power line, and the required minimum load current is larger for a larger load capacitance. Under such circumstance without the off-chip capacitor, ESR does not exist. Moreover, the second and third poles are pushed to frequencies that are higher than the unity-gain frequency of loop gain due to a large gmp. The transfer function is given by
( )
As shown in Fig. 3.9(c), pole-zero cancellation is automatically achieved by zf and pf, and thus, the theoretical phase margin is90o. However, parasitic poles and zeros will degrade the phase margin.
3.2 Transient Response Scheme of Voltage Regulator
3.2.1 Replica Feedback Circuit
The replica feedback circuit is shown in Fig. 3.10[14]. This regulator is composed of Bandgap reference, voltage comparator, charge pump, replica feedback circuit and output NMOS. The NMOS has inherently low output impedance for all frequencies. It also ensures a good PSRR because the NMOS behave like a cascade
device for the internal supply. The charge pump decreases the dropout voltage of regulator. The large capacitor C1 is necessary to reduce the capacitive coupling from the output to the gate voltage VG at higher frequencies through the gate-source capacitance of output transistor M1.
Instead of sensing the output voltage directly, a replica branch is used for feedback which guarantees stability independent of the load. This is an advantage since the exact load is not known. The influence of process variations and temperature at dc settings is cancelled due to the matched structure of the replica. The replica ensures that the output is controlled toward the correct nominal dc setting, and implies that the loop is not influenced by load current variations. The influence of replica feedback circuit is illustrated in Fig. 3.11[14].
Fig. 3.10 The voltage regulator with replica feedback circuit.
Fig. 3.11 Influence of replica feedback. With replica, the ripple in Vout is reduced by a factor 2.
3.2.2 Voltage Positioning
Optimum droop response is achieved for a constant, resistive output impedance of the regulator across the full frequency range of the load current, including dc. This concept, also called voltage positioning, is illustrated in Fig. 3.12[15].
Voltage positioning is easily implemented in replica-biased designs by adjusting the gain of the load regulation loop so that the dc and ac droops are equal. The regulator is shown in Fig. 3.13[15].
This regulator is composed of op amp A0, pre-driver N-stage NS, replica circuit PS0R, output stage PS0~PS19, resistor ESR and capacitor CDIE. The P-stage circuit is
This regulator is composed of op amp A0, pre-driver N-stage NS, replica circuit PS0R, output stage PS0~PS19, resistor ESR and capacitor CDIE. The P-stage circuit is