PV Characteristic and Detail Circuitry

5.3.1 Photovoltaic (PV) Cell

The I-V curve and P-V curve of PV cell is shown in Fig. 5.7. The black line is I-V curve of output load current and output voltage of PV cell. The output voltage of PV cell is between 840mV and 0mV. The red line shows the P-V curve of output power and output voltage of PV cell. The maximum output power of PV cell is 2.3mW.

Fig. 5.6 Block diagram of proposed power management.

0 200 400 600 800 1000

Fig. 5.7 P-V and I-V curve of PV cell. The x-axis is output voltage of PV cell. The left y-axis is load current. The right y-axis is output power.

5.3.2 Control Unit (CU)

Because there are two supply voltage sources of power management, we design a control unit to increase energy utility efficiency of overall system. The schematics of control unit are shown in Fig. 5.8.

When the PV cell supplies energy to voltage regulator, the direction of current flow is from node 1 to node 2. Thus the voltage of node 1 is higher then node 2. The op amp will outputs “1” to inverter and the MP1 will be turned on. In this case, the battery charger is active.

When the battery supplies energy to voltage regulator, the direction of current flow is from node 2 to node 1. Thus the voltage of node 2 is higher then node 1. The op amp will outputs “0” to inverter and the MP1 will be turned off. The MP2 will be turned on and the battery supplies power to voltage regulator. In this case, the control unit will disable the battery charger. With decreasing the current flow back to PV cell and disabling the battery charger, the energy of battery is used efficiently.

Note that the op amp and inverter shown in Fig. 5.4 are supplied by battery. In the beginning, the battery has no energy, so its output voltage is “0”. Thus the inverter will output “0” to turn on the MP1.

Fig. 5.8 The schematic of control unit (CU).

Fig. 5.9 Circuit of voltage regulator.

5.3.3 Voltage Regulator

The voltage regulator is composed of a differential amplifier, an inverter as a buffer and a power PMOS. The schematics of voltage regulator are shown in Fig. 5.9. With the MPAUX PMOS, as voltage of VREGU node dropping down, the MPAUX will supply more current to differential amplifier. Thus, the MPOUT will turn on rapidly and supply more current to VREGU node. When there is no load current, the MPAUX PMOS will slightly turn on and decrease the consumption power of differential amplifier.

5.3.4 Reference Voltage

The reference voltage circuit is shown in Fig. 5.10. The architecture is like Fig. 3.20. We remove the M2 from Fig. 3.20 for the power management system.

5.3.5 Voltage Generator

The power management system outputs tree different voltage level that is 0.5V, 1V and -0.5V. The 0.5V is generated by voltage regulator. The 1V and -0.5V are generated by charge pump.

Fig. 5.10 Reference voltage circuit for power management system.

The circuit of 1V generator and -0.5V generator is shown in Fig. 5.11. The CCLK, CCLKB, NCLK and NCLKB are supplied by voltage regulator. The 1V generator is a voltage doubler. It accepts the supply voltage of 0.5V from voltage regulator and output 1V to loading circuit. The negative voltage generator accepts GND as input voltage. When NCLK = 0.5V, the voltage of node 2 is 0V and the voltage of node 1 will be “0”. When NCLK = 0V, the voltage of node 1 will be -0.5V and voltage of node 2 will be discharged to 0V. Then, the output voltage will be -0.5V. When NCLK

= 0.5V, the voltage of node 2 will be -0.5V and node 1 is 0V. Thus, the OUT node will be -0.5V.

(a)

(b)

Fig. 5.11 (a) Circuit of voltage doubler. (b) Circuit of negative voltage generator.

5.3.6 Battery Charger

There are three charge pumps in the power management system. These charge pumps are powered by voltage regulator. The schematic of battery charger is shown in Fig. 5.12.

In this work, the clock generator is supplied by voltage regulator. The initial state is that node 1 = 0V and node 2 = 0V.When CLK=0.5V, the node 1 is 0.5V and node 2 is

“0.5V-VTn”. When CLKB=0.5V, the node 2 is “1V- VTn“ and the node 1 is 0.5V. As the node CLK is charge to 0.5V again, the node 1 is 1V. In first stage, the node 1 and node 2 will vibrate between 0.5V and 1V. The NMOS capacitors of second stage are connected to node 1 and node 2. Thus the node 3 and node 4 will vibrate between 1V and 1.5V. The node VOUT will be 2.5V.

5.3.7 Clock Generator

The clock system consists of two parts. The constant clock generator which simply generates constant clock is used to supply the battery charger and -0.5V generator.

The variable clock generator which changes the clock frequency dynamically is designed to supply 1V generator. It is controlled by the power efficiency optimization unit.

The proposed variable clock generator is shown in Fig. 5.13. It contains basic ring oscillator and insert two transmission gates between the inverters. The frequency of variable clock is controlled by the voltage bias of Vp and Vn. When Vp goes down and Vn goes high, the delay time of transmission gate is short, and the frequency of the clock rise, vice versa. Vp and Vn is biased by the net bias circuit. The variable clock generator achieves wide frequency range and low power. It can provide frequency range from 33MHz to 300MHz. the power consumption is 29uW when operated at 300MHz including the net bias circuit.

5.3.8 Power Efficiency Optimization Unit

The power efficiency optimization unit controls the clock frequency of variable clock generator and optimizes the power efficiency of 1V generator according to the loading condition. The power efficiency unit used voltage detector to detect the loading condition of the 1V generator output. The proposed voltage detector is shown in Fig. 5.14. When the output voltage of 1V generator decrease, vd will increase and it will be compare to the vref. The detecting flag will be sent according to the result of comparison.

If the load current increase and output voltage of 1V generator is below 900mV, the voltage detector will sent the flag signal and the 5-bits counter will count up to speed up the clock frequency of variable clock generator. The high frequency will give more pumping strength to pump the output voltage. If the load current decrease and output voltage of 1V generator is above 900mV, the flag will disable and the clock frequency of variable clock generator will decrease until reach the minimum clock frequency.

Fig. 5.12 Circuit of battery charger.

Vp

Net Bias

Vn

Circiut counter

Detecting Flag

Fig. 5.13 Circuit of variable clock generator.

Fig. 5.14 Architecture of voltage detector.

Fig. 5.15 Layout view of power management system for solar energy harvesting applications.