When using our delay monitor circuits, the reason of detecting PMOS variations first is that its size is smaller than the circuit of detecting NMOS variations coming first.
If we detect NMOS variations first, the NMOS variations must dominate the delay, in other words, the PMOS size must be much larger than NMOS. The required size may be PMOS with 400nm/90 and NMOS with 100nm/90nm to make PMOS have twice driving force to NMOS. The area is almost 2.5 times larger than the circuit which detecting PMOS variations first.
As for delay monitor issue, we know that our delay monitor circuits can separate each kind of variations clearly either PMOS or NMOS, but the drawback is the worse case. In worse case our circuits will confuse and may apply the wrong body bias to NMOS. However, detecting PMOS will not have this problem. So we can always aplly the correct PMOS body bias. On the other hand, our leakage monitor circuits can tolerate large variations but the drawback is we need a precise comparator.
Chapter 4
Experimental Results
We implement our circuits in HSPICE, and use memory compiler from FARADAY to build single port SRAM and dual port SRAM as our test circuits. We use the UMC 90nm CMOS library to implement our circuits.
4.1 Single Port SRAM
We use memory compiler to compile a 64-word (each word has 32 bits) single port SRAM. We use Monte-Carlo method to test the failure probability. We choose 640 cells per circuit as our test samples, and the result is shown in Table 4.1 to Table 4.4.
In Table 4.1, each test circuit suffers from both inter-die and intra-die variations.
The value of inter-die variations is 125mv and the value of intra-die variations is 75mv. 1 The meaning of each element is as follows. The first column represents the process corner of PMOS and NMOS respectively. For example, the first column and the bottom row represents PMOS has low threshold voltage and NMOS has
1We add the inter-die and intra-die variations to the MOS parameter ‘delvto’. We use the following two statements to declare these two parameters in HSPICE:
.param vthnmosrandom=agauss(nmos-interdie-value, 0.075, 3) .param vthpmosrandom=agauss(pmos-interdie-value, 0.075, 3)
We also add the statement: ‘delvto=vthnmosrandom’ to all NMOS, and add the statement
‘delvto=vthpmosrandom’ to all PMOS
low threshold voltage. The second column represents the original circuits without using body bias. The sub-columns 0 and 1 represent the action of ‘write 0 then read the data out’ and ‘write 1 then read it out’ respectively. Other numerical values represent the failure numbers in 640 times test. The third column represents that we only use NMOS body bias and we assume that all predictions are correct.
The fourth column presents the result of using the circuits in [1]. The fifth column represents that we use both PMOS and NMOS body bias and we assume that all predictions are correct. And the final column represents the results of using our circuits.
Table 4.1: Total failure number of the single port SRAM with 125mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that our circuits can always improve the yield. The ‘0’ and ‘1’ in second row represent the action of ‘write 0 then read the data out’ and ‘write 1 then read it out’
respectively. The numerical values in row 3 to row10 express the failure numbers in 640times test.
Without Only NMOS Both PMOS
125mv body bias body bias [1] and NMOS Ours
body bias
According to our argument in Section 3.3.2, we know that if we do not consider the effect of PMOS variations, we may get the wrong process corner. Here we show the results while we get the wrong process corner. We can see that using traditional circuits will get worse results than without body bias when PMOS with
high threshold and NMOS has low threshold, NMOS will be predicted as having normal threshold. Therefore, zero body bias will be used and the yield will be the same as without body bias circuits. We can see two things in the last two columns:
first, when the inter-die variations are 125mv, our improved circuits will always get the right prediction; second, our yield improvement will be better than the technique using only NMOS body bias.
Table 4.2: Total failure number of the single port SRAM with 150mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that when PMOS and NMOS both have high threshold the yield degrades very much, and using only NMOS body bias can not satisfy the requirement of yield improvement.
Without Only NMOS Both PMOS
150mv body bias body bias [1] and NMOS Ours
body bias
In Table 4.2, all experimental setups are the same as in Table 4.1 except for the 150mv assumption for inter-die variations. We can see that when PMOS and NMOS both have high threshold the yield degrades very much, and using only NMOS body bias can not satisfy the requirement of yield improvement. The yield improvement of using both PMOS and NMOS body bias is obviously.
In Table 4.3, all experimental setups are the same as in Table 4.1 except for the 175mv assumption for inter-die variations. Here we notice that our circuits will no longer always get the right predictions. When PMOS have high threshold and
Table 4.3: Total failure number of the single port SRAM with 175mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that even we get the wrong predictions, our yield are still very close to the right prediction of only use NMOS body bias.
Without Only NMOS Both PMOS
175mv body bias body bias [1] and NMOS Ours
body bias
NMOS have normal or low threshold, our circuits will get the right process corner of PMOS but get the wrong prediction of NMOS. Even we get the wrong predictions, our yield are still very close to the right prediction of only use NMOS body bias.
In Table 4.4 all experimental setups are the same as in Table 4.1 except for the 200mv assumption for inter-die variations. In this table we can see that using body bias can not improve much on the yield. This is because the inter-die variations are too large, and this will limit the effect of body bias.
4.2 Dual Port SRAM
Similar to single port SRAM, we use memory compiler to build a 64-words (each word has 32 bits) dual port SRAM in our test circuits. The dual port SRAM has two ports: port A and port B. We use port A to write the data to SRAM cell and use port B to read out the stored data. We use Monte-Carlo method to test the failure probability. We choose 640 cells per circuit as our test samples, and the
Table 4.4: Total failure number of the single port SRAM with 200mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that using body bias can not improve much on the yield.
Without Only NMOS Both PMOS
200mv body bias body bias [1] and NMOS Ours
body bias
result shows in Table 4.5 to Table 4.8. The means of each element are the same as Table 4.1 to Table 4.4.
In Table 4.5 we can see a huge difference to single port SRAM. When both PMOS and NMOS have high threshold voltage, we get the results of 640 failures in read 1. This means that the failure probability is 100%, and the failure is caused by the unsuccessful writing 1 to SRAM cell, hence we always get the 0 at output signal. This problem almost can not be solved by using only NMOS body bias. On the other hand, using both PMOS and NMOS body bias can solve the problem very well.
In Table 4.6, we see that our circuits can not solve the all failure problem happened at both PMOS and NMOS having high threshold voltage. We find that the corner point of all failure happened is when both PMOS and NMOS having 115mv inter-die voltage higher than normal threshold, and we use 500mv body bias still can not fix so much inter-die variations. Finally, the yield at 150mv inter-die variations can not improve at high-high case.
Table 4.5: Total failure number of the dual port SRAM with 125mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that when both PMOS and NMOS have high threshold voltage, we get the results of 640 failures in read 1. This means that the failure probability is 100%
Without Only NMOS Both PMOS
125mv body bias body bias [1] and NMOS Ours
body bias
Table 4.6: Total failure number of the dual port SRAM with 150mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that our circuits can not solve the all failure happened when both PMOS and NMOS having high threshold voltage.
Without Only NMOS Both PMOS
150mv body bias body bias [1] and NMOS Ours
body bias
Table 4.7: Total failure number of the dual port SRAM with 175mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that our circuits can improve the yield much better than using only NMOS body bias, especially for PMOS having high threshold voltage and NMOS having normal threshold voltage.
Without Only NMOS Both PMOS
175mv body bias body bias [1] and NMOS Ours
body bias
PMOS–NMOS 0 1 0 1 0 1 0 1 0 1
high – high 0 640 0 640 0 640 0 640 2 640
high – zero 15 307 15 307 24 455 3 32 8 45
high – low 30 41 14 30 30 41 8 9 17 15
zero – high 15 3 3 0 3 0 3 0 3 0
zero – low 9 0 5 0 5 0 5 0 5 0
low – high 10 35 5 12 10 35 0 7 0 7
low – zero 0 19 0 19 0 25 0 0 0 0
low – low 15 17 7 8 7 8 3 5 3 5
In Table 4.8, we can see that there is another all failure happened at the case of PMOS having high threshold and NMOS having normal threshold. In this case, using only NMOS body bias can not improve the yield, but using both PMOS and NMOS body bias can have obviously improvement.
Table 4.8: Total failure number of the dual port SRAM with 200mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that there is another all failure happened at the case of PMOS having high threshold and NMOS having normal threshold. In this case, using only NMOS body bias can not improve the yield, but using both PMOS and NMOS body bias can have obviously improvement.
Without Only NMOS Both PMOS
200mv body bias body bias [1] and NMOS Ours
body bias
PMOS–NMOS 0 1 0 1 0 1 0 1 0 1
high – high 0 640 0 640 0 640 0 640 0 640
high – zero 0 640 0 640 0 640 15 141 19 192
high – low 71 152 53 99 71 152 25 55 61 89
zero – high 61 191 13 14 13 14 13 14 13 14
zero – low 21 17 8 0 8 0 8 0 8 0
low – high 35 73 15 39 35 73 13 28 13 28
low – zero 8 28 8 28 11 34 0 6 0 6
low – low 27 34 23 30 23 30 16 17 16 17
Chapter 5 Conclusions
In this thesis, we have proposed some improved circuits of delay monitor and leakage monitor. These circuits can correctly detect both PMOS and NMOS variations, and improve the yield by decreasing the influence of inter-die variations. All of our test circuits are built by a widely used memory compiler. The experimental results show that some situations can not improve yield by using only NMOS body bias, but using both PMOS and NMOS body bias can improve significantly. Besides, the results also show that our proposed circuits can almost get the right predictions of variations. Even we get wrong prediction of NMOS, our yield can still improve by adapting correct PMOS body bias. We conclude that our yield is always better than only using NMOS body bias circuits.
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作者簡歷
蕭家棋，民國七十二年六月出生於彰化縣。民國九十五年八月畢業於國立交通大 學電子工程學系，並於同年九月進入國立交通大學電子工程研究所系統組就讀。
民國九十七年十月碩士畢業。