Single Port SRAM

We use memory compiler to compile a 64-word (each word has 32 bits) single port SRAM. We use Monte-Carlo method to test the failure probability. We choose 640 cells per circuit as our test samples, and the result is shown in Table 4.1 to Table 4.4.

In Table 4.1, each test circuit suffers from both inter-die and intra-die variations.

The value of inter-die variations is 125mv and the value of intra-die variations is 75mv. ¹ The meaning of each element is as follows. The first column represents the process corner of PMOS and NMOS respectively. For example, the first column and the bottom row represents PMOS has low threshold voltage and NMOS has

1We add the inter-die and intra-die variations to the MOS parameter ‘delvto’. We use the following two statements to declare these two parameters in HSPICE:

.param vthnmosrandom=agauss(nmos-interdie-value, 0.075, 3) .param vthpmosrandom=agauss(pmos-interdie-value, 0.075, 3)

We also add the statement: ‘delvto=vthnmosrandom’ to all NMOS, and add the statement

‘delvto=vthpmosrandom’ to all PMOS

low threshold voltage. The second column represents the original circuits without using body bias. The sub-columns 0 and 1 represent the action of ‘write 0 then read the data out’ and ‘write 1 then read it out’ respectively. Other numerical values represent the failure numbers in 640 times test. The third column represents that we only use NMOS body bias and we assume that all predictions are correct.

The fourth column presents the result of using the circuits in [1]. The fifth column represents that we use both PMOS and NMOS body bias and we assume that all predictions are correct. And the final column represents the results of using our circuits.

Table 4.1: Total failure number of the single port SRAM with 125mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that our circuits can always improve the yield. The ‘0’ and ‘1’ in second row represent the action of ‘write 0 then read the data out’ and ‘write 1 then read it out’

respectively. The numerical values in row 3 to row10 express the failure numbers in 640times test.

Without Only NMOS Both PMOS

125mv body bias body bias [1] and NMOS Ours

body bias

According to our argument in Section 3.3.2, we know that if we do not consider the effect of PMOS variations, we may get the wrong process corner. Here we show the results while we get the wrong process corner. We can see that using traditional circuits will get worse results than without body bias when PMOS with

high threshold and NMOS has low threshold, NMOS will be predicted as having normal threshold. Therefore, zero body bias will be used and the yield will be the same as without body bias circuits. We can see two things in the last two columns:

first, when the inter-die variations are 125mv, our improved circuits will always get the right prediction; second, our yield improvement will be better than the technique using only NMOS body bias.

Table 4.2: Total failure number of the single port SRAM with 150mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that when PMOS and NMOS both have high threshold the yield degrades very much, and using only NMOS body bias can not satisfy the requirement of yield improvement.

Without Only NMOS Both PMOS

150mv body bias body bias [1] and NMOS Ours

body bias

In Table 4.2, all experimental setups are the same as in Table 4.1 except for the 150mv assumption for inter-die variations. We can see that when PMOS and NMOS both have high threshold the yield degrades very much, and using only NMOS body bias can not satisfy the requirement of yield improvement. The yield improvement of using both PMOS and NMOS body bias is obviously.

In Table 4.3, all experimental setups are the same as in Table 4.1 except for the 175mv assumption for inter-die variations. Here we notice that our circuits will no longer always get the right predictions. When PMOS have high threshold and

Table 4.3: Total failure number of the single port SRAM with 175mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that even we get the wrong predictions, our yield are still very close to the right prediction of only use NMOS body bias.

Without Only NMOS Both PMOS

175mv body bias body bias [1] and NMOS Ours

body bias

NMOS have normal or low threshold, our circuits will get the right process corner of PMOS but get the wrong prediction of NMOS. Even we get the wrong predictions, our yield are still very close to the right prediction of only use NMOS body bias.

In Table 4.4 all experimental setups are the same as in Table 4.1 except for the 200mv assumption for inter-die variations. In this table we can see that using body bias can not improve much on the yield. This is because the inter-die variations are too large, and this will limit the effect of body bias.