Dual Port SRAM

Similar to single port SRAM, we use memory compiler to build a 64-words (each word has 32 bits) dual port SRAM in our test circuits. The dual port SRAM has two ports: port A and port B. We use port A to write the data to SRAM cell and use port B to read out the stored data. We use Monte-Carlo method to test the failure probability. We choose 640 cells per circuit as our test samples, and the

Table 4.4: Total failure number of the single port SRAM with 200mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that using body bias can not improve much on the yield.

Without Only NMOS Both PMOS

200mv body bias body bias [1] and NMOS Ours

body bias

result shows in Table 4.5 to Table 4.8. The means of each element are the same as Table 4.1 to Table 4.4.

In Table 4.5 we can see a huge difference to single port SRAM. When both PMOS and NMOS have high threshold voltage, we get the results of 640 failures in read 1. This means that the failure probability is 100%, and the failure is caused by the unsuccessful writing 1 to SRAM cell, hence we always get the 0 at output signal. This problem almost can not be solved by using only NMOS body bias. On the other hand, using both PMOS and NMOS body bias can solve the problem very well.

In Table 4.6, we see that our circuits can not solve the all failure problem happened at both PMOS and NMOS having high threshold voltage. We find that the corner point of all failure happened is when both PMOS and NMOS having 115mv inter-die voltage higher than normal threshold, and we use 500mv body bias still can not fix so much inter-die variations. Finally, the yield at 150mv inter-die variations can not improve at high-high case.

Table 4.5: Total failure number of the dual port SRAM with 125mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that when both PMOS and NMOS have high threshold voltage, we get the results of 640 failures in read 1. This means that the failure probability is 100%

Without Only NMOS Both PMOS

125mv body bias body bias [1] and NMOS Ours

body bias

Table 4.6: Total failure number of the dual port SRAM with 150mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that our circuits can not solve the all failure happened when both PMOS and NMOS having high threshold voltage.

Without Only NMOS Both PMOS

150mv body bias body bias [1] and NMOS Ours

body bias

Table 4.7: Total failure number of the dual port SRAM with 175mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that our circuits can improve the yield much better than using only NMOS body bias, especially for PMOS having high threshold voltage and NMOS having normal threshold voltage.

Without Only NMOS Both PMOS

175mv body bias body bias [1] and NMOS Ours

body bias

PMOS–NMOS 0 1 0 1 0 1 0 1 0 1

high – high 0 640 0 640 0 640 0 640 2 640

high – zero 15 307 15 307 24 455 3 32 8 45

high – low 30 41 14 30 30 41 8 9 17 15

zero – high 15 3 3 0 3 0 3 0 3 0

zero – low 9 0 5 0 5 0 5 0 5 0

low – high 10 35 5 12 10 35 0 7 0 7

low – zero 0 19 0 19 0 25 0 0 0 0

low – low 15 17 7 8 7 8 3 5 3 5

In Table 4.8, we can see that there is another all failure happened at the case of PMOS having high threshold and NMOS having normal threshold. In this case, using only NMOS body bias can not improve the yield, but using both PMOS and NMOS body bias can have obviously improvement.

Table 4.8: Total failure number of the dual port SRAM with 200mv assumption for inter-die variations and 75mv assumption for intra-die variations. In this table we can see that there is another all failure happened at the case of PMOS having high threshold and NMOS having normal threshold. In this case, using only NMOS body bias can not improve the yield, but using both PMOS and NMOS body bias can have obviously improvement.

Without Only NMOS Both PMOS

200mv body bias body bias [1] and NMOS Ours

body bias

PMOS–NMOS 0 1 0 1 0 1 0 1 0 1

high – high 0 640 0 640 0 640 0 640 0 640

high – zero 0 640 0 640 0 640 15 141 19 192

high – low 71 152 53 99 71 152 25 55 61 89

zero – high 61 191 13 14 13 14 13 14 13 14

zero – low 21 17 8 0 8 0 8 0 8 0

low – high 35 73 15 39 35 73 13 28 13 28

low – zero 8 28 8 28 11 34 0 6 0 6

low – low 27 34 23 30 23 30 16 17 16 17

Chapter 5 Conclusions

In this thesis, we have proposed some improved circuits of delay monitor and leakage monitor. These circuits can correctly detect both PMOS and NMOS variations, and improve the yield by decreasing the influence of inter-die variations. All of our test circuits are built by a widely used memory compiler. The experimental results show that some situations can not improve yield by using only NMOS body bias, but using both PMOS and NMOS body bias can improve significantly. Besides, the results also show that our proposed circuits can almost get the right predictions of variations. Even we get wrong prediction of NMOS, our yield can still improve by adapting correct PMOS body bias. We conclude that our yield is always better than only using NMOS body bias circuits.

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作者簡歷

蕭家棋，民國七十二年六月出生於彰化縣。民國九十五年八月畢業於國立交通大 學電子工程學系，並於同年九月進入國立交通大學電子工程研究所系統組就讀。

民國九十七年十月碩士畢業。