Dissertation Organization

This dissertation is organized as follow:

In Chapter 2, we discuss the device performance of OTFTs that incorporates high-κ HfLaO as the gate dielectric. The effects of surface treatment on TaN gate electrode are discussed along with the electric characteristics of OTFTs. The focus of this research is the integration of pentance based OTFT with high-κ HfLaO to reach good electrical characteristics such as a low SS and small VT.

In Chapter 3, we study the integration of pentacene OTFTs with a high-κ HfLaO dielectric onto flexible substrates.

In order to further extend the function of OTFTs, we develop a pentacene OTFT nonvolatile memory fabricated on a flexible polyimide substrate in Chapter 4. This memory function has been achieved by using a high-κ dielectric as charge trapping,

HfAlO capping SiON p-MOSFETs is mentioned in Chapter 5. The mechanisms of flatband voltage shift are discussed. By optimizing thickness of SiON, the good device performance of MoN/HAlO/SiON p-MOSFET can be reached.

A summary of the research work carried out is given in Chapter 6.

Table 1-1 Comparison of relevant properties for high-k candidates [1.4]. HfO2 25 5.8 1.4 Monoclinic, Tetragonal, Cubic

ZrO2 25 5.8 1.5 Monoclinic, Tetragonal, Cubic

Fig. 1-1. Leakage current versus voltage for various thickness of SiO2 layers [1.1].

Fig. 1-2. Static dielectric constant versus band gap for candidate gate oxides [1.5].

Fig. 1-3. Molcular structure of common p-type organic semiconductors: Pentacene, 6T (sexthiophene), P3HT (regioregular poly(3-hexylthiophene)), F8T2

Fig. 1-4. Various device structures of OTFTs.

Chapter 2

Low Sub-threshold Swing HfLaO/Pentacene Organic Thin Film Transistors

2.1 Introduction

Poly-Si thin-film transistors (TFTs) [2.1]-[2.6] are currently used for active matrix liquid crystal displays (AMLCDs) on glass substrates. These poly-Si TFTs are operated in inversion mode, and the ion-implantation for the n⁺ source-drain requires activation using furnace annealing at 600^oC, typically for ~12 hours. This extended annealing slows down the process sequence and the large thermal budget is unfavorable for environment energy conservation. In contrast, organic TFTs (OTFTs) [2.7]-[2.9] can be processed with a significantly lower thermal budget, and without requiring ion implantation or an extended dopant activation period. This is because the OTFTs can be operated in the accumulation mode, where ohmic-like source-drain contacts are used rather than ion-implanted n⁺ source-drain regions. Unfortunately, for

issues. Besides displaying a high-κ　value of up to 24, HfLaO permits low-temperature processing due to the strong metal-oxide bond enthalpy of both Hf-O and La-O [2.13]. The adding La2O3 into HfO2 is especially important to decrease the leakage current at low temperature process due to the larger conduction band offset of La2O3 (2.3 eV to Si) than that of HfO2 (1.5 eV to Si) [2.14]. The HfLaO MOSFET also shows less Fermi-level pinning than using HfO2 [2.10]-[2.12].

2.2 Experimental Details

The devices were fabricated on a thick SiO2 layer grown on Si wafers to mimic poly-Si TFTs fabricated on glass substrates [2.2]. A 50 nm thick TaN gate electrode was then deposited on the SiO2/Si, through a shadow mask, using reactive sputtering.

The surface of the TaN gate was subsequently treated with an NH3 plasma to improve the gate leakage current [2.14]-[2.16]. Such nitrogen plasma treatment is the key factor to achieve low leakage current and small EOT in previous DRAM capacitors [2.14]-[2.16]. The 20 nm thick HfLaO gate dielectric was then deposited by electron beam evaporation and annealed in O2 at 350^oC for 10 min. Next, pentacene (Aldrich Chemical Co.) was evaporated through a shadow mask onto the sample to form an active layer 70 nm thick. This evaporation was performed at a deposition rate of 0.5

μm and width of 2000 μm. We also deposited Au directly onto HfLaO/TaN to make 200×200 μm² capacitors to analyze the dielectric properties. The devices were characterized using an HP4156C semiconductor parameter analyzer and an HP4284A precision LCR meter, under dark and air ambient conditions.

2.3 Results and Discussion

In Figure 2-1 we show the schematic diagram of OTFT. The J-V characteristics of Au/HfLaO/TaN capacitors are shown in Figure 2-2. The NH3 plasma treatment improves the leakage current of both electron injection from top Au/HfLaO and bottom HfLaO/TaN with close capacitance density shown in Figure 2-3. It is important to notice that the leakage current is much worse as electron injected from bottom interface, which is consistent with previous Analog/RF and DRAM MIM capacitors [2.14]-[2.16]. However, such bottom electron injection is needed for the negative VG used in p-channel OTFTs. The data with NH3 plasma treatment indicate a leakage current of 5.1×10^-7 A/cm² at 2 V, at a capacitance density as high as 950 nF/cm². This gives an equivalent-oxide-thickness (EOT) of only 3.6 nm and a high-κ

The output characteristics (ID-VD) of a high-κ HfLaO/pentacene OTFT are displayed in Figure 2-4. The ID-VD characteristics with NH3 plasma treatment are well-behaved, and suggest possible operation at 2 V, which has the advantage of reducing the power consumption (ID×VD) in circuit operations. The ID-VD curves without NH3 plasma treatment show poor characteristics that are due to high gate leakage current induced ID lowering. The transfer characteristics (ID-VG), as shown in Figure 2-5, enable the extraction of the mobility (μ) and threshold voltage (VT) from the –ID1/2 vs. VG plot. The device with NH3treatment improves on current (Ion), SS and off current (Ioff). The Ion improvement is not due to the pentacene, since the surface roughness and grain sizes are similar shown in Figure 2-6. The performance improvements are due to NH3 plasma treatment to reduce gate leakage current. The device with NH3 plasma treatment shows a record small SS of only 78 mV/decade, a VT of -1.3 V, and a good μ of 0.71 cm²/V.s, along with an on-off-state drive current

where Cdep is the depletion capacitance density of pentacene, Cit is the capacitance density from charged interface traps and Ci is the gate capacitance density. Here the

that for poly-Si TFTs [2.1]-[2.6] and OTFTs [2.7]-[2.9] and is close to theoretical minimum value of 0.06 V/decade at room temperature. We attribute these results to the high Ci of 950 nF/cm² and small EOT of 3.6 nm, resulting from the use of advanced high-κ HfLaO dielectric even processed at low temperature.

The important device parameters are detailed in Table I, where the data from conventional n-channel poly-Si TFTs using solid phase crystallization (SPC) and LPCVD or PECVD oxides [2.3]-[2.5] are included for comparison. Note that the μCi

term is directly related to ID (W/2L×μCi(VG-VT)²), normalized to the channel length L, channel width W, and over-drive voltage of VG-VT. The performance of our HfLaO OTFTs is comparable with that of poly-Si TFTs, which incorporate LPCVD and PECVD TEOS oxides [2.3]-[2.5], but with the additional merits of a better SS, lower VT, faster process sequence and lower thermal budget process.