[5.1] D. S. Yu, A. Chin, C. H. Wu, M.-F. Li, C. Zhu, S. J. Wang, W. J. Yoo, B. F.
Hung and S. P. McAlister, “Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference,” in IEDM Tech. Dig., 2005, pp.
649-652.
[5.2] P. F. Hsu, Y. T. Hou, F. Y. Yen, V. S. Chang, P. S. Lim, C. L. Hung, L. G.
Yao, J. C. Jiang, H. J. Lin, J. M. Chiou, K. M. Yin, J. J. Lee, R. L. Hwang, Y.
IEDM Tech. Dig., 2006, pp. 617-620.
[5.4] K. Akiyama, W. Wang, W. Mizubayashi, M. Ikeda, H. Ota, T. Nabatame and A. Toriumi, “VFB roll-off in HfO2 gate stack after high temperature annealing process - a crucial role of out-diffused oxygen from HfO2 to Si -,” in VLSI Symp. Tech. Dig., 2007, pp. 72-73.
[5.5] S. C. Song, C. S. Park, J. Price, C. Burham, R. Choi, H. C. Wen, K. Choi, H.-H.
Tseng, B. H. Lee, and R. Jammy, “Mechanism of Vfb roll-off with high work function metal gate and low temperature oxygen incorporation to achieve PMOS band edge work function,” in IEDM Tech. Dig., 2007, pp. 337-340.
[5.6] C. F. Cheng, C. H. Wu, N. C. Su, S. J. Wang, S. P. McAlister and Albert Chin,
“Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions,” in IEDM Tech. Dig., 2007, pp. 333-336.
[5.7] S. Natarajan, M. Armstrong, M. Bost, R. Brain, M. Brazier, C-H Chang, V.
Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O.
Golonzka, W. Han, J. He, R. Heussner, R. James, I. Jin, C. Kenyon, S. Klopcic, S-H. Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg, J. Neirynck, P. Packan, S. Pae, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone, T. Troeger, C. Weber, M. Yang, A. Yeoh, K.
Zhang, “A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171 μm2 SRAM cell size in a 291Mb array,” in IEDM Tech. Dig., 2008, pp. 941-943.
[5.8] S. Natarajan, J. Huang, P. D. Kirsch, D. Heh, C.Y. Kang, G. Bersuker, M.
Hussain, P. Majhi, P. Sivasubramani, D. C. Gilmer, N. Goel, M. A.
in IEDM Tech. Dig., 2008, pp. 45-48.
[5.9] H. N. Alshareef, H. R. Harris, H.C. Wen, C. S. Park, C. Huffman1, K. Choi, H.
F. Luan, P. Majhi, B. H. Lee, R. Jammy, D. J. Lichtenwalner, J. S. Jur, and A.
I. Kingon, “Thermally stable n-metal gate MOSFETs using La-incorporated HfSiO dielectric,” in VLSI Symp. Tech. Dig., 2006, pp. 7-8.
[5.10] Y. H. Wu, M. Y. Yang, A. Chin, and W. J. Chen, “Electrical characteristics of high quality La2O3 dielectric with equivalent oxide thickness of 5Å,” IEEE Electron Device Lett., vol. 21, no. 7, pp. 341-343, Jul. 2000.
[5.11] A. Chin, C. C. Liao, C. H. Lu, W. J. Chen, and C. Tsai, “Device and reliability of high-k Al2O3 gate dielectric with good mobility and low Dit,” in VLSI Symp.
Tech. Dig., 1999, p.135-136.
[5.12] H.-J. Li, and M. I. Gardner, “Dual high-κ gate dielectric with poly gate electrode: HfSiON on nMOS and Al2O3 capping layer on pMOS,” IEEE Electron Device Lett., vol. 26, no.7, pp. 441-444, Jul. 2005.
[5.13] V. S. Chang, Lars-Åke Ragnarsson, H. Y. Yu, M. Aoulaiche, T. Conard, K.
Yin, T. Schram, J. W. Maes, S. D. Gendt, and S. Biesemans, “Effects of Al2O3
dielectric cap and nitridation on device performance, scalability, and reliability for advanced high-κ/metal gate pMOSFET applications,” IEEE Trans.
Electron Devices, vol. 54, no.10, pp. 1258-1263, Oct. 2007.
[5.14] N. Mise, T. Morooka, T. Eimori, S. Kamiyama, K. Murayama, M. Sato, T.
[5.16] X.-W. Wang, A. Balasinski, T. P. Ma, and Y. Nishioka, “Pre-oxidation fluorine implantation into Si process-related MOS characteristics,” J.
Electrochem. Soc., vol. 139, no. 1, pp. 238-241, Jan. 1992.
[5.17] M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K. Shiga, J.
Yugami, J. Tsuchimoto, Y. Ohno, and M. Yoneda, “Fluorine incorporation into HfSiON dielectric for Vth control and its impact on reliability for poly-Si gate pFET,” in IEDM Tech. Dig., 2005, pp. 413-416.
[5.18] S. Tsujikawa, H. Umeda, T. Kawahara, Y. Kawasaki, K. Shiga,T. Yamashita, T. Hayashi, J. Yugami, Y. Ohno, and M. Yoneda, “A simple approach to optimizing ultra-thin SiON gate dielectrics independently for n- and p-MOSFETs,” in IEDM Tech. Dig., 2005, pp. 824-827.
[5.19] T. Hayashi, M. Mizutani, M. Inoue, J. Yugami, J. Tsuchimoto, M. Anma, S.
Komori, K. Tsukamoto, Y. Tsukamoto,K. Nii, Y. Nishida, H. Sayama, T.
Yamashita, H. Oda, T. Eimori, and Y. Ohji, “Vth-tunable CMIS platform with high-k gate dielectrics and variability effect for 45nm node,” in IEDM Tech.
Dig., 2005, pp. 906-909.
[5.20] J. Hauser, CVC NCSU Software, Version 5.0, 2000, Raleigh, NC: Dept. Elect.
Computer Eng., North Carolina State Univ.
[5.21] A. E.-J. Lim, R. T. P. Lee, G. S. Samudra, D.-L. Kwong, and Y.-C. Yeo,
“Modification of molybdenum gate electrode work Function via (La-, Al-induced) dipole effect at high-k/SiO2 interface,” IEEE Electron Device Lett., vol. 29, no. 8, pp. 848-851, Aug. 2008.
[5.22] J. F. Moulder, Handbook of X-ray Photoelectron Spectroscopy, 2nd ed.,
formation during chemical vapor deposition of amorphous Al2O3 thin films on Si(100),” Appl. Phy. Lett., vol. 75, no .25, pp. 4001-4003, Dec. 1999.
[5.24] S. Heo, M. Chang, Y. Ju, S. Jung, and H. Hwang, “The effect of KrF laser
annealing within an ultrashort time on metal-alumina-nitride-oxide-silicon-type flash memory devices,” Appl. Phy.
Lett., vol. 93, no. 17, p. 172115, Oct. 2008.
[5.25] J. Robertson, O. Sharia, and A. A. Demkov, “Fermi level pinning by defects in HfO2-metal gate stack,” Appl. Phy. Lett., vol. 91, no. 13, p. 132912, Sep. 2007.
[5.26] L. R. C. Fonseca, D. Liu, and J. Robertson, “P-type Fermi level pinning at a Si:Al2O3 model interface,” Appl. Phy. Lett., vol. 93, no. 12, p. 122905, Sep.
2008.
[5.27] S.-I. Saito, K. Torii, Y. Shimamoto, O. Tonomura, D. Hisamoto, T. Onai, M.
Hiratani, Shin’ichiro Kimura, Y. Manabe, M. Caymax, and J. W. Maes,
“Remote-charge-scattering limited mobility in field-effect transistors with SiO2
and Al2O3/SiO2 gate stacks,” J. Appl. Phys., vol. 98, no. 11, p. 113706, Dec.
2005.
Publication Lists:
(A) International Journal:
[1] H.-L. Cheng, J.-W. Lin, M. F. Jang, F.-C. Wu, W.-Y. Chou, M.-H. Chang, and C.-H. Chao, “Long-Term Operations of Polymeric Thin-Film Transistors:
Electric-Field-Induced Intrachain Order and Charge Transport Enhancements of Conjugated Poly(3-hexylthiophene),” Macromolecules vol. 42, no. 21, pp.
8251–8259, Nov. 2009.
[2] M. F. Chang, P. T. Lee, and A. Chin, “Low Threshold Voltage MoN/HfAlO/SiON p-MOSFETs with 0.85-nm EOT,” IEEE Electron Device Lett. vol. 30, no. 8, pp. 861–863, Aug. 2009.
[3] M. F. Chang, P. T. Lee, S. P. McAlister, and A. Chin, “Small Sub-threshold-Swing and Low-Voltage, Flexible Organic Thin Film Transistors which use HfLaO as the Gate Dielectric,” IEEE Electron Device Lett. vol. 30, no. 2, pp. 133–135, Feb. 2009.
[4] A. Chin, M. F. Chang, S. H. Lin, W. B. Chen, P. T. Lee, F. S. Yeh, C. C. Liao, M.-F. Li, N. C. Su and S. J. Wang, “Flat Band Voltage Control on Low Vt
Metal-Gate/High-κ CMOSFETs with small EOT,” Microelectronics Engineering, vol. 86, pp. 1728–1732, Jul. 2009
[5] M. F. Chang, P. T. Lee, S. P. McAlister, and A. Chin, “A Flexible Organic Pentacene Non-volatile Memory Based on High-k Dielectric Layers,” Appl. Phy.
Lett. Vol. 93, no. 23, p.233302, Dec. 2008.
[6] M. F. Chang, P. T. Lee, S. P. McAlister, and A. Chin, “Low Subthreshold
(B) Conferences & Proceeding
[1] A. Chin, M. F. Chang, P. T. Lee and C. H. Wu, “High Performance Organic TFT and Nonvolatile Memory Using High-k Dielectric Layers,” Progress In Electromagnetics Research Symposium (PIERS), Xi'an, China, March 22-26, 2010 (Invited).
[2] A. Chin, M. F. Chang, S. H. Lin, W. B. Chen, P. T. Lee, F. S. Yeh, C. C. Liao, M.-F. L, N. C. Su and S. J. Wang “Flat Band Voltage Control on Low Vt
Metal-Gate/High-κ CMOSFETs with small EOT,” 16th Bi-Annual Conference on Insulating Films on Semiconductors (INFOS), Cambridge University, UK, Jun. 29-Jul. 1, 2009 (Invited).
[3] A. Chin, M. F. Chang, C. C. Liao, N. C. Su, P. T. Lee, and S. J. Wang, “Low Vt Metal-Gate/High-κ CMOS Using Laser-Irradiation Annealing and Reflection,”
International Symp. on Advanced Gate Stack Technology (ISAGST), (IEEE), Sep.29-Oct. 1, Austin, Texas USA. 2008 (Invited).
[4] M. F. Chang, P. T. Lee and A. Chin, “Low Voltage and Small Subthreshold Swing HfLaO/Pentacene Organic TFTs,” Int’l Solid-State Devices & Materials Conf. (SSDM), (IEEE), pp. 1138-1139, Japan, Sep. 2008.
[5] N. C. Su, C. H. Wu, M. F. Chang, J. Z. Huang, S. J. Wang, W. C. Lee, P. T.
Lee, H. L. Kao and A. Chin, “Gate-First Low Vt Al/TaN/Ir/HfLaO p-MOSFET Using Simple Laser Annealing,” 66th Device Research Conference (DRC)