Chapter 1 Introduction
2.4. Summary
We have fabricated and characterized low voltage OTFTs that incorporate high-κ HfLaO as the gate dielectric. These devices exhibit good electrical
Table 2-1 Comparison of p-channel HfLaO/pentacene OTFTs with n-channel poly-Si
pentacene poly-Si by SPC poly-Si by SPC poly-Si by SPC
Ci (nF/cm2) 950 43.1 57.5 86.3
Fig. 2-1. Schematic diagram of HfLaO/pentacene OTFTs and Au/HfLaO/TaN MIM devices.
-3 -2 -1 0 1 2 3 10-9
10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1
Electron injection from bottom TaN/HfLaO Needed VG bias in HfLaO/pentacene OTFT
Current density
(
A/cm2)
Volatage (V) Electron injection from top Au/HfLaO
Fig. 2-2. Leakage current comparison of Au/HfLaO/TaN capacitors with and without NH3 plasma treatment
-3 -2 -1 0 1 2 3 0
3 6 9 12
Capancitance Density
(
fF/μm2)
Volatage(V)
w/o NH3 plasma treatment
with NH3plasma treatment
Fig. 2-3. C-V characteristics of Au/HfLaO/TaN capacitors with and without NH3
plasma treatment.
0.0 -0.5 -1.0 -1.5 -2.0
Gate leakage current induced ID lowering
(b)
Fig. 2-4. ID-VD characteristics of HfLaO gate dielectric OTFTs with (a) and without (b) NH plasma treatment.
-2.0 -1.5 -1.0 -0.5 0.0
with NH3 plasma treatment w/o NH3 plasma treatment
[
ABS(
Drain Current)]1/2 without NH3 plasma treatment.(a)
(b)
Chapter 3
Small Sub-threshold-Swing and Low-Voltage, Flexible Organic Thin Film Transistors which
use HfLaO as the Gate Dielectric
3.1 Introduction
Pentacene-based organic thin-film transistors (OTFTS) have been intensely investigated due to their low cost and light weight, for potential use in applications such as flexible displays and low-cost flexible integrated circuits (IC) [3.1]-[3.3]. The low thermal budget and rapid processing have strong merits of energy saving and environment friendly, which in sharp contrast to the extended 600oC annealing times in conventional solid-phase crystallized (SPC) poly-Si TFTs. Although low thermal budget poly-Si TFTs can also be formed on plastic substrate using excimer laser annealing [3.4]-[3.5], the uniformity is a concern. Alternatively, poly-Si TFTs [3.6] or even single crystal sub-μm MOSFETs [3.7] can be realized on plastic substrate by
gate dielectrics have been applied in OTFTs for low–voltage operation [3.1], [3.3], [3.11]-[3.14]. In chapter 2 we have studied pentacene OTFTs, on SiO2/Si substrates using high-κ HfLaO as the gate dielectric. Although the performance is comparable with SPC poly-Si TFTs, the process temperature of 350oC is still not suitable for flexible electronics. In this work we further decrease the process temperature to 200oC and demonstrate HfLaO/pentacene OTFTs, fabricated on low-cost flexible polyimide (PI) (Kapton HPP-ST, Dupont) substrates. These substrates are much more economical than other PI (Kapton E-type, Dupont) substrates [3.1], [3.11] and those which use polyethylene naphthalate (Teonex Q65 PEN, Dupont) [3.2].
3.2 Experimental Details
All the devices were fabricated on 125 μm thick PI substrates (Kapton HPP-ST, Dupont). Prior to the device fabrication process, the PI substrates were annealed in vacuum environment (3×10-6 torr) at 200oC [3.2]. A 100 nm SiO2 thin film was deposited on the PI substrate by electron beam evaporation to ensure a low internal stress [3.3]. Then a 50 nm TaN gate electrode was deposited by reactive sputtering, through a shadow mask. The surface of the TaN gate was treated in an NH3 plasma to reduce the gate leakage current [3.15]-[3.17]. A 30 nm thick HfLaO gate dielectric
Chemical Co.), 70 nm in thickness, was deposited through the shadow mask. A deposition rate of 0.5 Å/s, at a pressure of 3×10-6 torr was used, with a temperature of the substrate at 70oC. Finally, 50 nm of Au was deposited for the source/drain electrodes. The channel width and channel length were 2000 and 100 μm, respectively.
Metal-insulator-metal (MIM) Au/HfLaO/TaN capacitors, 200×200 μm2 in size, were also fabricated to analyze the leakage current and the dielectric properties. All electrical characteristics were measured using an HP4156C semiconductor parameter analyzer and an HP4284A precision LCR meter in the dark and an air ambient.
3.3 Results and Discussion
We show a schematic diagram and image of the OTFTs in Figs. 1(a) and (b). The C-V and J-V characteristics of the Au/HfLaO/TaN capacitors are detailed in Fig. 2 (a)
and (b) respectively. A low leakage current of 3.5×10-6 A/cm2 at 2.5 V was measured, along with a capacitance density of 450 nF/cm2. This density yields an equivalent-oxide-thickness (EOT) of 7.7 nm and a high-κ value of 15.3.
The output characteristics (ID-VD) of a high-κ HfLaO OTFT are shown in Fig. 3.
on-off-state drive current ratio (Ion/Ioff) was 1.2×104. These values make the device suitable for high-switching-speed, low-power ICs. The SS controls the on/off voltage swing, and should be small. The SS of our device is better than values observed for other flexible pentacene OTFTs [3.1]-[3.3], [3.11], [3.12]. The low SS value arises from the high gate capacitance density and small EOT. The relatively smaller mobility and Ion/Ioff were due to both lower operation voltage and poor surface roughness. A rms surface roughness of 4.3 nm was measured by Atomic Force Microscopy (AFM) on HfLaO and worse than the 2.0 nm value of BZN [3.3], which is originated from the poor 9.0 nm roughness of very low cost PI substrate (Kapton HPP-ST, Dupont).
In Table 3-1 we summarize some important device parameters, including other data of low-voltage flexible pentacene OTFTs using Bi1.5Zn1.0Nb1.5O7 (BZN), polyvinylphenol (PVP), Ta2O5, TiSiO2 and Mn-doped Ba0.6Sr0.4TiO3 (Mn-doped BST) as gate dielectrics, and fabricated on high quality PI (Kapton E-type) and PEN substrates [3.1]-[3.3], [3.11], [3.12]. The low-voltage OTFTs using (2-anthryl)undecoxycarbonyldecylphosphonic acid (π-σ-PA1)/AlOx, octadecylphosphonic acid (OPDA)/AlOx and HfLaO as gate dielectrics, fabricated on Si, glass and SiO2/Si substrate are also list in Table 3-1 for comparison [3.13]-[3.14].
The performance of our HfLaO OTFTs is comparable with other low-voltage flexible pentacene OTFTs for low-power applications, but with the additional merit of a good SS and the use of economical PI substrates.
3.4 Summary
A high-κ HfLaO dielectric was successfully integrated into pentacene OTFTs fabricated on low-cost flexible substrates. The electric characteristics of these HfLaO/pentacene OTFTs showed a low SS of only 0.13 V/decade, a high gate-capacitance-density of 450 nF/cm2, a low VT of -1.25 V, a good μ of 0.13 cm2/Vs and a Ion/Ioff of 1.2×104. This superior performance permits the devices to be operated at 2.5 V, which could be useful in flexible electronics.
.
Table 3-1 Comparison of low voltage OTFTs with various gate dielectrics.
(a)
SiO
2TaN
Au Au
PI
HfLaO
pentacene
-2 -1 0 1 2 4.4
4.5 4.6
Capacitance density (fF/μm2 )
Voltage (V) (a)
-3 -2 -1 0 1 2 3
10-9 10-8 10-7 10-6 10-5 10-4
Current density (A/cm2
)
Voltage (V) (b)
Fig. 3-2. (a) C–V and (b) J–V characteristics of Au/HfLaO/TaN capacitors.
0.0 -0.5 -1.0 -1.5 -2.0 0.0
-0.2 -0.4 -0.6 -0.8 -1.0
VG = - 1.2V VG = - 1.6V VG = - 2.0V VG = - 2.4V
Drain current (μA)
Drain Voltage (V)
Fig. 3-3. ID-VD curve for an HfLaO gate dielectric OTFT.
-2.5 -2.0 -1.5 -1.0 -0.5 0.0
Chapter 4
A Flexible Organic Pentacene Nonvolatile Memory Base on High-κ Dielectric Layers
4.1 Introduction
Organic non-volatile memory devices have potential applications in flexible display drive logic, radio frequency identification tags and smart cards [4.1, 4.2].
These non-volatile memory devices supply an essential function for integrated circuits (ICs) based on organic thin-film transistors (OTFTs). The advantages of using organic memory devices, over their inorganic counterparts, are in their low cost, light weight, simple structure, mechanical flexibility, and low-temperature processing. The OTFT-based non-volatile organic memory devices display high drive current, low off-state leakage current and reasonably-fast switching speeds. The memory properties of these OTFT-based devices arise from the electric field modulation in the gate insulator, through the spontaneous polarization of ferro-electrics [4.2-4.4] or
removing the stored charges. This charge transfer in the gate dielectric is readable by measuring the threshold voltage (VT) of the transistor. This program or erase function can be obtained by having a large electric field across the gate insulator. Previous charge-trapping OTFTs have used a polymer as the insulator[4.5] or a floating gate [4.6] – necessitating a high gate voltage (VG) to write the data. Such high voltages are incompatible with low-power IC designs and challenge existing battery technology. A solution to lowering the program and erase voltages is to use a high-κ dielectric. This has been done by incorporating a high-κ dielectric as the gate insulator in the OTFTs, leading to lower voltage operation [4.7-4.9].
Here we demonstrate a pentacene OTFT non-volatile memory, fabricated on a flexible polyimide (PI) substrate, which shows a program/erase voltage of 12 V, speed of 1 ms/100 ms, initial memory window of 2.4 V and a 0.78 V memory window after 48 hours. This has been achieved by using a high-κ dielectric as charge trapping-, blocking- and tunneling gate insulator layers. This yields to similar program/erase voltages as in charge trapping non-volatile memory devices in Si technology [4.10-4.14]. The magnitude of the VT writing voltage can be decreased to 6 V by applying voltages of different polarity to the gate-electrode and the pentacene. We
4.2 Experimental Details
The OTFT memory devices were fabricated on 125 μm thick PI substrates (Kapton HPP-ST, Dupont). Prior to device fabrication, the substrates were cleaned in de-ionized water and annealed in a vacuum (3×10-6 torr) at 200°C - to improve the dimension stability. A 100 nm SiO2 thin film was deposited on the substrate by electron beam evaporation to create a layer with low internal stress. A 50 nm TaN gate electrode was then deposited by reactive sputtering, through a shadow mask. This was given a NH3 plasma treatment to improve the metal-electrode/high-κ interface [4.9]. The 20 nm HfLaO, 20 nm HfON and 6 nm HfO2 were then deposited by physical vapor deposition and given a 200°C, 30 minute furnace treatment in O2, to improve the gate oxide quality. This was followed by deposition, through a shadow mask, of the pentacene active layer (Aldrich Chemical Co.), 70 nm in thickness. (The deposition conditions were: - a deposition rate of 0.5 Å/s, at a pressure of 3×10-6 torr, with the substrate being held at 70°C.) Finally, 50 nm of gold was deposited, at rate of 1 Å/s, for the source/drain electrodes. The channel width and channel length were
A schematic diagram of the OTFT non-volatile memory is shown in Figure 4-1(a) and a corresponding image in Figure 4-1(b). The structure comprises a TaN gate electrode, HfLaO charge blocking dielectric, HfON charge trapping layer, HfO2
charge tunneling dielectric, pentacene semiconductor layer and gold electrodes for the source-drain contacts. Output and transfer characteristics for such a device are displayed in Figures 4-2(a) and 4-2(b). From the transfer characteristics, the mobility, VT, sub-threshold swing (SS) and on/off current ratio (Ion/Ioff) were 0.1 cm2V-1s-1, -1.4 V, 160 mVdec-1 and 1×104 in the saturation region at a drain voltage (VD) of -3 V. The low VT and good SS are due to the use of a high-κ material as gate the dielectric [4.7-4.9].
The energy band diagram our OTFT memory device [4.15, 4.16] is shown in Figure 4-3. The HfLaO gate dielectric has a high dielectric constant, large bandgap and high electron injection barrier with respect to the TaN gate electrode during the erase process [4.9]. The small band-gap HfON, [4.10-4.12] with its deep trapping energy, was chosen as the charge-trapping layer to achieve good charge trapping characteristics. The thin HfO2 dielectric serves as a charge-tunneling layer. The gold electrode forms an ohmic-like contact for the injection of holes. When a proper gate
A Metal-Insulator-Semiconductor (MIS) structure is useful for charge injection studies [4.17]. Figure 4-4 shows the quasi-static capacitance-voltage (C-V) characteristics, as a function of VG, for a TaN-HfLaO-HfON-HfO2-pentacene-Au MIS structure. The maximum capacitance density was found to be 2.7 fFμm-2. The decrease of the capacitance value at positive VG , and increase for negative VG , reflects the depletion and accumulation of holes stored in the MIS capacitor, respectively. No bipolar behavior[4.17] was observed in our OTFT devices. These results suggest that the pentacene is a p-type semiconductor and that no electron accumulation occurs at the dielectric/pentacene interface. It is important to notice the large C-V hysteresis, with the shifts being as large as 4 V. Since the area under the C-V curves reflects the trapped charges, the large hysteresis indicates good charge
storage capacity, potentially useful for memory devices. The charges are mainly stored in the HfON layer of our device - this conclusion follows from the observation that, for a similar MIS structure without an HfON layer, no significant C-V hysteresis was found for the same biasing conditions.
application of a reverse Vg of 12 V for 100 ms. Thus the VT value can be shifted, reversibly, by applying an appropriate gate bias. We investigated the program and erase characteristics further, and observed different VT shifts as a function of VG, for program or erase functions (Figure 4-6(a) and 4-6(b)). A 2.6 V VT shift was shown after a -12 V program voltage pulse applied for 1 ms. The could be erased, with a large 2.5 V VT shift, after a +12 V voltage pulse for 100 ms. Since a negative voltage was applied across the HfLaO/HfON/HfO2 gate dielectric stack during the programming process, hole accumulation occurred at the dielectric/pentacene interface. The increase of the VT shift with the increase in negative VG indicates that the accumulated holes were injected over the HfO2 gate dielectric and stored in the lower energy HfON dielectric. The erase was performed by applying a positive VG to the TaN gate electrode, where the applied electric field over the HfLaO/HfON/HfO2
gate dielectric stack causes hole depletion in the pentacene. The stored holes in the HfON may tunnel out, over the HfO2 gate dielectric, into the pentacene; alternatively, the minority carriers (electrons), generated in the depletion region of the pentacene, can also tunnel through the HfO2 and into the HfON – all of which gives rise to the erase function. Similar mechanisms have also been suggested by us to explain the
MIS capacitor is shown in Figure 4-5 (b)
For non-volatile memory applications good retention characteristics are essential.
To investigate the retention we applied a VG of -12 V at 1 ms to program the device, and 12 V at 100 ms for the erase function. In Figures 4-7(a) and 4-7(b) we show the retention data. The VT was extracted in the linear region of the ID-VG characteristics at VD = -1V. The initial memory window was 2.4 V, which decreased to 0.78 V after 48
hours. The significant charge loss of 50% at 103 s is possibly related to the increase in the leakage current due to the surface roughness of the PI substrates, as well as defects in the low-temperature-formed HfO2. Atomic force microscopy showed that the rms surface-roughness was approximately 5 nm. Improvements in the leakage current can be expected from smoother substrates and replacing the HfO2 with a higher-quality gate dielectric. Finally in figure 8 we display the endurance characteristics of the memory device. A large memory window of 2.3 V, with a degradation of less than 5 %, was obtained after 102 cycles.
4.4 Summary
memory window of 2.4 V.
.
(a)
(b)
Fig. 4-1. (a) Schematic cross-sectional diagram and (b) Image of the flexible pentacene OTFT memory devices.
0.0 -0.5 -1.0 -1.5 -2.0
Fig. 4-2. (a) Output and (b) transfer characteristics of pentacene OTFT memory devices.
Fig. 4-3. Band diagram of the TaN-HfLaO-HfON-HfO2-pentacene-Au OTFTs.
-6 -4 -2 0 2 4 1
2
3 +8V : -8V +10V : -10V
+12V : -12V -8V : +8V -10V : +10V -12V : +12V
Capacitance Density (fFμm-2 )
Bias Voltage (V)
Fig. 4-4. Capacitance-voltage hysteresis for the MIS structure, showing 3-4V hysteresis. The curves are for different sets of program and erase voltages, as indicated.
0 -1 -2 -3 -4
Fig. 4-5. (a) Drain current-Gate Voltage (ID-VG) hysteresis curves for a pentacene
10-3 10-2 10-1 100
Fig. 4-6. (a) Program characteristics and (b) erase characteristics of OTFT memory devices for different voltages and times. The erase characteristics were initially programmed at Vg = -12V for 1ms. The Vth was extracted from the I -V curve at V = -1 V in the linear region.
100 101 102 103 104 105 106
Normalized V T (V) shift
Retention Time (sec) (b)
Fig. 4-7. (a) Retention characteristics in terms of the threshold voltage, Vth, for the
10
010
110
2-1
-2 -3 -4 -5
Program : -12V 1ms Erase: 12V 100 ms
Number of Cycles
Thr eshold Voltage ( V )
Fig. 4-8. Endurance characteristics of a pentacene OTFT memory device.
Chapter 5
Interfacial SiON Thickness Dependence on Device Performance of High-κ
MoN/HfAlO/SiON p-MOSFETs
5.1 Introduction
Although the high-κ gate oxide and metal gate have been successfully implemented into 45 nm node CMOSFETs and below, the undesired high threshold voltage (VT) is still a difficult challenge [5.1]-[5.14]. This challenge is even worse at small equivalent-oxide thickness (EOT) by the flat-band voltage (Vfb) roll-off effect [5.4]-[5.6]. The unwanted high Vt issue is particularly harder for p-MOSFET than n-MOSFET due to very limited elements of metal-gate in the Periodic Table that have
the needed high effective work-function (φm-eff) >5.2 eV [5.1].One effective method to reduce the VT is to use the unique negative or positive Vfb property of high-κ La2O3
[5.8]-[5.10] or Al2O3 [5.11]-[5.14] to mix or cape with the Hafnium (Hf) based
In this chapter we have investigated the devices performance and mechanisms of HfAlO capping on different thickness SiON. The F+ implantation is also performed to study the Vfb shift on MoN/HfAlO/SiON p-MOS capacitors. Under the optimized condition, small EOT, low VT, good sub-threshold swing (SS) and high mobility are simultaneously reached in the gate-first MoN/HfAlO/SiON p-MOSFETs.
5.2 Experimental Details
The gate-first MoN/HfAlO/SiON p-MOSFET was fabricated on 12-in N-type Si wafer. After standard cleaning, different 0.83, 1.5 or 2.1 nm thick SiON (8% N) was grown by using in-situ steam-generated (ISSG) oxide. Next, a 1 nm HfAlO [5.1]
dielectric was deposited by physical vapor deposition (PVD), followed by a 500oC O2
post-deposition anneal. The composition ratio of Hf and Al in HfAlO is 1:1. Then 50-nm MoN and 200-nm TaN were deposited ex-situ by PVD. The nitrogen content in TaN and MoN is 50%. After gate definition, self-aligned BF2+ was implanted at 35 KeV and 5×1015 cm-2 for p+source-drain regions and activated at 1000oC by rapid thermal annealing (RTA) for 1 sec. For comparison, MoN/SiON p-MOSFETs were also formed. We also studied the effect of F+ implantation on p-MOS devices, performed before gate oxide stack at 10 KeV and 1x1014 cm-2 dosage. The formed
radiation and detected at a take-off angle of 60o. The fabricated devices were characterized by capacitance-voltage (C-V) and gate current density-voltage (J-V) measurements using the HP4284A precision LCR meter and HP4156C semiconductor parameter analyzer, respectively. The Vfb and EOT values were extracted from measured C-V curves using a CVC simulator [5.20] that accounts for the quantum-mechanical effects. The mobility of MOSFET was extracted directly from the measured Id-Vg characteristics.
5.3 Results and Discussion
A. Positive Vfb shift of MoN/HfAlO/SiON gate capacitors
Figures 5-1(a) and 5-1(b) show the C-V and J-V characteristics of MoN/HfAlO/SiON gate capacitors with various SiON thicknesses and control MoN/2.1nm SiON. The C-V measurements were performed at a frequency of 100 kHz.
The positive Vfb value of as-deposited MoN/HfAlO/SiON capacitor is nearly identical to the control MoN/2.1nm SiON device, which is consistent with the previous report [5.21]. In sharp contrast, large positive V shift of more than 500 mV and a higher
after 1000oC RTA. The capacitor with the thinnest 0.83 nm SiON shows the largest Vfb that may be due to Al diffusion through SiON and react with Si channel layer. The EOT is improved with decreasing SiON thickness from 2.1 to 1.5 nm, but degrades at the thinnest 0.83 nm. The leakage current is higher at thinner EOT, where the MoN/HfAlO/1.5-nm-SiON p-MOS capacitor has the highest leakage current of 5×10-3 A/cm2 at 1 V. The achieved large Vfb and low gate leakage current were due to the using high-work function MoN gate and HfAlO. In addition, the high temperature RTA is also crucial to reach further positive Vfb shift of HfAlO/SiON gate dielectric.
At optimized 1.5 nm interfacial SiON, a small EOT of 0.85 nm was obtained using quantum-mechanical C-V calculation.
B. The mechanism
To investigate the needed positive Vfb shift after 1000oC RTA, we have performed the XPS measurements on HfAlO/SiON gate dielectric. Figure 5-3 exhibits the Si 2p photoemission spectra of MoN/HfAlO/SiON gate stack, where the top MoN was etched back for XPS measurements by using reactive ion etching (RIE) with BCl3/Cl2
plasma. The XPS spectrum of MoN/SiON was also added for comparison. There are two major peaks in the XPS data after Gaussian function de-convolution. The peak at
The Si-O bonding energy of as-deposited MoN/HfAlO/SiON is 102.6 eV that lowers to 102.1 eV after 1000oC RTA. This 102.1 eV value is very close to the reported data [5.23]-[5.24] that is attributed to AlSiO silicate formation. This is originated from the Al2O3 reacting with Si substrate [5.23] or Si3N4 dielectric [5.24]. During the silicate formation with a lower 0.5 eV Si-O binding energy, the charged oxygen vacancies in Al2O3 may also be formed after 1000oC RTA:
Al2O3 + SiO1.92N0.08 → Al2O3-x + SiO1.92+xN0.08 (1) The formation is thermo-dynamically favorable due to the lower bond enthalpy of Al2O3 (511 kJ/mol) and SiN (470 kJ/mol) in SiON than that of SiO2 (800 kJ/mol) [5.1]. Similar formation of charged oxygen vacancies was also reported in HfLaO/Si MOS capacitor after high temperature RTA [5.6] and responsible to the Vfb roll-off at smaller EOT [5.5]-[5.6], [5.25]. This charged oxygen vacancies can lead to the unique positive Vfb of Al2O3 from theoretical calculation [5.26], which explains well the measured >0.5 V positive Vfb shift of HfAlO/SiON gate stack after 1000oC RTA.
We have used the F+ implantation to further study the effect of Vfb shift. Figure
these without (Fig. 5-1(a)).
The SIMS depth profiles were measured to study the degradation in MoN/HfAlO/SiON device. Figures 5-5(a) and 5-5(b) show the SIMS profiles for MoN/HfAlO/1.5-nm-SiON gate stack without and with F+ implantation, respectively.
After 1000oC RTA, the Al and Mo are diffused closer to SiON/Si that explains the achieved higher capacitance density or smaller EOT than as-deposited case. The poor
After 1000oC RTA, the Al and Mo are diffused closer to SiON/Si that explains the achieved higher capacitance density or smaller EOT than as-deposited case. The poor