Fig. 3.3 shows the junction characteristics of Ge p-MOSFET and Ge n-MOSFET. For p+/n junction, the current density at forward bias and reverse bias are 6.584x101 A/cm2 at 1 V and 3.93x10-3 A/cm2 at -1 V, respectively while the on/off ratio is about 1.66x104. For n+/p junction, the current density at forward bias and reverse bias are 5.06x101 A/cm2 at -1 V and 3.29x10-4 A/cm2 at 1 V, respectively while the on/off ratio is about 1.51x105. The higher current density at reverse bias of germanium device compare to silicon devices is due to smaller bandgap of germanium. To extract junction series resistance, we know that:
nkT series resistance is about 59.4 Ω. For n+/p junction, the series resistance is about 47.7 Ω.
To extract ideality factor, we know that:
A plot of ln[I/(1-exp(-qV/kT))] versus V can determine ideality factor (n) from slope. The ideality factor of p+/n junction is 1.262 and that of n+/p junction is 1.512.
Fig. 3.4 shows ID-VG and IS-VG characteristics of Ge p-MOSFET and Ge n-MOSFET.
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For Ge p-MOSFET, the on/off ratio is about 5.62x104 for IS and 2.92x103 for ID. For Ge n-MOSFET, the on/off ratio is about 1.85x105 for IS and 1.73x104 for ID. The reason why on/off ratio of ID is always lower than that of IS is due to small bandgap energy of germanium causes junction leakage. Our MOSFETs also show serious gated-induce drain leakage current (GIDL) due to large gate to source/drain overlapping area. The subthreshold swing of p-MOSFET is about 119.1 mV/dec, while that of n-MOSFET is about 112.5 mV/dec.
Fig. 3.5 shows ID-VD characteristics of Ge p-MOSFET and Ge n-MOSFET. At the same overdrive voltage, we can observe that p-MOSFET reveals much larger driving current than n-MOSFET, due to n-MOSFET reveals much larger source/drain resistance than p-MOSFET.
As we know, n-type dopant like phosphorous is much easier lost during subsequent annealing by out-diffusion [3.9-3.10]. During high-dielectric annealing, there’s only about 3~4 nm ZrO2 film on source/drain region, such a thin film could not restrict phosphorous out-diffuse.
Also, activation of n-type dopant in germanium is a problem which the active level of n-type dopant in germanium is much lower than p-type dopant in germanium [3.11-3.12].
Fig. 3.6 shows the plot of measured resistance versus channel length on mask for Ge p-MOSFET and Ge n-MOSFET. We extract source/drain series resistance (RSD) by Terada and Muta method [3.13].
= = + = ∆
( )+ , (3.3) where Rm is measured resistance, Rch is channel resistance; RSD is source/drain series resistance. Eq. (3.3) gives Rm=RSD while L=ΔL. A plot of Rm versus L for device with different L and varying gate voltage shows lines intersecting at one point giving RSD. If the lines fail to intersect at same point, we can further write Eq. (3.3) as
= + = ( − ∆ ) + = + . (3.4) The parameters A and B are determined from slope and intercept of Rm versus L plots for different gate voltages. RSD can be obtained from the intercept of a B versus A plot. By our
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measurements, the source/drain series resistance is about 365.2 for p-MOSFET and 1965.4
for n-MOSFET. Also ΔL=0.75 m for p-MOSFET and ΔL=0.15 m for n-MOSFET.
To extract effective mobility
= ,
where the drain conductance gd is defined as
= | = ,
and Qinv can be measured by split-CV method
= ∫ .
The mobile channel charge density is determined from the gate to channel capacitance, CGC. Then CGC is measured using the connection of Fig. 3.7, the capacitance meter is connected between the gate and the source/drain and the substrate is grounded. For VGS < VT the channel region is accumulated and the overlap capacitances 2Cov are measured (Fig. 3.8 (a)). For VGS
> VT,the surface is inverted and 2Cov+Cch are measured (Fig. 3.8 (b)).
Fig. 3.9 shows hole mobility as a function of inversion charge density for Ge p-MOSFET.
The peak hole mobility of p-MOSFET is about 259 cm2/V-s. Here we do not show the electron mobility of Ge n-MOSFET because of the huge source/drain series drain resistance.
The voltage drop across the source/drain resistance IDRSD causes a reduction in drain current.
Hence, the measured mobility by split C-V method appears to be lower than the real value.
3.4 Conclusion
In Chapter 3, we investigate fabrication and electric characteristics of Ge MOSFETs. For Ge p-MOSFET (the channel width is 100 m, the channel length is 5 m), the on /off ratio of p+/n junction, ID-VG and IS-VG are about 1.66x104, 2.92x103, and 5.62x104, respectively, while
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the substhreshold swing is about 119.1 mV/dec. For Ge n-MOSFET (the channel width is 100
m, the channel length is 5 m), the on /off ratio of n+/p junction, ID-VG and IS-VG are about 1.51x105, 1.73x104, and 1.86x105, respectively, while the substhreshold swing is about 112.5 mV/dec.
From ID-VD curve we can see that Ge n-MOSFET reveals poor driving current than Ge p-MOSFET at the same overdrive voltage. As we mentioned, n-type dopant in germanium diffuses much easier than p-type dopant in germanium. So n-type dopant will be much easier lost during subsequent thermal process because such a thin high- film on source/drain region cannot restrict the dopant out diffuse. Also, the activation level of n-type dopant in germanium is lower than p-type dopant in germanium. Due to these problems, Ge n-MOSFETs always exhibit poor performance than Ge p-MOSFETs.
To solve these problems, changing fabrication scheme may be a solution. In next chapter, Ge MOSFETs using gate first process will be introduced.
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Fig. 3.1 Process flow of Ge MOSFETs.
Fig. 3.2 Device structure of Ge MOSFETs.
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Fig. 3.5 ID-VD characteristic of Ge MOSFETs; (a) Ge p-MOSFET, and (b) Ge n-MOSFET.
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Fig. 3.6 Rm versus L as a function of gate voltage to extract series resistance; (a) Ge p-MOSFET, and (b) Ge n-MOSFET.
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Fig. 3.7 Configuration to measure CGC.
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(a)
(b)
Fig. 3.8 Schematic for gate to channel capacitance measurements for (a) VGS < VT, and (b) VGS > VT.
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0.5 1.0 1.5 2.0 2.5 3.0
0 50 100 150 200 250 300
H o le M o b il it y ( c m
2/V -s )
N
inv(10
12cm
-2)
Fig. 3.9 Hole mobility as a function of inversion charge density for Ge p-MOSFET.
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Chapter 4
Germanium MOSFETs with ZrO 2 /Ge Gate Stack Using Gate First Process
4.1 Introduction
Recently, Ge p-MOSFET with high hole mobility has been reported [4.1-4.2]. But the Ge n-MOSFET is still not good enough due to the high interface density of state (Dit) [4.3] and the poor n+/p junctions. Though, attention has been paid more to GeO2/Ge gate stack due to its superior interface properties and has been reported with low Dit recently [4.4-4.7], the n+/p junctions still suffer from the low activation and fast diffusion rate of n-type dopants in germanium.
A SiO2 capping layer has been utilized to prevent dopant out-diffuse [4.8]. In Chapter 3, we have used this method to prevent dopant out-diffuse. However, SiO2 capping layer will be removed and the dopant will out-diffuse during subsequent process. In order to conquer this drawback, change the fabrication scheme may be a solution. By gate first process, the source/drain will be defined after gate stack formation. Due to this change, more effective dopant activation caused by the last high temperature step in the gate first process can prevent dopant out-diffuse.
In this chapter, both germanium n-MOSFET and p-MOSFET are fabricated using gate first process. Junction and device characteristics, series resistance, subthreshold swing and mobility are discussed.
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