Table 5.1 shows the comparison of Ge p-MOSFETs using gate last process and gate first process. Table 5.1 (a) shows junction characteristics of Ge p-MOSFETs. We can see that on current of p+/n junction using gate first scheme is about 5 times higher than that of p+/n junction using gate last scheme. Because of dopant activation caused by the last high temperature step in the gate first process, less dopant out-diffuse results in lower junction series resistance. The off current of p+/n junction using gate first scheme is almost the same compared to that of p+/n junction using gate last scheme. Therefore, on/off ratio of junction using gate first scheme is higher than that of junction using gate last junction. From Table 5.1 (b) & (c), because of the source/drain resistance of gate first p-MOSFET is 3 times smaller than gate last p-MOSFET (the source/drain resistance has been normalized), we see that driving current for gate first p-MOSFET is a little higher than gate last p-MOSFET. Fig. 5.1 shows the channel surface of gate last MOSFET and gate first MOSFET. We can see that the channel surface of gate last MOSFET is much rough than gate first MOSFET, so the mobility degrades fast at high electric field for gate last MOSFET compared to gate first MOSFET.
Table 5.2 shows the comparison of Ge n-MOSFETs using gate last process and gate first process. Table 5.2 (a) shows junction characteristics of Ge n-MOSFETs. We can see that on current of n+/p junction using gate first scheme is about 3.2 times higher than that of n+/p junction using gate last scheme. Because of dopant activation caused by the last high
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temperature step in the gate first process, less dopant out-diffuse results in lower junction series resistance. The off current of n+/p junction using gate first scheme is about 30 times higher than that of n+/p junction using gate last scheme. The reason is that the thermal budget is not enough to activate phosphorous during dopant activation for gate first process. From Table 5.2 (b) & (c), the source/drain resistance of gate first n-MOSFET is 2.1 times smaller than gate last n-MOSFET (the source/drain resistance has been normalized), however, we see that driving current for gate first n-MOSFET is a little lower than gate last n-MOSFET. The reason may be the effective channel length of gate first n-MOSFET is longer than gate last n-MOSFET.
5.2 Conclusion
In this thesis, ZrO2 film has been obtained by PE-ALD growth with an interfacial GeOx layer for Ge MOS capacitors. The dependence of ALD ZrO2 growth temperature and post deposition annealing (PDA) temperature were investigated. Dit distribution was also measured by conductance method. The Ge 3d XPS spectra with different treatment such as as-deposited, annealing at 500°C and annealing at 600°C are shown. With increasing annealing temperature, germanium suboxide will also increase. Therefore, we think more germanium suboxide can improve ZrO2/Ge interface. We chose PE-ALD ZrO2 at 250°C and then annealing at 600°C for one minute in N2 ambient to be the optimized condition to fabricate Ge-MOSFETs.
We have successfully fabricated Ge MOSFETs using gate last process. For Ge p-MOSFET, the on/off ratio of p+/n junction is 1.66x104, on/off ratio of ID is 2.92x103, the subthreshold swing is 119.1 mV/dec, the source/drain resistance is about 365.2 and the peak hole mobility is 259.6 cm2/V-s. For Ge n-MOSFET, the on/off ratio of n+/p junction is 1.51x105, the on/off ratio of ID is 1.73x104, the subthreshold swing is 112.5 mV/dec and the
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source/drain resistance is about 1965.4 .
Ge MOSFETs using gate first process were also successfully fabricated. For Ge p-MOSFET, the on/off ratio of p+/n junction is 8.61x104, the on/off ratio of ID is 5.32x103 the subthreshold swing is 125.1 mV/dec, the source/drain resistance is about 50.3 and the peak hole mobility is 227.4 cm2/V-s. For Ge n-MOSFET, the on/off ratio of n+/p junction is 1.66x104, the on/off ratio of ID is 3.02x103, the subthreshold swing is 130.5 mV/dec and the source/drain resistance is about 460.4 .
Finally, the comparison of gate last MOSFETs and gate first MOSFETs were discussed.
We conclude that using gate first scheme can reduce source/drain resistance effectively.
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Table 5.1 Comparison of Ge p-MOSFETs between the gate last and the gate first processes.
Ge p-MOSFETs :
Gate last 1.32x101 4.52x10-3 2.92x103
Gate first 2.18x101 4.18x10-3 5.32x103
(b)
MOSFET S.S(mV/dec) RSD(⋅mm) L(m)
Gate last 119.1 36.52 0.75
Gate first 125.8 10.06 0.52
(c)
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(a)
(b)
Fig. 5.1 TEM image of Ge p-MOSFET; (a) gate last MOSFET, and (b) gate first MOSFET.
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Table 5.2 Comparison of Ge n-MOSFETs between the gate last and the gate first processes.
Ge n-MOSFETs :
56
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