在鍺通道金氧半場效電晶體上製造閘極介電層二氧化鋯/鍺堆疊結構之研究

國

立

交

通

大

學

電信工程研究所

碩

士

論

文

在鍺通道金氧半場效電晶體上製造閘極介電層二氧

化鋯/鍺堆疊結構之研究

Investigation of ZrO

2

/Ge Gate Stack Fabricated on

Ge-Channel MOSFETs

研 究 生：李品輝

指導教授：簡昭欣 教授

李義明

教授

在鍺通道金氧半場效電晶體上製造閘極介電層二氧

化鋯/鍺堆疊結構之研究

Investigation of ZrO

2

/Ge Gate Stack Fabricated on

Ge-Channel MOSFETs

研 究 生：李品輝 Student：Pin-Hui Li

指導教授：簡昭欣 教授 Advisor：Dr. Chao-Hsin Chien

李義明 教授 Advisor：Dr. Yiming Li

國 立 交 通 大 學

電 信 工 程 研 究 所

碩 士 論 文

A Thesis

Submitted to College of Electrical and Computer Engineering National Chiao Tung University

for the Degree of Master in

Communications Engineering November 2013

Hsinchu, Taiwan, Republic of China

I

在鍺通道金氧半場效電晶體上製造閘極介電層二氧

化鋯/鍺堆疊結構之研究

學生：李品輝

指導教授：簡昭欣 教授

李義明 教授

國立交通大學電信工程研究所碩士班

摘要

在這篇論文中，首先我們製造了以二氧化鋯為閘極介電層的鍺金氧半電容，再來我 們使用了電性和物性分析來研究利用不同溫度的原子層化學沉積以及不同溫度的沉積 後退火對鍺基板和二氧化鋯之間介面的影響。我們討論並使用電導方法(conductance method)來萃取介面缺陷電荷密度，也利用准靜態電容量測方法(quasi-static C-V)和貝格 朗積分(Berglund integral)萃取出表面電位並探討能帶彎曲的有效程度。我們選擇 250 度 的原子層化學沉積以及在 600 度的氮氣環境下進行一分鐘的沉積後退火做為我們製作元 件的條件。

其次，我們成功的利用閘極後形成的製程(gate last process)做出了鍺金氧半場效電晶

體。我們的 p+ /n 接面以及 p 型金氧半場效電晶體的開關比分別為 1.66x104和 2.92x103_， 次臨界擺幅為 119 mV/dec。我們的 n+ /p 接面以及 n 型金氧半場效電晶體的開關比分別為 1.51x105和 1.73x104_{，次臨界擺幅為 112.5 mV/dec。但是在介電層退火的過程中，我們} 的摻雜會向外擴散而造成有很大的源極/汲極串連阻抗。為了改善這個缺點，我們改變了 製程的先後順序。

再來，我們利用閘極先形成的製程(gate first process)做出了鍺金氧半場效電晶體。們 的 p+

II 幅為 125.8 mV/dec。我們的 n+ /p 接面以及 n 型金氧半場效電晶體的開關比分別為 1.66x104 和 3.02x103_{，次臨界擺幅為 130.5 mV/dec。} 最後，我們比較閘極後形成的鍺金氧半場效電晶體和閘極先形成的鍺金氧半場效電 晶體。由於摻雜活化是閘極先形成的製程中最後一個高溫的步驟，所以源極/汲極的串連 阻抗被大大的降低。

III

Investigation of ZrO

2

/Ge Gate Stack Fabricated on

Ge-Channel MOSFETs

Student：Pin-Hui Li Advisor：Dr. Chao-Hsin Chien

Dr. Yiming Li

Institute of Communications Engineering

Electrical and Computer Engineering College

National Chiao Tung University

ABSTRACT

In this thesis, firstly ZrO2/Ge MOS capacitors are fabricated. ZrO2 was deposited by

atomic layer deposition (ALD) with different conditions such as deposition temperatures and

post deposition annealing (PDA) temperatures. We electrically and physically analyze the

ZrO2/Ge MOS capacitors. Conductance method is discussed in detail and utilized to extract

the density of interface state of the ZrO2/Ge MOS capacitors. Also, by using quasi-static C-V

curve and Berglund integral, we can estimate the band bending efficiency from the extracted

surface potential. We choose ALD at 250C and PDA at 600C in N2 ambient for one minute

to be an optimized condition to fabricate the Ge MOSFETs.

Secondly, we successfully fabricate the Ge MOSFETs using a gate last scheme. The

on/off ratio of our p+/n junction and reaches 1.66x104 and 2.92x103, respectively and the subthreshold swing of p-MOSFET is 119 mV/dec. The on/off ratio of our n+/p junction and n-MOSFET reaches 1.51x105 and 1.73x104, respectively and the subthreshold swing of n-MOSFET is 112.5 mV/dec. Even so, we find, however, there is a large source/drain series

IV

resistance in our MOSFET due to the dopant out-diffusion during the high- dielectric

annealing. In order to improve this drawback, we further change the fabrication from the gate

last scheme to the gate first scheme.

Thirdly, we fabricate Ge MOSFETs using a gate first scheme. The on/off ratio of our p+/n junction and p-MOSFET reaches 8.61x104 and 5.32x103, respectively and the corresponding subthreshold swing is 125.8 mV/dec. The on/off ratio of our n+/p junction and n-MOSFET is 1.66x104 and 3.02x103, respectively while the subthreshold swing is 130.5 mV/dec.

Finally, comparison between the studied gate last and gate first MOSFETs is discussed in

detail. The engineering findings of this study indicates that source/drain series resistance can be largely reduced due to more effective dopant activation caused by the last high temperature

V

致謝

在這兩年多的碩士生涯中，首先我要感謝我的指導老師 簡昭欣教授。老師不僅在 實驗上給予很大的建議，教我正確的研究態度及方法，也教了我不少待人處事的道理， 讓我受益良多並更加成長。也要感謝另一個指導老師 李義明教授。感謝李老師能讓我 做我真正想做的研究，而且在研究上也會給我建議及鼓勵。在這裡要對兩位老師致上最 誠摯的敬意與謝意。 政庭學長，不管是實驗的設計、數據的分析及整理、半物、製程上或量測的問題， 每次跟你討論都獲益良多，你也都會跟我一一解說，沒有你的幫助，實驗成果是不可能 這麼豐富的。能跟你一起做實驗、一起幫 Lamigo 加油真的很開心，祝福你明年能夠順 利畢業。哲偉學長，超常拿著蠢問題追著你，不管你怎麼忙也都不厭其煩地替我解惑， 也常關心我的進度，希望以後還能有機會一起打球。信淵學長，你的 coding 神技真是令 人歎為觀止，在 Dit的萃取上謝謝你的幫忙跟指導，希望你元件能趕快做出來。謝謝宏 基學長，因為有你，奈中的機台能夠順利破關，也祝你博士學位能早日破關。謝謝哲鎮、 酷奇、小林學長，沒有你們的帶領，實驗沒辦法這麼快的上手，許多實驗上的小撇步， 都讓我在實驗上順利不少。再來要感謝實驗室同學的陪伴，主元、邦聖、純敏、周洋平 時互相討論研究問題，一起打嘴砲，讓我兩年的研究生生活充滿樂趣。崇浚、弘彬、晨 揚、晉宇、俊翰，謝謝你們的幫忙，讓我在實驗的負擔上減輕不小，也祝福你們到時候 都能準時畢業。 感謝我的朋友們，一起分攤平時作研究的壓力。感謝系壘的大家，在繁忙的研究中 一起為比賽付出是很熱血的一件事。最重要的是感謝我的家人，有你們的關心支持與栽 培照顧，讓我能無後顧之憂地專心做研究。感謝你們提供一個溫暖的家，在我失意時能 有個避風港。沒有你們的付出，不會有今天的我。 最後，感謝所有幫助過我大大小小的人，祝福你們都能心想事成。

VI

Contents

摘要 ... I ABSTRACT ... III 致謝 ...V Contents ...VI Table Captions ... VIII Figure Captions ... IX

Chapter 1 ... 1

1.1 General Background ... 1

1.2 Motivation ... 2

1.3 Scope and Organization of the Thesis ... 3

Chapter 2 ... 5

2.1 Introduction ... 5

2.2 Fabrication of PE-ALD ZrO2/Ge MOS Capacitors ... 6

2.3 Electrical and Physical Characteristics of Ge MOS Capacitors with Various PDA Conditions ... 7

2.4 Determine the Dit at ZrO2/Ge Interface ... 8

2.4.1 Conductance Method ... 8

2.4.2 Dit Measurement of ZrO2/Ge Interface ... 10

2.5 Conclusion ... 12

Chapter 3 ... 24

3.1 Introduction ... 24

VII

3.3 Electrical Characteristic of Ge MOSFETs ... 26

3.4 Conclusion ... 28

Chapter 4 ... 38

4.1 Introduction ... 38

4.2 Fabrication of Gate First Ge-MOSFETs ... 39

4.3 Electrical Characteristic of Ge MOSFETs ... 40

4.4 Conclusion ... 41

Chapter 5 ... 50

5.1 Comparison between Gate-last and Gate-first MOSFETs ... 50

5.2 Conclusion ... 51

Reference ... 56

VIII

Table Captions

Table 1.1 Scaling parameter in CMOS circuit design. ... 4

Table 1.2 Material properties of bulk Ge, Si, GaAs, and InAs at 300K are compared. ... 4

Table 2.1 Comparison of relevant properties for high- candidate. ... 13

Table 2.2 C-V characteristic with different PDA temperature; (a) ALD at 200°C, (b) ALD at

250°C. ... 18

Table 5.1 Comparison of Ge p-MOSFETs between the gate last and the gate first processes. 53

IX

Figure Captions

Fig. 2.1 Process flow of (100)-oriented Ge MOSCAPs with different ALD temperature and

different PDA conditions. ... 13

Fig. 2.2 MOSCAP of ZrO2/Ge gate stack structure. ... 14

Fig. 2.3 TEM image of PE-ALD ZrO2/Ge gate stack . ... 14

Fig. 2.4 Capacitance of an MOS capacitor for various bias conditions. ... 15

Fig. 2.5 Multi-frequency C-V of Ge MOS capacitor with different PDA condition using ALD 200°C; (a) PDA at 500°C for 1 min in N2, and (b) PDA at 600°C for 1 min in N2. .. 16

Fig. 2.6 Multi-frequency C-V of Ge MOS capacitor with different PDA condition using ALD 250°C; (a) PDA at 500°C for 1 min in N2, and (b) PDA at 600°C for 1 min in N2. .. 17

Fig. 2.7 Deconvolution of the XPS spectra of ZrO2/Ge structure with different PDA conditions. ... 19

Fig. 2.8 GIXRD spectrum for as-deposited ZrO2, ZrO2 with PDA at 500°C and 600°C. ... 19

Fig. 2.9 Equivalent circuit for conductance measurement; (a) MOS capacitor with interface trap time constant τit = RitCit , (b) simplified circuit of (a), and (c) measured circuit.20 Fig. 2.10 Trap response frequency for germanium under different temperature.... 20

Fig. 2.11 / versus frequency of Ge MOS capacitor with different PDA conditions; (a) PDA at 500°C, and (b) PDA at 600°C. ... 21

Fig. 2.12 Dit measurement of Ge MOS capacitors with different PDA conditions. ... 22

Fig. 2.13 A band diagram showing the weak inversion response. ... 22

Fig. 2.14 relation between gate voltage and surface potential by integration of quasi-static CV; (a) PDA at 500°C, and (b) PDA at 600°C... 23

Fig. 3.1 Process flow of Ge MOSFETs. ... 30

X

Fig. 3.3 I–V characteristics of p+/n and n+/p junctions; (a) p+/n junction, and (b) n+/p junction.

... 31

Fig. 3.4 ID-VG and IS-VG characteristics of Ge MOSFETs; (a) Ge p-MOSFET, and (b) Ge n-MOSFET. ... 32

Fig. 3.5 ID-VD characteristic of Ge MOSFETs; (a) Ge p-MOSFET, and (b) Ge n-MOSFET. . 33

Fig. 3.6 Rm versus L as a function of gate voltage to extract series resistance; (a) Ge p-MOSFET, and (b) Ge n-MOSFET. ... 34

Fig. 3.7 Configuration to measure CGC. ... 35

Fig. 3.8 Schematic for gate to channel capacitance measurements for (a) VGS < VT, and (b) VGS > VT. ... 36

Fig. 3.9 Hole mobility as a function of inversion charge density for Ge p-MOSFET. ... 37

Fig. 4.1 Process flow of Ge MOSFETs. ... 43

Fig. 4.2 Device structure of Ge MOSFETs. ... 44

Fig. 4.3 I–V characteristics of p+/n and n+/p junctions; (a) p+/n junction, and (b) n+/p junction. ... 45

Fig. 4.4 ID-VG and IS-VG characteristic of Ge MOSFETs; (a) Ge p-MOSFET, and (b) Ge n-MOSFET. ... 46

Fig. 4.5 ID-VD characteristics of Ge MOSFETs; (a) Ge p-MOSFET, and (b) Ge n-MOSFET. 47 Fig. 4.6 Rm versus L as a function of gate voltage to extract series resistance; (a) Ge p-MOSFET, and (b) Ge n-MOSFET. ... 48

Fig. 4.7 Hole mobility as a function of inversion charge density for Ge p-MOSFET. ... 49

1

Chapter 1

Introduction

1.1 General Background

In 1947, John Bardeen and Walter Brattain observed that when two gold point contacts

were applied to germanium, the output signal’s power is greater than the input ones. This was the first transistor which was fabricated. Then germanium was the predominant material for

solid-state device through the 1950s and 1960s. The first integrated circuit using germanium

was fabricated by Jack Kilby at Texas Instrument in 1958. However, the first metal oxide

semiconductor field effect transistor (MOSFETs) was invented by Dawon Kahng and Martin

Atalla at Bell Laboratory in 1959. Since that, germanium was largely replaced by silicon due

to several reasons. The reasons include that silicon exhibits larger bandgap than germanium

resulting in lower leakage current. Second, SiO2 reveals excellent thermal stability and quality

for silicon as the gate dielectric compared to water-soluble and thermal unstable GeO2 for

germanium [1.1]. Third, silicon is abundant on the earth’s surface. Therefore, silicon has

formed the basis of the semiconductor industry almost since its birth.

According to Moore’s law [1.2], the number of transistors on integrated circuit doubles

approximately every eighteen months. Continue to shrink each component in an integrated

circuit can allow more complex circuit in the same area or an equally complex circuit in a

smaller area. According to Table 1.1 [1.3], the scaling parameters are derived based on the

constant field scaling, in which the electric field at the semiconductor surface under that gate

2

Recently, it is becoming much difficult to enhance Si complimentary

metal-oxide-semiconductor (CMOS) performance through traditional device scaling. In order

to maintain Moore’s law, MOSFETs with high-mobility channel are attractive for the

advanced CMOS devices [1.4]. Germanium has the potential advantage of having carrier

mobility high enough to overcome the future scaling limits of Si MOSFET and it is

compatible with the conventional Si integration technologies. Therefore, germanium has been

identified as the candidate for the channel engineering.

1.2 Motivation

As we know the driving current of a MOSFET can be described as below

( )2 2 1 t GS ox DS V V L W C I    (1.1)

Cox is the gate oxide capacitance,  is the mobility for hole or electron, W is the channel width,

L is the channel length, VGS is the applied voltage from gate to source and Vt is the threshold

voltage. Which we focus on are the mobility and gate oxide capacitance. As shown in

Table1.2 [1.5], germanium reveals better electron (3900 cm2/V-s v.s. 1500 cm2/V-s) and hole (1900 cm2/V-s v.s. 450 cm2/V-s) mobility than silicon. As we mention above, germanium oxide is water soluble and thermal unstable during fabrication. But there’s a significant

progress toward the replacement of SiO2 gate dielectric with high dielectric constant (high-)

material. Hence, the drawback of germanium oxide becomes less significant.

Recently, effective electrical passivation of germanium for high- gate dielectric layers

using germanium oxide has been investigated [1.6]. However, GeO2 gate stack may lead to

3

the gate stack that high- material directly on germanium. Employing ZrO2 high- dielectric

may be a promising solution. Though the ZrO2 gate stacks have been investigated [1.7-1.9],

the interfaces are still not good enough. Also, they do not use ZrO2 gate stack to realize Ge

MOSFET.

1.3 Scope and Organization of the Thesis

The promising high-mobility substrate material, Ge, is investigated in this thesis. In this

thesis, we focus on the research of using atomic layer deposition (ALD) to deposit ZrO2

directly on germanium and then using high- rapid thermal anneal (high- RTA). The thesis is

divided into five chapters and arranged as follows:

Chapter 1, a brief overview of background and motivation is described.

Chapter 2, p-type germanium MOS capacitor is fabricated using ALD ZrO2. The

interface quality of the ZrO2/Ge system using high- RTA at different temperatures is

investigated. Theory of conductance method is utilized to the extract density of interface state.

Also, by quasi-static C-V curve and Berglund integral, we can estimate the band bending

efficiency from the extracted surface potential.

Chapter 3, both n-MOSFETs and p-MOSFETs are fabricated using gate last process.

The device electrical characteristics are investigated, including ID-VG, IS-VG, ID-VD,

subthreshold swing, series resistance and mobility.

Chapter 4, both n-MOSFETs and p-MOSFETs are fabricated using gate first process.

The device electrical characteristics are investigated, including ID-VG, IS-VG, ID-VD,

subthreshold swing, series resistance and mobility.

4

Table 1.1 Scaling parameter in CMOS circuit design.

Table 1.2 Material properties of bulk Ge, Si, GaAs, and InAs at 300K are compared.

Ge Si GaAs InAs Bandgap (eV) 0.66 1.12 1.42 0.35 Hole mobility(cm2/V-S) 1900 450 400 460 Electron mobility(cm2/V-S) 3900 1500 8500 33000 Conduction band DOS Nc (cm-3) 1.04x1019 2.8x1019 4.7x1017 8.7x1016 Valance band DOS Nv (cm-3) 6x1018 1.04x1019 7x1018 6.6x1018 Lattice constant( o A ) 5.646 5.431 5.653 6.058 Dielectric constant 16 11.9 13.1 15.2 Melting point(°C) 937 1412 1240 942 Dopant activation limit (cm-3) P: (4-6)x1019 P: (1-2)x1020 P: (4-6)x1018 P: (1-3)x1018

5

Chapter 2

ZrO

₂

/Ge Gate Stack MOS Capacitance

2.1 Introduction

The rapid shrinking of the transistor feature size has forced the channel length and gate

dielectric thickness to also decrease rapidly. That is the thickness of SiO2 must decrease with

channel length. However, gate leakage current increase with scaling down the oxide thickness

due to direct tunneling. In order to achieve significant suppression of the direct-tunneling gate

leakage current and continue scale down the EOT, replacing SiO2 with high- dielectric

remarkably demand [2.1].

Development of high-/Ge gate stack with high interface quality and small EOT is

important for Ge to be used as high mobility channel material. Successful of high-/Ge gate

stack such as Al2O3 and HfO2 has been studied, recently. As shown in Table2.1, Al2O3

exhibits wide bandgap energy, large conduction band and valance band offset, thermal

stability and the dielectric constant is 2.3 times larger than SiO2. HfO2 also exhibits wide

bandgap energy, large conduction band and valance band offset, and the dielectric constant is

6.4 times larger than SiO2. There are several multiple gate stack structures have been

investigated, like Al2O3/GeOx/Ge [2.2-2.4] and HfO2/Al2O3/GeOx/Ge [2.5]. Though, the

technique of postoxidation has been developed to reduce the GeOx thickness and still maintain

the good interface quality, the EOT is still restricted due to not enough high dielectric constant

of Al2O3. To overcome this obstacle, much higher-k HfO2 is introduced. Nevertheless

HfO2/GeOx/Ge is not workable since the Ge-Hf bonds which can be produced owing to the

6

leakage pathway [2.6]. So, Al2O3 plays an important role in HfO2/Al2O3/GeOx/Ge gate stack

not only serving oxygen diffusion barrier but also suppress Ge diffusion to form leakage path.

However, the existence of Al2O3 may restrict the EOT to be further scaled down.

In this chapter, p-type germanium MOS capacitors are fabricated with ZrO2/Ge gate

stack by plasma enhanced ALD (PE-ALD) which use Tetrakis(ethylmethylamino)zirconium

(TEMAZr) as precursor and then followed by oxygen plasma . The reason why we use ZrO2

is that it exhibits high dielectric constant and also ZrO2 directly on Ge won’t cause leakage

path like HfO2. The effect of different PE-ALD ZrO2 growth temperatures and different post

deposition annealing (PDA) temperatures are investigated. Theory of the conductance method

is discussed in detail, and utilized to extract the density of interface state (Dit) for the different

samples.

2.2 Fabrication of PE-ALD ZrO

2

/Ge MOS Capacitors

(100)-oriented p-Ge substrates with resistivity ca. 0.1 ·cm ~ 0.6 ·cm were used. In

order to fabricate Ge MOS capacitors, Ge wafers were cleaned by diluted Hydrofluoric acid

(DHF) and deionized water to remove native oxide. Then ZrO2 film is obtained by PE-ALD

growth with an interfacial GeOx layer on each sample at 200°C and 250°C. Followed, each

sample was annealed at 500°C and 600°C in N2 ambient for 1 minute, respectively. Then, we

defined gate electrode area by photolithography and then 1000 o

A Ti/Pt was deposited by

sputtering. Finally, 4000 o

A Al was deposited by thermal coater as backside contact.

The process flow and MOS capacitor structure are shown in Fig. 2.1 and Fig. 2.2. Also

the cross-section transmission electron microscopy (TEM) image of the ZrO2/Ge gate stack

7

2.3 Electrical and Physical Characteristics of Ge MOS Capacitors

with Various PDA Conditions

The C-V characteristic can be discussed by equivalent circuit in Fig. 2.4 [2.7]. Cox is

oxide capacitance, Cp is accumulation capacitance, Cb is bulk capacitance, Cn is inversion

capacitance and Cit is interface trap capacitance. We take the p-type substrate as the example.

When bias is negative, the surface is accumulated by hole, Cp is very high approaching a short

circuit. For small positive bias, the surface is depleted. The space charge in the deletion region

dominates and the interface charge will also contribute to the capacitance. For positive bias,

Cn dominate. If the electron charge can follow the ac frequency Fig. 2.5(d), Cn is very high

approaching a short circuit. If the electron charge can’t follow the ac frequency Fig. 2.5(e),

then Cb dominates.

High interface trap density may cause inefficient Fermi level response or even Fermi

level pinning, preventing control over the carrier in the channel and the realization of

MOSFETs with good sub-threshold swing and high driving current. That is the reason why we

want a lower density of interface state. Fig. 2.5 and Fig. 2.6 show the multi-frequency C-V of

Ge MOS capacitors with different ALD temperatures and different PDA conditions. The more

detailed C-V characteristic is shown in Table2.2. The hump of C-V curve in the depletion

region indicates there are traps at the ZrO2/Ge interface. We can obviously see that the MOS

capacitors with ALD at 200°C reveal much larger hump in the depletion region, which means

that the interface between ZrO2 and Ge reveals higher density of interface state. This

phenomenon may be the fact that the oxidation at lower ALD temperature is less complete

than higher ALD temperature. Also, we can see that the MOS capacitor with PDA at 600°C

8

conclude that using ALD at 250°C to form ZrO2/Ge gate stack and then annealing at 600°C

can result in much better interface quality.

To further investigate the impact of PDA, we analyze the interface by Ge 3d XPS spectra.

Fig. 2.7 shows the Ge 3d spectra of ZrO2/Ge structure that without PDA, PDA at 500°C for 1

minute in N2 and PDA at 600°C for 1 minute in N2. We can see that with higher PDA

temperature, the sample leads to more germanium suboxide. Because of Ge surface passivated

with ZrO2 are slowly oxidized without causing GeO diffusion. As a result, Ge atoms near

MOS interface can be terminated with oxygen atoms or Ge atoms without dangling bonds

even under the oxidation condition lower than GeO2, leading to lower Dit with Ge suboxide

[2.8]. This suggests that the decrease of density of interface state is attributable to more

germanium suboxide.

Also, we use grazing incidence X-ray diffraction (GIXRD) to identify the crystalline

phase of ZrO2. The spectrum is shown in Fig. 2.8. All the conditions, such as as-deposited

ZrO2, ZrO2 annealing at 500°C and 600°C show amorphous phase of gate dielectrics.

2.4 Determine the D

it

at ZrO

2

/Ge Interface

2.4.1 Conductance Method

It is often impractical to fabricate MOSFETs for germanium because the transistor

fabrication may introduce other issue. Therefore, MOS capacitor structures are commonly

used to investigate the interface of dielectric and substrate. The conductance method,

proposed by Nicollian and Goetzberger in 1967, is one of the most sensitive methods to

determine Dit [2.9-2.10]. The main advantage of conductance method is that Dit can be

9

Dit in depletion and weak inversion portion of the bandgap and the capture cross-sections for

majority carriers. The conductance method is based on analyzing the loss due to interface trap

capture and emission of carriers. The measurement is applied a dc gate voltage with a small

amplitude ac signal (~25 mV) and frequency (typically between 1 MHz and 1 kHz).

The simplified equivalent circuit of MOS capacitor appropriate for the conductance

method is shown in Fig. 2.9 (a). It consists of the oxide capacitance Cox, the semiconductor

capacitance CS, and the interface trap capacitance Cit. The circuit can be simplified as in Fig.

2.9 (b), where Cp and Gp are given by

₂ ) ( 1 it it S p C C C     , (2.1) and 2 ) ( 1 _it it it p q D G      _. (2.2)

The interface trap capacitance is related to density of interface state by C_it q2D_it, where q

is the elemental charge, is the angular frequency, 2f (f is the measurement frequency).

The trap response time is given by Shockley-Read-Hall statistic of capture and emission rate:

                         T k E E N v T k E E N v B V t V h th h it B t C C e th e it exp ) ( exp ) ( 1 , , 1 , ,     , (2.3)

where  is the capture cross section, vth is the thermal velocity, N is the effective density of

state of majority carrier band, Ec and Ev are the conduction band and valence band energy, Et

is the trap energy in bandgap, kB is the Boltzmann constant and T is the temperature. Eq. (2.1)

and (2.2) are for interface trap with a single energy level in bandgap. However, interface traps

10

dispersion must be taken into account and the normalized conductance is shown:

ln



1 ( )2



2 _it it it p qD G      . (2.4)

The maximum appears at ω ≈ 2/ and we find

max 5 . 2         p it G Aq D , (2.5)

where A is the device area. GP/ω plots are repeated at different gate voltage to determine Dit

from the maximum GP/ω and determine τit from ω at the peak conductance location on the

ω-axis.

For measurement, the equivalent circuit is shown in Fig.2.9 (c), where Cm is measured

capacitance, Gm is measured conductance. We can express GP/ω as

2 2 2 2 ) ( _{ox m} m ox m p C C G C G G       _. (2.6)

2.4.2 D

it

Measurement of ZrO

2

/Ge Interface

Fig. 2.10 shows trap level position calculated from Eq. (2.3), assuming the capture

cross-section =1x10-16 cm2. The interface trap response frequency as a function of temperature determines which trap in bandgap can be observable in MOS admittance

characteristic. Due to typically measurement frequency (between 1 MHz and 1 KHz), it is

unable to extract Dit in the whole bandgap at room temperature. Therefore, we vary the

temperature to extract Dit in the whole bandgap. We can see that traps locate near to midgap

can be observed at high temperature and traps locate near to band edge can be observed at low

temperature.

Fig. 2.11 shows Gp/Aωq versus frequency of Ge MOS capacitor with different PDA

conditions at 300K. The Dit value is estimated by multi peak values of the plot of Gp/Aωq

11

energy in bandgap by Eq. (2.3). Therefore, the plot of interface state density versus energy in

the bandgap can be obtained by repeated different gate voltages.

The capture cross-section is assumed to be 1x10-16 cm2. And the plot of Dit versus

valance band energy offset is shown in Fig. 2.11. We can see that the MOS capacitor with

PDA at 600°C reveals about two times smaller interface states than the MOS capacitor with

PDA at 500°C. The result matches to what we discuss in chapter 2.3. The lower hump in

depletion region indicates lower density of interface states. Also, with higher PDA

temperature, the interface between ZrO2 and germanium contains more Ge suboxide which

helps to improve the quality of interface.

The results show more interface state density in the midgap and this phenomenon is called

“weak inversion response” [2.11]. Due to small bandgap of germanium, the interface traps

will show a communication with majority and minority carrier in measurement frequency

when a MOS capacitor is biased in weak inversion. The schematic band diagram is shown in

Fig. 2.13. The traps can be filled or emptied by minority carrier is due to the proximity of

Fermi level to minority carrier band.

The presence of the weak inversion response within the typical 1 KHz to 1 MHz

measurement frequency depends on the bandgap energy, the capture cross section and the

temperature. For silicon, this phenomenon does not occur in measurement frequency at 300K

[2.12]. However, for small bandgap material like germanium, the weak inversion response

will occur in measurement frequency at room temperature. As we mention in Eq. (2.3), lower

temperature measurement may be a solution to prevent this effect.

Fig. 2.14 shows the relation between gate voltage and surface potential by quasi-static

CV and Berglund integral.

G V V QS S dV Cox C G FB



         1  .

12

than Ge MOS capacitor with PDA at 500°C. Much effective band banding can also confirm

that Dit for the sample with PDA at 600°C is less than PDA at 500°C.

2.5 Conclusion

ZrO2/Ge MOS capacitors are fabricated using PE-ALD. The interface of ZrO2/Ge is

investigated with different ALD temperature and different PDA conditions. The Ge 3d XPS

spectra of different samples such as as-deposited ZrO2, ZrO2 with PDA at 500°C and 600°C

are shown. The XPS spectra show that with more germanium suboxide, the interface owns

lower density of interface states. Conductance method was discussed in detail and utilized to

extract Dit and confirm what we mention in Chapter 2.3.

The EOT is scaled down to around 1.7 nm and a lower Dit value is obtained by PDA at

600°C in N2 ambient. Finally, we choose ZrO2/Ge gate stack using PE-ALD at 250°C and

then PDA at 600°C in N2 ambient to be the optimized condition to fabricate germanium

13

Table 2.1 Comparison of relevant properties for high- candidate.

Fig. 2.1 Process flow of (100)-oriented Ge MOSCAPs with different ALD temperature and different PDA conditions.

14

Fig. 2.2 MOSCAP of ZrO2/Ge gate stack structure.

15

16 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0 0.5 1.0 1.5 2.0 2.5 ALD 200°C , PDA 500°C

C

a

p

a

ci

ta

n

ce

(

F

/cm

2

)

Voltage (V)

1 MHz 100 KHz 10 KHz 1 KHz (a) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0 0.5 1.0 1.5 2.0 2.5 ALD 200°C , PDA 600°C

C

a

p

a

ci

ta

n

ce

(

F

/cm

2

)

Voltage (V)

1 MHz 100 KHz 10 KHz 1 KHz (b)

Fig. 2.5 Multi-frequency C-V of Ge MOS capacitor with different PDA condition using ALD

17 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 0.5 1.0 1.5 2.0 2.5 ALD 250°C , PDA 500°C

C

a

p

a

ci

ta

n

ce

(

F

/cm

2

)

Voltage (V)

1 MHz 100 KHz 10 KHz 1 KHz (a) -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 0.5 1.0 1.5 2.0 2.5 ALD 250°C , PDA 600°C

C

a

p

a

ci

ta

n

ce

(

F

/cm

2

)

Voltage (V)

1 MHz 100 KHz 10 KHz 1 KHz (b)

Fig. 2.6 Multi-frequency C-V of Ge MOS capacitor with different PDA condition using ALD

18

Table 2.2 C-V characteristic with different PDA temperature; (a) ALD at 200°C, and (b) ALD

at 250°C.

ALD at 200°C

PDA temp.

C

ox

(F/cm

2

)

EOT (nm)

VFB (V)

500°C

1.95

1.77

-0.15

600°C

2.02

1.709

-0.3

(a)

ALD at 250°C

PDA temp.

Cox (F/cm

2

)

EOT (nm)

VFB (V)

500°C

2.01

1.717

-0.1

600°C

2.00

1.726

-0.15

19 36 34 32 30 28 26 As Deposited

In

te

n

si

ty

(

a

.u

.)

PDA 500°C Ge1+

Binding Energy (eV)

Ge0+ Ge2+

Ge3+ Ge4+

PDA 600°C

Fig. 2.7 Deconvolution of the XPS spectra of ZrO2/Ge structure with different PDA

conditions. 20 30 40 50 60 70 80 0 50 100 150 200

In

ten

si

ty

(c

o

u

n

ts

)

2 Theta()

20

Fig. 2.9 Equivalent circuit for conductance measurement; (a) MOS capacitor with interface

trap time constant τit = RitCit , (b) simplified circuit of (a), and (c) measured circuit.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

10

1

10

2

10

3

10

4

10

5

10

6

10

7

10

8

10

9

Assume capture cross section : 1E-16 cm

2

In

te

r

fa

c

e

T

r

a

p

Fr

eq

u

e

n

c

y

(

Hz

)

Energy in Bandgap (eV)

300K 250K 180K 120K 77K

E

_v

E

_c

21 103 104 105 106 0.0 0.5 1.0 1.5 2.0 2.5 V_G=-0.6~-0.1 (V) step=0.02 (V) Temp=300K PDA 500°C

G

p

/A



q

(

1

0

1 2

eV

-1

cm

-2

)

Frequency (Hz)

V_G= -0.1 V V_G= -0.6 V (a) 103 104 105 106 0.0 0.5 1.0 1.5 2.0 2.5 V_G=-0.6~-0.1 (V) step=0.02 (V) Temp=300K PDA 600°C

G

p

/A



q

(

1

0

1 2

eV

-1

cm

-2

)

Frequency (Hz)

V_G= -0.1 V V_G= -0.6 V (b)

Fig. 2.11 / versus frequency of Ge MOS capacitor with different PDA conditions; (a) PDA at 500°C, and (b) PDA at 600°C.

22 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.5 1.0 1.5 2.0 2.5 3.0 PDA 500°C PDA 600°C

D

it (

1

0

1 2

c

m

-2

e

V

-1 )

Valance Band Offset (eV)

E_{v E}

c

Fig. 2.12 Dit measurement of Ge MOS capacitors with different PDA conditions.

23 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 -0.4 -0.2 0.0 0.2 0.4 0.6 P-Ge _s from QSCV PDA 500°C

S

u

rf

a

ce

p

o

ten

ti

a

l,



s

(

V

)

V

_G

-V

_FB

(V)

accumulation inversion E_c E_v (a) -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -0.4 -0.2 0.0 0.2 0.4 0.6 P-Ge _s from QSCV PDA 600°C

S

u

rf

a

ce

p

o

ten

ti

a

l,



s

(

V

)

V

_G

-V

_FB

(V)

E_c E_v accumulation inversion (b)

Fig. 2.14 relation between gate voltage and surface potential by integration of quasi-static CV;

24

Chapter 3

Germanium MOSFETs with ZrO

₂

/Ge

Gate Stack Using Gate Last Process

3.1 Introduction

Since the technology node of complementary metal-oxide-semiconductor (CMOS)

comes to 22 nm, it is becoming much difficult to enhance Si CMOS performance through

traditional device scaling [3.1].To further improve the device performance, channel materials

with high mobility will be needed for future nodes to meet the ITRS requirements of

MOSFETs [3.2]. Germanium is one of potential candidate to replace silicon due to high

electron and hole mobility. Also, it is compatible with the conventional silicon integration

technologies

Compared to SiO2, GeOx is water soluble and reveals poor thermal stability. However, by

replacing dielectric with high- material, the main drawback of germanium disappears.

Recently, high hole and electron mobility have been reported for Ge p-MOSFETs [3.3] and

Ge n-MOSFETs [3.4-3.5]. Ge n-MOSFETs always exhibit poor driving currents and mobility

lower than universal Si mobility. The reasons are the large source/drain resistance due to

low-level activation of n-type dopant. Also, fermi level pinning at the interface between n-Ge

and metal leads to the formation of a Schottky barrier which is almost independent on the

metal work function [3.6-3.8]. Therefore, the good passivation of the gate oxide/channel

interface is needed to improve Ge n-MOSFETs performance.

25

last process. Junction and device characteristics, series resistance, subthreshold swing and

mobility are discussed.

3.2 Fabrication of Gate Last Ge-MOSFETs

(100)-oriented p-Ge substrates and (100)-oriented n-Ge substrates with resistivity ca. 0.1

·cm ~ 0.6 ·cm and ca. 0.6 ·cm ~ 0.94 ·cm were used to fabricate Ge n-MOSFETs and

Ge p-MOSFETs, respectively. In order to fabricate Ge MOSFETs, Ge wafers were cleaned by

diluted Hydrofluoric acid (DHF) and deionized water to remove native oxide. Then we

deposited 4200 o

A SiO2 for field oxide by Plasma-enhanced chemical vapor deposition

(PECVD). The source and drain region were defined by first photolithography, followed by

implantation of phosphorous for Ge n-MOSFETs and BF2 for Ge p-MOSFETs. Both

phosphorous and BF2 dopant concentration are 1x15 cm-2 and implant energy are 20 keV.

After implantation, we deposited 1000 o

A SiO2 for capping layer to prevent dopant

out-diffuses during dopant activation. Then we activated dopant by rapid thermal annealing

(RTA) system 600°C 30 second for BF2 and 600°C 10 second for phosphorous, respectively.

Next active area (AA) was defined by second photolithography and then 40 cycles PE-ALD

ZrO2 was deposited at 250°C. The samples were annealed using high- RTA at 600°C for 60

second in N2 ambient. After annealing, contact hole was defined by third photolithography,

followed dry etching the contact hole on source/drain region. 4000 o

A Al was deposited by

thermal coater and then defined metal pads through fourth photolithography. Finally, 4000 o A

Al was deposited as backside contact. The process flow and device structure are shown in Fig.

26

3.3 Electrical Characteristic of Ge MOSFETs

Fig. 3.3 shows the junction characteristics of Ge p-MOSFET and Ge n-MOSFET. For

p+/n junction, the current density at forward bias and reverse bias are 6.584x101 A/cm2 at 1 V and 3.93x10-3 A/cm2 at -1 V, respectively while the on/off ratio is about 1.66x104. For n+/p junction, the current density at forward bias and reverse bias are 5.06x101 A/cm2 at -1 V and 3.29x10-4 A/cm2 at 1 V, respectively while the on/off ratio is about 1.51x105. The higher current density at reverse bias of germanium device compare to silicon devices is due to

smaller bandgap of germanium. To extract junction series resistance, we know that:

nkT Ir V q _s e I I  ₀ (  )/ , and nkT g r qI dV dI g s d d ) 1 (    . (3.1)

We can write Eq. (3.1) as

s d Ir q nkT g I   .

A plot of I/gd versus I can determine series resistance (rs) from slope. For p+/n junction, the

series resistance is about 59.4 Ω. For n+/p junction, the series resistance is about 47.7 Ω. To extract ideality factor, we know that:

I I₀eqV/nkT(1eqV/kT). (3.2)

We can write Eq. (3.2) as

V nkT q I e I kT qV          / ln 0 1 ln .

A plot of ln[I/(1-exp(-qV/kT))] versus V can determine ideality factor (n) from slope. The

ideality factor of p+/n junction is 1.262 and that of n+/p junction is 1.512.

27

For Ge p-MOSFET, the on/off ratio is about 5.62x104 for IS and 2.92x103 for ID. For Ge

n-MOSFET, the on/off ratio is about 1.85x105 for IS and 1.73x104 for ID. The reason why

on/off ratio of ID is always lower than that of IS is due to small bandgap energy of germanium

causes junction leakage. Our MOSFETs also show serious gated-induce drain leakage current

(GIDL) due to large gate to source/drain overlapping area. The subthreshold swing of

p-MOSFET is about 119.1 mV/dec, while that of n-MOSFET is about 112.5 mV/dec.

Fig. 3.5 shows ID-VD characteristics of Ge p-MOSFET and Ge n-MOSFET. At the same

overdrive voltage, we can observe that p-MOSFET reveals much larger driving current than

n-MOSFET, due to n-MOSFET reveals much larger source/drain resistance than p-MOSFET.

As we know, n-type dopant like phosphorous is much easier lost during subsequent annealing

by out-diffusion [3.9-3.10]. During high-dielectric annealing, there’s only about 3~4 nm

ZrO2 film on source/drain region, such a thin film could not restrict phosphorous out-diffuse.

Also, activation of n-type dopant in germanium is a problem which the active level of n-type

dopant in germanium is much lower than p-type dopant in germanium [3.11-3.12].

Fig. 3.6 shows the plot of measured resistance versus channel length on mask for Ge

p-MOSFET and Ge n-MOSFET. We extract source/drain series resistance (RSD) by Terada

and Muta method [3.13].

= = + = ∆

( )+ , (3.3)

where Rm is measured resistance, Rch is channel resistance; RSD is source/drain series

resistance. Eq. (3.3) gives Rm=RSD while L=ΔL. A plot of Rm versus L for device with

different L and varying gate voltage shows lines intersecting at one point giving RSD. If the

lines fail to intersect at same point, we can further write Eq. (3.3) as

= + = ( − ∆ ) + = + . (3.4) The parameters A and B are determined from slope and intercept of Rm versus L plots for

28

measurements, the source/drain series resistance is about 365.2  for p-MOSFET and 1965.4

 for n-MOSFET. Also ΔL=0.75 m for p-MOSFET and ΔL=0.15 m for n-MOSFET.

To extract effective mobility

= ,

where the drain conductance gd is defined as

= | = ,

and Qinv can be measured by split-CV method

= ∫ .

The mobile channel charge density is determined from the gate to channel capacitance, CGC.

Then CGC is measured using the connection of Fig. 3.7, the capacitance meter is connected

between the gate and the source/drain and the substrate is grounded. For VGS < VT the channel

region is accumulated and the overlap capacitances 2Cov are measured (Fig. 3.8 (a)). For VGS

> VT,the surface is inverted and 2Cov+Cch are measured (Fig. 3.8 (b)).

Fig. 3.9 shows hole mobility as a function of inversion charge density for Ge p-MOSFET.

The peak hole mobility of p-MOSFET is about 259 cm2/V-s. Here we do not show the electron mobility of Ge n-MOSFET because of the huge source/drain series drain resistance.

The voltage drop across the source/drain resistance IDRSD causes a reduction in drain current.

Hence, the measured mobility by split C-V method appears to be lower than the real value.

3.4 Conclusion

In Chapter 3, we investigate fabrication and electric characteristics of Ge MOSFETs. For

Ge p-MOSFET (the channel width is 100 m, the channel length is 5 m), the on /off ratio of

29

the substhreshold swing is about 119.1 mV/dec. For Ge n-MOSFET (the channel width is 100

m, the channel length is 5 m), the on /off ratio of n+/p junction, ID-VG and IS-VG are about

1.51x105, 1.73x104, and 1.86x105, respectively, while the substhreshold swing is about 112.5 mV/dec.

From ID-VD curve we can see that Ge n-MOSFET reveals poor driving current than Ge

p-MOSFET at the same overdrive voltage. As we mentioned, n-type dopant in germanium

diffuses much easier than p-type dopant in germanium. So n-type dopant will be much easier

lost during subsequent thermal process because such a thin high- film on source/drain region

cannot restrict the dopant out diffuse. Also, the activation level of n-type dopant in

germanium is lower than p-type dopant in germanium. Due to these problems, Ge

n-MOSFETs always exhibit poor performance than Ge p-MOSFETs.

To solve these problems, changing fabrication scheme may be a solution. In next chapter,

30

Fig. 3.1 Process flow of Ge MOSFETs.

31 -1.0 -0.5 0.0 0.5 1.0 10-4 10-3 10-2 10-1 100 101 102 I_on/I_off: ~1.66x104 r_s: 59.4 n: 1.262 P+/N Junction

C

u

rre

n

t

D

en

si

ty

(

A

/c

m

2

)

Voltage (V)

(a) -1.0 -0.5 0.0 0.5 1.0 10-5 10-4 10-3 10-2 10-1 100 101 102 I_on/I_off: ~1.51x105 r_s: 47.7 n: 1.512 N+/P Junction

C

u

rre

n

t

D

en

si

ty

(

A

/c

m

2

)

Voltage (V)

(b)

Fig. 3.3 I–V characteristics of p+/n and n+/p junctions; (a) p+/n junction, and (b) n+/p junction. 0 1 2 3 4 5 6 7 0.2 0.4 0.6 I/ gd ( V ) Current (mA) 0 1 2 3 4 5 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 I/ g d ( V ) Current (mA)

32 -2.0 -1.5 -1.0 -0.5 0.0 10-4 10-3 10-2 10-1 100 101 102 I D(VD=-0.1 V) I_D(V_D=-1 V) I S(VD=-0.1 V) I_S(V_D=-1 V) I_on/I_off(I_S) ~ 5.62x104 I_on/I_off(I_D) ~ 2.92x103 S.S.=119.1 (mV/dec) W/L=100 m/5m

S

o

u

r

ce

/D

ra

in

C

u

r

re

n

t

(

A

/

m

)

Gate Voltage (V)

(a) -0.5 0.0 0.5 1.0 1.5 2.0 10-5 10-4 10-3 10-2 10-1 100 101 102 I_D(V_D=0.1 V) I_D(V_D=1 V) I_S(V_D=0.1 V) I_S(V_D=1 V) I_on/I_off(I_S) ~ 1.86x105 I_on/I_off(I_D) ~ 1.73x104 S.S.=112.5 (mV/dec) W/L=100 m/5 m

S

o

u

rce/

D

ra

in

C

u

rr

en

t

(



A

/

m

)

Gate Voltage (V)

(b)

Fig. 3.4 ID-VG and IS-VG characteristics of Ge MOSFETs; (a) Ge p-MOSFET, and (b) Ge

33 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0 2 4 6 8 10 12 W/L=100m/5m V_G-V_t=0~-1.1 V step=-0.1 V

D

ra

in

C

u

rren

t

(



A

/

m

)

Drain Voltage (V)

(a) 0.0 0.2 0.4 0.6 0.8 1.0 0 1 2 3 4 5 6 7 8 9 W/L=100m/5m V_G-V_t=0~1.7 V step=0.1 V

D

ra

in

C

u

rren

t

(



A

/

m

)

Drain Voltage (V)

(b)

34 0 10 20 30 40 50 0 1000 2000 3000 4000 5000 6000

R

_SD

=365.2 

L(m)

V_G-V_t=-0.5 (V) V_G-V_t=-0.7 (V) V_G-V_t=-0.9 (V)

R

m

(



)

Channel Length on Mask

(

m

)

(a) 0 10 20 30 40 50 2000 3000 4000 5000 6000 7000 V_G-V_t=1.2 (V) V_G-V_t=1.4 (V) V_G-V_t=1.6 (V)

R

m (



)

Channel Length on Mask

(

m

)

R

_SD

=1965.4 ()

L=1.75 (m)

(b)

Fig. 3.6 Rm versus L as a function of gate voltage to extract series resistance; (a) Ge

35

36 (a)

(b)

Fig. 3.8 Schematic for gate to channel capacitance measurements for (a) VGS < VT, and (b)

37 0.5 1.0 1.5 2.0 2.5 3.0 0 50 100 150 200 250 300

H

o

le

M

o

b

il

it

y

(

c

m

2

/V

-s

)

N

_inv

(10

12

cm

-2

)

38

Chapter 4

Germanium MOSFETs with ZrO

₂

/Ge

Gate Stack Using Gate First Process

4.1 Introduction

Recently, Ge p-MOSFET with high hole mobility has been reported [4.1-4.2]. But the Ge

n-MOSFET is still not good enough due to the high interface density of state (Dit) [4.3] and

the poor n+/p junctions. Though, attention has been paid more to GeO2/Ge gate stack due to

its superior interface properties and has been reported with low Dit recently [4.4-4.7], the n+/p

junctions still suffer from the low activation and fast diffusion rate of n-type dopants in

germanium.

A SiO2 capping layer has been utilized to prevent dopant out-diffuse [4.8]. In Chapter 3,

we have used this method to prevent dopant out-diffuse. However, SiO2 capping layer will be

removed and the dopant will out-diffuse during subsequent process. In order to conquer this

drawback, change the fabrication scheme may be a solution. By gate first process, the

source/drain will be defined after gate stack formation. Due to this change, more effective

dopant activation caused by the last high temperature step in the gate first process can prevent

dopant out-diffuse.

In this chapter, both germanium n-MOSFET and p-MOSFET are fabricated using gate

first process. Junction and device characteristics, series resistance, subthreshold swing and

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4.2 Fabrication of Gate First Ge-MOSFETs

(100)-oriented p-Ge substrates and (100)-oriented n-Ge substrates with resistivity ca. 0.1

·cm ~ 0.6 ·cm and ca. 0.6 ·cm ~ 0.94 ·cm were used to fabricate Ge n-MOSFETs and

Ge p-MOSFETs. In order to fabricate Ge MOSFETs, Ge wafer were cleaned by diluted

Hydrofluoric acid (DHF) and deionized water to remove native oxide. Then we deposited

4200 o

A SiO2 for field oxide by Plasma-enhanced chemical vapor deposition (PECVD). The

active area (AA) region was defined by first photolithography. And then 80 cycles ZrO2 was

deposited at 250°C using PE-ALD. After ZrO2 deposited, the samples were annealed using

high- RTA at 600°C for 60 second in N2 ambient. Followed, 500

o

A TiN was deposited for

gate electrode by sputtering. Next, 500 o

A SiO2 was capping for hard mask and 5000

o A

SiO2 was capped at backside by PECVD. Because of the solution to etch TiN will etch

photoresist, so we capped 500 o

A SiO2 on TiN for hard mask. Also, the solution to etch TiN

will etch germanium, so we must cap 5000 o

A SiO2 to protect bulk germanium. Then gate

was defined by second photolithography. Followed phosphorous for Ge n-MOSFETs and BF2

for Ge p-MOSFETs were implanted. Both phosphorous and BF2 dopant concentration are

1x15 cm-2 and implant energy are 20 keV. Due to gate first process the source/drain region will be self-align. After implantation, we deposited 1000

o

A SiO2 for capping layer by

PECVD to prevent dopant out-diffuses during dopant activation. Then, we activated dopant

by rapid thermal annealing (RTA) system 600°C 30 second for both Ge n-MOSFET and Ge

p-MOSFET. Next, contact hole was defined by third photolithography, followed dry etching

the contact hole on source/drain and gate region. 4000 o

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coater and then defined metal pads through fourth photolithography. Finally, 4000 o

A Al was

deposited as backside contact. The process flow and device structure are shown in Fig. 4.1

and Fig. 4.2.

4.3 Electrical Characteristic of Ge MOSFETs

Fig. 4.3 shows the junction characteristics of Ge p-MOSFET and Ge n-MOSFET. For

p+/n junction, the current density at forward bias and reverse bias are 3.37x102 A/cm2 at 1 V and 3.87x10-2 A/cm2 at -1 V, respectively. Also, the on/off ratio is about 8.61x104, the ideality factor is 1.255 and the series resistance is 16.2  for p+/n junction. For n+/p junction, the current density at forward bias and reverse bias are 1.64x102 A/cm2 at -1 V and 1.00x10-2 A/cm2 at 1 V, respectively. Also, the on/off ratio is about 1.66x104, the ideality factor is 1.527 and the series is 21.7  for n+/p junction. The higher current density at reverse bias of germanium device compare to silicon devices is due to smaller bandgap of germanium.

Fig. 4.4 shows ID-VG and IS-VG characteristics of Ge p-MOSFET and Ge n-MOSFET.

For Ge p-MOSFET, the on/off ratio is about 3.98x104 for IS and 5.32x103 for ID. For Ge

n-MOSFET, the on/off ratio is about 9.33x104 for IS and 3.02x103 for ID. The reason why

on/off ratio of ID is always lower than that of IS is due to small bandgap energy of germanium

causes junction leakage. The subthreshold swing of p-MOSFET and n-MOSFET is about

125.8 mV/dec and 130.5 mV/dec, respectively.

Fig. 4.5 shows ID-VD characteristics of Ge p-MOSFET and Ge n-MOSFET. At the same

overdrive voltage, we can see that p-MOSFET exhibits much larger driving current than

n-MOSFET, due to n-MOSFET reveals much larger source/drain resistance than p-MOSFET.

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n-type dopant in germanium is much lower than p-type dopant in germanium.

Fig. 4.6 shows the plot of measured resistance versus channel length on mask for Ge

p-MOSFET and Ge n-MOSFET. We extract source/drain series resistance (RSD) by Terada

and Muta method which we discussed in detail in Chapter 3. By our measurement, the

source/drain series resistance is about 50.3  for p-MOSFET and 460.4  for n-MOSFET.

Also, ΔL=0.52 m for p-MOSFET and ΔL=0.93 m for n-MOSFET.

We use split-CV method which has been discussed in chapter 3 to extract effective

mobility. Fig. 4.7 shows hole mobility as a function inversion charge density for Ge

p-MOSFET. The peak hole mobility of p-MOSFET is about 227.4 cm2/V-s. Here we do not show the electron mobility for Ge n-MOSFET because of the large source/drain series

resistance of Ge n-MOSFET. The voltage drop across the source/drain resistance IDRSD causes

a reduction in drain current. Hence, the measured mobility by split C-V method appears to be

lower than the real value.

4.4 Conclusion

In Chapter 4, we investigate fabrication and electric characteristics of Ge MOSFETs. For

Ge p-MOSFET (the channel width is 200 m, the channel length is 5 m), the on /off ratio of

p+/n junction, ID-VG and IS-VG are about 8.61x104, 5.32x103, and 3.98x104, respectively,

while the substhreshold swing is about 125.8 mV/dec. For Ge n-MOSFET (the channel width

is 200 m, the channel length is 5 m), the on /off ratio of n+/p junction, ID-VG and IS-VG are

about 1.66x104, 3.02x103, and 9.33x104, respectively, while the substhreshold swing is about 130.5 mV/dec.

From ID-VD curve we can see that Ge n-MOSFET reveals poor driving current than Ge

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diffuse than p-type dopant in germanium. Also, the activation level of n-type dopant in

germanium is lower than p-type dopant in germanium. Because of these problems, Ge

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44

45 -1.0 -0.5 0.0 0.5 1.0 10-4 10-3 10-2 10-1 100 101 102 103 I_on/I_off ~ 8.61x104 r_s :16.2 n: 1.255 P+/N Junction

C

u

rr

en

t

D

en

si

ty

(

A

/c

m

2 )

Voltage (V)

(a) -1.0 -0.5 0.0 0.5 1.0 10-4 10-3 10-2 10-1 100 101 102 103 I_on/I_off ~ 1.66x104 r_s :21.7 n: 1.527 N+/P junction

Cu

rr

en

t

De

n

si

ty

(

A/

cm

2

)

Voltage (V)

(b)

Fig. 4.3 I–V characteristics of p+/n and n+/p junctions; (a) p+/n junction, and (b) n+/p junction. 0.00 0.01 0.02 0.03 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 I /g d ( V ) Current (A) 0.000 0.004 0.008 0.012 0.016 -0.5 -0.4 -0.3 -0.2 -0.1 I/ g d ( V ) Current (A)