Reverse Body Bias (V)
4.4 FBB Analysis
Forward body bias is originally arranged to co-work with DVS to solve the problem of performance coherence in our CTAPM design. However, this technique doesn’t show enough competence for the job based on used TSMC 100nm technology.
Related simulation results will be expressed to explain the statement in this Section.
Reviewed from Section 4.2, supply voltage range can be divided into high, middle, and low VDD zones. When operating in high and middle VDD zones, frequency decreases as temperature increases, which causes the problem of performance coherence between functional blocks. However, frequency increases as temperature increases in the low VDD zone, resulting in no performance coherence problem at all.
Figure 4.12 and Figure 4.13 clearly illustrate these phenomena once more. In this place, we define that the 600MHz speed mode is in the high VDD zone, and the 500MHz and 400MHz speed modes are in the middle VDD zone, whereas the last two low speed modes are in the low VDD zone.
Temperature (C)
-60 -40 -20 0 20 40 60 80 100 120 140
Operating Frequency (MHz)
400 500 600 700 800 900 1000 1100
FF corner of tsmc 100nm technology FS corner of tsmc 100nm technology TT corner of tsmc 100nm technology SF corner of tsmc 100nm technology SS corner of tsmc 100nm technology
Figure 4.12 Relationship between operating frequency and
temperature in five technology corners for the high VDD zone. Supply voltage is 1.0V. Frequency decreases as temperature increases.Temperature (C)
-60 -40 -20 0 20 40 60 80 100 120 140
Operating Frequency (MHz)
0 50 100 150 200 250 300 350
FF corner of tsmc 100nm technology FS corner of tsmc 100nm technology TT corner of tsmc 100nm technology SF corner of tsmc 100nm technology SS corner of tsmc 100nm technology
Figure 4.13 Relationship between operating frequency and
temperature in five technology corners for the low VDD zone. Supply voltage is 500mV. Frequency increases as temperature increases, so that there is no problem of performance coherence.Following is the evidences showing that FBB is not that effective to increase speed. As shown in Figure 4.14, applying FBB on PMOS is more powerful than NOS because of stronger body effect for the same FBB voltage level. Even so, it still can’t catch the frequency loss due to temperature raise. The speed of the ring oscillator decreases about 20MHz from 25°C to 50°C when the supply voltage is 1.0V, but applying FBB can only provide about 15MHz performance gain. Besides, although applying heavier FBB on PMOS can further increase the speed, the power overhead will be amazingly huge. For example, applying 650mV FBB on PMOS can compensate the frequency loss, but its power consumption at room temperature rises
from 37.40uW to 373.14uW, which is absolutely not applicable. Hence, we choose to raise 10 ~ 20mV of the supply voltage to deal with frequency sacrifice due to temperature rise in Section 4.2, since its power overhead is quite little.
Forward Body Bias (mV)
0 100 200 300 400 500 600 700
Operating Frequency (MHz)
660 670 680 690 700 710 720 730
Both PMOS and NMOS PMOS only
NMOS only
Figure 4.14 Relationship between operating frequency and forward
body bias at 25°C in the high VDD zone. Supply voltage is 1.0V.Figure 4.15 shows similar results as Figure 4.14. We notice that the applicable FBB range is narrower at high temperature, reducing the speed increase that FBB can provide. Although the frequency loss is reduced to about 12MHz from 125°C to 150°C when the supply voltage is 1.0V, applying FBB can only provide about 6MHz performance gain, still not enough to overcome this thermal impact.
Forward Body Bias (mV)
0 100 200 300 400 500
Operating Frequency (MHz)
590 600 610 620 630 640 650
Both PMOS ans NMOS PMOS only
NMOS only
Figure 4.15 Relationship between operating frequency and forward
body bias at 125°C in the high VDD zone. Supply voltage is 1.0V.Concerning about the middle VDD zone, however, Figure 4.16 presents the power of forward body bias to increase speed. The frequency loss is about 8MHz from 25°C to 50°C when the supply voltage is 750mV, and applying FBB can provide about 30MHz performance gain to compensate this loss. Besides, the applicable FBB range is about the same with the high VDD zone case, revealing that it is less dependent on the supply voltage than operating temperature.
Forward Body Bias (mV)
0 100 200 300 400 500 600 700
Operating Frequency (MHz)
400 420 440 460 480 500
Both PMOS and NMOS PMOS only
NMOS only
Figure 4.16 Relationship between operating frequency and forward
body bias at 25°C in the middle VDD zone. Supply voltage is 750mV.According to Figure 4.14 to Figure 4.16, we can draw Figure 4.17 to conclude the FBB characteristics. The lower the supply voltage and operating temperature are the better performance improvement it has. Therefore, when operating in the high VDD
zone, DVS is used alone to ensure performance coherence between functional blocks.
In the middle VDD zone, FBB can co-work with DVS to solve the problem. However, it is unnecessary to adopt FBB in the low-VDD operation, since the frequency, since there is no performance coherence problem in this situation.
Figure 4.17 Illustration of FBB application efficiency. FBB is suitable
in middle-VDD and low-temperature environments.At last, one thing should be clarified. Even though FBB is applicable in the middle VDD zone, we don’t take this option eventually. Instead, DVS is still used alone to face the frequency loss for simplicity. As shown in Figure 4.18, although applying FBB can reduce VDD at the same target frequency, the power consumption is higher because the circuit is leakier due to the decrease of threshold voltage. Raising a margin VDD is more efficiency to ensure performance coherence in this technology.
16.6 16.62 16.64 16.66 16.68 16.7 16.72 16.74 16.76
Power Consumption (uW)
800mV VDD 0mV FBB
790mV VDD 200mV FBB
780mV VDD 400mV FBB
Figure 4.18 Comparison of power consumptions at 500MHz between
different VDD and FBB voltages. FBB is applied on PMOS.4.5 Discussion
In our analysis flow, every design decision is based on its own trade-offs for each low power technique. For example, we consider area overhead, virtual ground noise and power consumption when choosing sleep transistor type for power gating, but we are not conscious that this earlier decision has impact for other techniques. In fact, technique-to technique trade-offs need to be taken into account when we make a design decision, and sleep transistor type selection is coincidentally the most complicated case among all design decisions.
Table 4.4 shows the advantages of choosing NMOS or PMOS to be sleep transistors corresponding to power gating and reverse body bias. Since both techniques deal with leakage reduction, they have to compromise to complement each other for some design constraints. For example, if the triple-well technology is not supported by the foundry, inevitably we can’t use NMOS sleep transistors for small area overhead as we wish. Therefore, sometimes we need to “bottom-up” to change or reconsider previous design decisions.