400 500 600 700 800 900 1000 1100
Operating Frequency (MHz)
0 200 400 600 800 1000
FF corner of tsmc 100nm technology FS corner of tsmc 100nm technology TT corner of tsmc 100nm technology SF corner of tsmc 100nm technology SS corner of tsmc 100nm technology
Figure 4.5 Relationships between operating frequency and supply
voltage in five different technology corners.Supply Voltage (mV)
400 500 600 700 800 900 1000 1100
Power consumption (uW)
0 10 20 30 40 50 60 70
FF corner of tsmc 100nm technology FS corner of tsmc 100nm technology TT corner of tsmc 100nm technology SF corner of tsmc 100nm technology SS corner of tsmc 100nm technology
Figure 4.6 Relationships between power consumption and supply
voltage in five different technology corners.Figure 4.7 shows relationships between operating frequency and supply voltage in eight different temperature levels. Figure 4.8 is the corresponding power statistics.
We notice that supply voltage range can be divided into high, middle, and low VDD
zones. When operating in the high VDD zone, frequency decreases as temperature increases, which causes the problem of performance coherence between functional blocks. In the middle VDD zone which is round 700mV in our simulation, frequency decreases slightly as temperature increases. However, frequency increases as temperature increases in the low VDD zone, resulting in no performance coherence problem at all.
The reason of these phenomena is as follows: As temperature rises, the mobility decreases due to more phonon scattering, and the threshold voltage is reduced due to Fermi level. In high and middle VDD zones, the mobility is dominant, so that the drain current and operating frequency are both reduced. However, the threshold voltage is the dominant factor in the low VDD zone, and thus increases the drain current and operating frequency. While this concept is well-known to analog designers, it has so far not been emphasized in digital circuit design.
Supply Voltage (mV)
400 500 600 700 800 900 1000 1100
Operating Frequency (MHz)
0 200 400 600 800 1000
-40 degrees Centigrade -25 degrees Centigrade 0 degrees Centigrade 25 degrees Centigrade 50 degrees Centigrade 75 degrees Centigrade 100 degrees Centigrade 125 degrees Centigrade
Figure 4.7 Relationships between operating frequency and supply
voltage in eight different temperature levels.Supply Voltage (mV)
400 500 600 700 800 900 1000 1100
Power Consumption (uW)
0 10 20 30 40 50
-40 degrees Centigrade -25 degrees Centigrade 0 degrees Centigrade 25 degrees Centigrade 50 degrees Centigrade 75 degrees Centigrade 100 degrees Centigrade 125 degrees Centigrade
Figure 4.8 Relationships between power consumption and supply
voltage in eight different temperature levels.4.2.2 V
DDLook-Up Table Construction
Since frequency increases as temperature increases in the low VDD zone, there is no performance coherence problem in this supply region. Therefore, we raise a margin of supply voltage in high VDD and middle VDD zones to keep performance coherence, but keep minimum required supply voltage in the low VDD zone. Table 4.2 is simulation results of the VDD look-up table. Without utilizing DVS, the supply voltage must be the highest one, 980mV in the table, to ensure normal operation. On the contrary, it only needs to be 500mV for 200MHz operation at 150°C if we utilize
DVS on both frequency and temperature dimensions. It can lead to 74% total power reduction and maintain performance coherence at the same time. By appropriate coding, the logical VDD look-up table can be built like Table 4.3.
Table 4.2 Numerical V
DD look-up table for CTAPM. 10mV is the minimum step.VDD (mV) -40~-25°C -25~0°C 0~25°C 25~50°C 50~75°C 75~100°C 100~125°C 125~150°C 600 MHz 860 870 890 910 930 940 960 980
500 MHz 780 780 790 800 810 820 830 840
400 MHz 700 700 700 710 710 710 720 720
300 MHz 630 630 620 620 610 610 600 600
200 MHz 570 560 550 530 520 510 500 500
Table 4.3 Logical V
DD look-up table for CTAPM. Each VID number corresponds to an independent VDD level, respectively.VID -40~-25°C -25~0°C 0~25°C 25~50°C 50~75°C 75~100°C 100~125°C 125~150°C 600 MHz 100100 100101 100111 101001 101011 101100 101110 110000
500 MHz 011100 011100 011101 011110 011111 100000 100001 100010
400 MHz 010100 010100 010100 010101 010101 010101 010110 010110
300 MHz 001101 001101 001100 001100 001011 001011 001010 001010
200 MHz 000111 000110 000101 000011 000010 000001 000000 000000
In our initial plan, DVS is used in the large steps of temperature to meet performance requirements, and FBB will be applied in the small steps of temperature to adjust frequency changes due to temperature variation. There should be no need to raise a margin of the supply voltage in high VDD and middle VDD zones because of performance coherence needs. However, the effect of FBB is surprisingly too small to compensate frequency decrease based on used TSMC 100nm technology, which will be described later in Section 4.4. Consequently, DVS is used alone to solve the problem in this situation, raising a margin of the supply voltage to ensure performance coherence.
4.3 RBB Analysis
In this section, we present experimental results about reverse body bias technique. Owing to previous works about this technique mainly focusing on the effect of leakage suppression, we put our emphasis on the apply methods instead. As shown in Figure 4.9, although converging quickly, applying reverse body bias on PMOS is the least effective since the leakage current of OFF-state PMOS devices is much smaller than that of NMOS devices. Applying reverse body bias on both PMOS and NMOS leads to the largest leakage saving. However, applying reverse body bias on NMOS only is efficient due to lower power overhead of the charge-pump circuit, which is needed to provide body bias voltage.
Figure 4.10 is the case co-working with power gating technique. Because the magnitude of leakage current of the circuit is decided by the OFF-state NMOS sleep transistor in this situation, applying reverse body bias on this sleep transistor only is as effective as on all PMOS and NMOS devices. In addition, applying reverse body bias on NMOS sleep transistor only introduces the least loading and power overhead of charge-pump circuits.
What is worth to mention is that the magnitude of reverse body bias voltage has its limit; in fact, applying too large reverse body bias will bring about obvious second order effects (SCE), such as gate induced drain lowering (GIDL). Previous research indicates (see Figure 4.11) that beyond a certain optimal RBB voltage, which is about 0.3X VDD for 0.13um technology, the transistor OFF-state current starts to increase due to increased GIDL leakage [19]. We follow the reference to choose 0.3V as optical reverse body bias voltage to avoid the GIDL effect because the lack of BSIM4 model.