Besides, the type of technology process has great impact for architecture decisions. Modern nano-scale CMOS technology platforms typically provide up to six different types of logic core devices with different oxide thickness and threshold voltages for high performance, low leakage power, and low operating power requirements [paper and TSMC]. The effect of body bias is just restricted by oxide thickness and threshold voltages. Although not useful in our simulations based on TSMC 100nm CMOS technology, FBB is more powerful for devices with thicker oxides and larger threshold voltages [31]. On the contrary, RBB is useful for devices with thicker oxides and low threshold voltages. Namely, FBB is applicable for low power technologies while RBB is suitable for high speed technologies.
Therefore, for simplicity we give up FBB in our CTAPM system based on used technology. However, if the target technology changes and FBB enables enough performance gain through the same analysis flow, then it is still a solution to ensure performance coherence or compensate process variation in other power management designs. RBB also has the possibility to not be adopted for low leakage technology since threshold voltages are larger to reduce its effect. The full version of CTAPM system has been proposed in Chapter 3, Figure 4.19 now shows an example of simplified version of CTAPM system, which only uses DVS to adjudge performance in the active mode and power gating to suppress leakage power in the standby mode, but skip body bias for simplicity. The analysis flow is still the same for different technologies, while the selection of low-power techniques will be case by case.
Figure 4.19 Simplified version of the CTAPM unit architecture. DVS,
clock gating and power gating still remain to maintain the functionality, whereas charge-pump circuits for body bias are removed.4.6 Summary
Utilizing power gating technique will reduce leakage power from 2.3uW to 12.66nW for our test vehicle, and combining power gating with 0.3V reverse body bias can further reduce leakage power to 7.2nW at room temperature. More than 90%
leakage saving can be achieved applying these techniques. However, because the lack of BSIM4 model, we can not obtain the optimized RBB values at different temperatures for the used technology.
Beside power control mechanism, we utilize DVS on the temperature axis to meet performance requirements. The experimental results show that the proposed CTAPM architecture has potential to reduce more than 70% of dynamic power dissipation in regular CMOS systems and ensure performance coherence at the same time. Nevertheless, forward body bias is not powerful as we expected based on used technology. Performance gain it provided is hard to compensate frequency loss when the temperature gets higher, especially at high supply voltage level.
Finally, design trade-offs between different techniques and technologies are discussed in this chapter. The type of sleep transistors has the influence on both power gating and reverse body bias. Besides, FBB may be useful in low power technologies while RBB is powerful in high speed technologies. The proposed full-version CTAPM architecture can be modified or simplified while maintaining the same functionality.
Chapter 5 Conclusion
5.1 Conclusion
Power dissipation in modern VLSI designs has become the most critical issue in System-on-Chip (SoC) era. Modern SoC integrations and mobile systems have emphasized low power techniques due to shortage of battery life. Besides, thermal impact is another reason to address the importance of power management because of high costs of packaging and cooling requirements for reliability.
In this thesis, a block-level optimization of comprehensive thermal-aware power management (CTAPM) is presented. The proposed CTAPM system adopts several circuit-level low power techniques to take care of both dynamic power and leakage power consumption in power phase, and deal with performance coherence between functional blocks in thermal phase as well. Dynamic voltage scaling (DVS) is utilized on both performance and temperature axis to reduce dynamic power and ensure all voltages islands are synchronous in the active mode. Clock gating is applied to reduce unnecessary clock switching power in the standby mode. Power gating and reverse body bias is aimed at leakage power suppression. However, forward body bias is not powerful to use.
Basic concepts including architecture design, control state machine, and look-up table design are also introduced after the overview of power source categories and these low power techniques. Through proposed analysis flow and test vehicle, the experimental results show that the proposed CTAPM architecture has potential to reduce more than 70% of dynamic and 90% of static power dissipation in regular CMOS systems. It also brings a significant improvement in system stability. The results are based on TSMC 100nm technology. Last but not least, the analysis flow is the same for different technologies, while the selection of low-power techniques can be case by case.
5.2 Future Works
Although transient analysis is not covered in this thesis, it is important for hardware or software scheduling to place the CTAPM into a real SoC system.
Transition time and power need to be studied for each adopted low power technology.
For example, if using power gating saves 10uW of leakage power in the standby mode, but it consumes extra 20uW transition power to close sleep transistors, then the system should keep sleep transistors OFF for at least two seconds to gain net power reduction. For another example, if it needs 10ms to change the supply voltage to different level, then the system has to be stopped for the same interval during the transition. Such transient information can be known by simulations of peripheral circuits or direct physical measurements. As it should be, peripheral circuits, such as DC-DC converters for DVS, charge-pump circuits for body bias, and thermal sensors for software feedback, are also future works to realize the CTAPM system. Moreover, since the analysis flow is compatible, a standardized test key for individual optimization of chips can be developed in the future.
Noise margin consideration is another important issue for future researchers.
The ideally optimized VDD look-up tables may not suitable for some noise-sensitive circuits, since the supply voltage may be scaled down a lot to destroy noise margins.
Besides, sleep transistors acting as minor power-rail resistance contribute virtual supply noise in normal operation. These drawbacks should be examined to maintain system stability.
Finally, the cell-based design flow may have to be modified to implement these low power techniques. However, it is not an issue for full-custom design. Since the hardware-language coding can’t generate sleep transistors for power gating, it should be done by either CAD tool support during the place-and-route (P&R) stage or post-layout custom modification. Besides, substrate/well contacts of original standard cells must be removed and re-create properly to isolate the body of transistors for body bias technique [32]. Voltage separation also needs to be done to apply DVS individually for voltage islands [33]. These back-end design processes have to be rearranged into the conventional cell-based design flow.
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