Chapter 5 Conclusion and Future Work
5.2 Future Work
The development and characterization of NW-TFTs with PRTA and furnace annealing
MILC channels have been studied in this thesis. To further enhance the device performance,
several propositions are suggested for future work.
1. Through the post-treatments like high temperature annealing and hydrogenation
plasma passivation, further improvement in electrical performance is expected by
enlarging the grain size and eliminating defects in the MILC film.
2. Several reports have revealed that the growth rate of MILC can be enhanced by
incorporation of boron into a-Si channel (i.e., dopant effect of MILC) [63]. For
long-channel NW-TFT devices, the region of laterally-grown cryststalline grain in the
NW through additional BF2+ implantation.
3. Both MILC and SPC techniques have been studied in fabricating NW-TFTs. Another
interesting approach in the preparation of LTPS film, excimer laser annealing (ELA),
can also be explored to fabricate devices for comparisons.
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Table 1-1 The comparisons among SPC, ELA, and MILC.
MILC
SPC ELA
Conventional PRTA
Temperature
High Low Medium Medium/HighTime
Long Short Medium ShortGrain size
Small Medium Large Large/MediumCost
Low High Low LowThroughput
Batch Single Batch SingleIssue
Many defects Expensive Metal contaminationTable 3-1 Key electrical parameters of NW-TFTs with SSW configuration by PRTA MILC.
L = 0.6 um L = 1 um L = 1.5 um L = 5 um
Vth (V) 1.74 2.10 2.21 4.74
S.S. (V/dec) 0.43 0.46 0.61 0.93
μFE (cm2/V-s) 104.28 83.37 96.24 52.25
Ion/Ioff (A/A) 7.70×105 7.70×105 3.52×105 3.34×105
Nt (cm-2) 9.39×1011 1.06×1012 1.09×1012 2.14×1012
＊ All parameters were extracted at VD = 0.5 V except for the off-state current, Ioff , and on/off current ratio, Ion/Ioff , which were extracted at VD = 3 V.
Table 4-1 Stress Measurements of LTO and Nitride films deposited on a-Si layer.
a-si (a)
Mask oxide a-si
(b)
a-si Nitride Mask oxide
(c)
(a) a-Si
(b) a-Si / oxide 1000A
(c)
a-Si /oxide1000A / Nitride 1000A
Radius (m) -95.573 -91.018 -49.561
Stress (MPa) -7.11E01 -6.13E02
＊ “ - (negative) symbol represents compressive stress”
Table 4-2 Major parameters for NW-TFTs by three different crystallization approaches.
PRTA (MILC)
FU (MILC)
SPC (FU)
V
th(V)
1.74 2.45 4.61S.S. (V/dec)
0.43 0.51 0.68μ
FE(cm
2/V-s)
104.28 88.94 15.98I
on/I
off(A/A)
7.70×105 4.80×105 6.01×105N
t(cm
-2)
9.39×1011 1.12×1012 1.70×1012＊ The channel length of NW-TFTs is 0.6um. All parameters were extracted at VD = 0.5 V except for the on/off current ratio, Ion/Ioff , which was extracted at VD = 3 V. Ioff is defined as the minimum drain current for convenience.
Fig. 1-1 Schematic illustration of the free energy of a- and c-states.
(a)
(b)
Fig. 1-2 (a) Equilibrium molar free-energy diagram for NiSi2 in contact with a-Si and c-Si.
(b) Schematic representation of the proposed NiSi2 and growth of c-Si.
1
2
3
4
Fig. 2-1 Key device-fabrication flow.
(a)
Width Gate
Gate Oxide Thickness
(b)
Fig.2-2 (a) Top view of NW-TFTs and (b) the definition of poly-Si nanowire channel.
Fig. 2-3 TEM images of NW-TFT without Nitride-capping layer.
Nitride
Fig. 2-4 TEM images of NW-TFT with Nitride-capping layer.
Time (seconds)
0 10 20 30 40 50 60
Temperature of RTA processor (o C)
300 One cycle of PRTA
actual ramp = ~ 70 oC/sec
(a)
Annealing Time (seconds)
0 50 100 150 200 250 300 350 400
Temperature of RTA processor (o C)
0
——— Temperature of RTA processor - - - Status of heating lamp
Off On
(b)
Fig. 3-1 (a) Heating temperature during one cycle of PRTA. (b) On/Off status of the heating lamp and measured temperature in RTA processor.
(a)
Total Heating Time (minutes)
0 2 4 6 8 10 12
Length of The MILC Region (um)
0 5 10 15 20 25 30
PRTA with Peak temperature (On / Off time of the PRTA heating lamp is 10 seconds/30 seconds )
Length 90 um
725oC 700oC 690oC 675oC 650oC
(b)
Fig. 3-2 Growth of MILC region using PRTA with different annealing peak temperature (On/Off time of PRTA per cycle is 10/30 sec ).
Fig. 3-3 Illustration of competing crystallization mechanisms between MILC and background SPC.
1/kT (eV-1)
12.0 12.1 12.2 12.3 12.4 12.5 12.6
ln R (Growth Velocity (nm/min) )
7.0
690 680 670 660 650
Temperature ( oC )
PRTA MILC
(a)
1/kT (eV-1)
14.0 14.2 14.4 14.6 14.8 15.0 15.2
ln R (Growth Velocity (nm/min) )
1.5
Fig. 3-4 Activation energies of MILC for PRTA and furnace annealing.
(a)
(b)
Fig. 3-5 Schematic device structures for two kinds of MILC seeding window arrangement, including (a)ASW and (b) SSW configurations.
MILC window
Source Drain
(a) 20 cycles
MILC window
Source Drain
(b) 40 cycles
MILC window
Source Drain
(c) 60 cycles
Fig. 3-6 Optical microscopic images of the growth of MILC region with increasing pulsed cycles.
Gate Voltage (V)
PRTA 650oC_10sec_60cycles ASW configuration
PRTA 650oC_10sec_60cycles SSW configuration
W = 45nm GW = 1um VD = 0.5V
(b)
Fig. 3-7 Transfer characteristics of (a) ASW and (b) SSW NW-TFTs with different channel length.
Gate Voltage (V)
PRTA 650oC_10sec_60cycles W/L = 45nm / 1um
PRTA _650oC_10sec_60cycles W/L = 45nm / 1um
GW = 1um
VG = 4V~8V, Step = 1V
(b)
Fig. 3-8 (a) Transfer and (b) output characteristics of NW-TFT by PRTA MILC.
Gate Voltage (V)
w/ Nitride capping layer W / L = 45nm / 1um
w/ Nitride capping layer W / L = 45nm / 1.5um GW = 1um
VD = 0.5V
(b) Channel Length = 1.5 um
Fig. 3-9 Transfer characteristics of NW-TFTs with nitride capping layer.
Gate Voltage (V)
PRTA MILC 10sec_60cycles w/o Nitride capping layer W/L = 45nm / 1um
PRTA MILC 10sec_60cycles w/o Nitride capping layer W/L = 45nm / 1.5um GW = 1um
VD = 0.5V
(b) Channel Length = 1.5 um
Fig. 3-10 Transfer characteristics of NW-TFTs without nitride capping layer.
Gate Voltage (V)
Fig. 3-11 Transfer characteristics of NW-TFTs fabricated by PRTA anneal at 675°C.
Gate-to-Drain Overlap Region
Drain Path 2
Gate Oxide
Fig. 3-12 A schematic of possible flow paths for off-state leakage currents.
Gate Channel Path 1
Drain/Channel Junction
(a) Low electric field:
(b) Medium electric field:
(c) High electric field:
Fig. 3-13 Leakage mechanism in the gate-to-drain overlap region. (a) Thermal emission.
(b) Thermionic field emission. (c) Band-to-band tunneling.
Gate Voltage (V)
PRTA _650oC_10sec_60cycles ASW configuration
PRTA _650oC_10sec_60cycles SSW configuration
W/L = 45nm / 1um GW = 1um VD = 0.5, 3 V
(b)
Fig. 3-14 Transfer characteristics of NW-TFT with (a) ASW and (b) SSW configuration measured under both forward and reverse modes of operation.
Gate Voltage (V)
w/ Nitride capping layer w/o Nitride capping layer N-type NW-TFT
PRTA MILC
650oC_10sec_60cycles W/L = 45nm / 1um
w/ Nitride capping layer w/o Nitride capping layer N-type NW-TFT
PRTA MILC
650oC_10sec_60cycles W/L = 45nm / 2um GW = 1um VD = 0.5V
(b) Channel Length = 2 um
Fig. 4-1 Transfer characteristics of NW-TFTs with or without Nitride capping layer.
S.S. (V/dec)
w/ Nitride capping layer w/o Nitride capping layer
N-type NW-TFT PRTA MILC
650oC_10sec_60cycles W/L = 45nm / 1um
w/ Nitride capping layer w/o Nitride capping layer
N-type NW-TFT PRTA MILC
650oC_10sec_60cycles W/L = 45nm / 1um GW = 1um VD = 0.5V N = 30
(b)
Fig. 4-2 Cumulative probability of (a) subthreshold swing and (b) threshold voltage of NW-TFTs with or without nitride capping layer.
Gate Voltage (V)
Fig. 4-3 (a)Transfer and (b)output characteristics of NW-TFTs with ASW configuration fabricated by furnace MILC.
Gate Voltage (V)
Fig. 4-3 (c)Transfer and (d)output characteristics of NW-TFTs with SSW configuration fabricated by furnace MILC.
Gate Voltage (V)
Fig. 4-4 (a)Transfer and (b)output characteristics of NW-TFTs fabricated by furnace SPC.
Gate Voltage (V)
Fig. 4-5 Transfer characteristics of NW-TFTs fabricated by MILC (both PRTA and furnace anneal) and SPC (furnace anneal).
1/VG (V-1)
0.05 0.10 0.15 0.20 0.25 0.30
ln (I D/V G) (AV-1 )
-24 -22 -20 -18 -16 -14
PRTA MILC FU MILC FU SPC N-type NW-TFT
Nt = 9.39 x1011 cm-2
Nt = 1.12 x1012 cm-2
Nt =1.7 x1012 cm-2
Fig. 4-6 Plot of ln(ID/VG) versus (1/VG) for three different crystallization approaches.
(a) 2 channels
(b) 6 channels
(c) 10 channels
Fig. 4-7 Schematic illustrations of ASW and SSW NW-TFT with multiple channels.
Gate Voltage (V)
(a) ASW configuration
Gate Voltage (V)
(b) SSW configuration
Fig. 4-8 Transfer characteristics of NW-TFTs with multiple channels fabricated by furnace MILC.
Gate Voltage (V)
Fig. 4-9 Transfer characteristics of NW-TFTs with multiple channels fabricated by PRTA MILC.
multiple channels
multiple channels
Fig 4-10 On-current as a function of the multiple channels for NW-TFT devices crystallized by MILC : (a) furnace anneal (ASW configuration), (b) furnace anneal (SSW configuration), (c) PRTA (SSW configuration), and (d) crystallized by furnace SPC. The number of devices characterized for each condition is 20.
multiple channels
2-channels 6-channels 10-channels
On-Current (μA)
-1 0 1 2 3 4 5
PRTA SSW FU SSW FU ASW N-type NW-TFT MILC
W/L = 45nm / 1um GW = 1um
VD = 0.5V, VG = 10V
Fig. 4-11 Comparisons of on-current for PRTA and furnace MILC NW-TFTs with multiple channels.
S.S. (V/dec)
Fig. 4-12 Cumulative probability of (a) subthreshold swing and (b) threshold voltage of NW-TFTs fabricated by three different approaches. (i.e., MILC by either PRTA or furnace anneal, and SPC by furnace anneal)
作者簡歷
姓名：林漢仲 Han-Chung Lin 性別：男
生日：西元 1984 年 2 月 24 日 籍貫：台北市
住址：台北市內湖區環山路二段 93 號 2 樓
學歷：國立交通大學 電子研究所 2006 年 9 月~ 2008 年 6 月 國立臺灣海洋大學 電機工程學系 2002 年 9 月~ 2006 年 6 月 台北市立內湖高級中學 1999 年 9 月~ 2002 年 6 月 台北市立麗山國中 1996 年 9 月~ 1999 年 6 月 台北市立麗山國小 1990 年 9 月~ 1996 年 6 月
論文題目：
低溫多晶矽技術對多晶矽奈米線薄膜電晶體通道結晶特性影響之研究 A Study of Characteristics of Poly-Si Nanowire Thin-Film Transistors Fabricated by LTPS Technique