Chapter 2 Device Fabrication and Measurement
2.2 Measurement Setup and Electrical Characterization
Electrical characterization on the NWFETs was performed using an HP 4156
semiconductor parameter analyzer system. In all measurements, the temperature was
controlled and fixed at a stable value by temperature-regulated hot chuck. From the
measured ID-VG curve at VG = 0.5V, key parameters including threshold voltage (Vth),
subthreshold swing (SS), and field-effect mobility (μFE) were extracted based on the
following relations.
In this study, a constant-current method was employed to determine the threshold voltage,
in other words, the threshold voltage is defined as the gate voltage as the drain current ID
reaches the value of (W/L)×100 nA, or.
nA
L I W V
Vth = G@ D = ×100 (2-1),
where W, L are the channel width and length, respectively.
The subthreshold swing could be calculated from the subthrshold current in the weak
inversion region by
Finally, the filed-effect mobility (μFE) is determined by using the following equation:
where gm is the maximum transconductance and Cox is the gate oxide capacitance per unit
area.
Chapter 3
NW-TFTs Fabricated by Pulsed RTA MILC
3.1 Material Analysis of PRTA Grain Growth
For the material analysis, a 5 nm-thick Ni seeding layer was deposited onto a selected
a-Si region which is called seeding window with dimension of 90×90 μm2.
Recrystallization of the amorphous silicon was subsequently performed to observe the
PRTA MILC characteristics, where all samples were annealed in a RTA processor (AG heat
pulse 610 system) with N2 ambient for 60 cycles with each cycle consisting of 10 seconds
on-period and 30 seconds off-period. Various annealing temperatures, i.e., 650 °C, 675 °C,
690 °C, 700 °C, or 725 °C, were set within every operational cycle. Figure 3-1 illustrates
the heating pattern of the applied temperature which is measured in the chamber during the
annealing process. However, MILC growth rate during cooling interval at 400 °C is less
than 0.1μm/h [48] and can be ignored.
The length of the MILC region formed by PRTA in different annealing conditions is
shown in Fig. 3-2. The value was measured by an optical microscope and was defined as
the length from the center of seeding window edge to the MILC front. Since SPC also
occurs throughout the entire a-Si film during the annealing process, it was observed that the
growth rate of the MILC region gradually slows down at higher temperature. It can be
explained by competing crystallization mechanisms between MILC and background solid
phase crystallization. While SPC takes place in the film, the laterally-grown cryststalline
grain is blocked and no further lateral growth is observed. At the onset of the crystallization,
an incubation time is required for the SPC of a-Si to take place. At higher annealing
temperature, the SPC takes place earlier and becomes more dominant than MILC process.
Conversely, the effect of SPC diminishes at low annealing temperature. A distinctive
illustration is depicted in Fig. 3-3. Moreover, the lateral saturation region and film
crystallinity are dependent on the temperature of MILC annealing process. To obtain large
grain size with high quality of film crystallinity, it is necessary to retard the background
SPC process. By properly adjusting the annealing period or the peak temperature
conditions, the PRTA cycle can be tuned to be shorter than the transient time of the
background SPC, the undesirable effect of SPC can thus be completely suppressed during
MILC process [46].
3.2 Activation Energy Extraction
In order to gain a deeper insight into the kinetics of MILC by rapid thermal and furnace
anneal, the activation energy for a-Si to become poly-Si is obtained by thermodynamic
Arrhenius plot [49], as defined by
0 exp( ) kT A E
R= ⋅ − a (3-1),
where R is the recrystallization growth rate, A0 is the coefficient constant of growth rate, Ea
is the activation energy, k is the Boltzman constant, and T is the absolute temperature. The
equation can also be expressed as
ln( ) ln( 0) ( ) kT A E
R = + − a (3-2).
The extracted parameters, R and Ea, are related to the different definitions used (some
authors include the incubation time to be part of activation energy calculation), the
apparatuses of annealing, and the preparation of specimens [50]. In this work, the measured
initial rates of MILC crystallization, as a function of annealing temperature are shown in
Fig. 3-4. The activation energy of two dissimilar methods, deduced from the slopes, was
found to be 1.55 eV for PRTA and 1.76 eV for furnace annealing. The lower activation
energy for RTA is believed to be due to photon assisted or free energy released by sudden
heating during RTA [51]. Moreover, the method of PRTA crystallization proceeds much
faster than conventional furnace annealing during MILC process. For instance, the sample
of furnace annealing was prepared at 525 °C for 21 hr to form MILC length of about 32 μm,
whereas the PRTA sample was prepared at 650 °C with 60 cycles of pulses (total heating
time of 10 minutes) to form MILC length of 12.9 μm. Despites the fact that MILC length of
PRTA is shorter than that of furnace annealing, the recrystallized growth rate per unit time
is faster than that of the conventional furnace anneal. This improvement of growth rate for
PRTA MILC is also exploited to reduce the long process time in recrystallization.
3.3 Fundamental Characteristics of PRTA NW-TFTs
The operational principles of the novel NW-TFTs are similar to those of the conventional
TFTs. The n+ poly-Si gate is used to modulate the channel potential, consequently
controlling the switching behavior of the devices. Based on one-sided or two-sided seeding
windows for MILC, the NW-TFTs are categorized as metal-induced unilateral
crystallization (MIUC) or metal-induced bilateral crystallization (MIBC). The schematic
device structures of two kinds of MILC seeding windows arrangement are shown in Fig.
3-5, including (a) asymmetric seeding window (ASW), and (b) symmetric seeding window
(SSW). Figure 3-6 presents the growth of MILC region with increasing pulsed cycles, as
observed by optical microscope.
Figure 3-7 shows the transfer characteristics of n-channel NW-TFT devices with ASW
and SSW configurations. The samples were prepared by PRTA anneal at 650 °C peak
temperature with 60 cycles of pulses (total heating time of 10 min) to form MILC
crystallized channel. The performance of ASW devices with different channel lengths are
presented in Fig. 3-7 (a). According to previous material analysis in Section 3.1, MILC
process should ideally proceed continuously in the channel during the 60 cycles of PRTA
annealing. However, SPC seems to take place earlier than expected. We may exploit the
electrical characteristics to gain insights into the crystalline quality of polysilicon channel.
The result illustrates that the NW crystallinity is dependent on the channel length, i.e., the
NW located near the Ni seeding window depicts superior crystallinity to that away from the
window. It is believed that the heterogeneous nucleation of SPC process, rather than the
Ni-induced lateral recrystallization, dominates the channel recrystallization process in the
area away from the seeding window. Considerable grain boundaries and microstructural
defects in the NW would inevitably degrade the device performance. In addition, along
SiO2 film steps preferential nucleation area during annealing was observed [52]. Since NW
channels are just located at the steps of gate oxide, controlling RTA heating temperature is
supposed to be more significant during MILC treatment. However, for PRTA MILC
technique, NW-TFT devices with SSW has demonstrated that better device performance
can be achieved as shown in Fig. 3-7 (b) and Fig. 3-8, especially in terms of higher drain
current and steeper subthreshold slope, compared with the asymmetric counterparts. It can
be attributed that SSW cases may have more opportunities to develop better NW channel
crystallinity because seeding windows on both the source and drain terminals would
proceed to convert a-Si into polycrystalline silicon simultaneously. The probability of
undesired, fine grains by SPC can be reduced, and the needle-like grain with crystallization
direction along the channel is formed. As a result, the number of barrier at GBs where
conduction electrons must overcome is also reduced as well. The major device parameters
of different channel lengths are extracted and summarized in Table 3-1. Therefore, the
following discussion will focus on NW-TFT devices with SSW configuration. Also noted
that the off-state current of SSW case is rather high due to more Ni residual giving rise to
metal contamination. Further details regarding off-state leakage current mechanisms will be
discussed later.
3.4 Effects of Pulsed RTA Annealing Conditions
3.4.1 Effects of Pulsed RTA Annealing Temperature
In order to obtain ideal crystallinity of NW channels, selecting a precise heating
temperature plays an important role on PRTA MILC fabrication. The MILC annealing
conditions affect not only the recrystallization growth rate but also polycrystalline silicon
grain size, grain boundaries, and even metallic species distribution inside the film. Figure
3-9 compares several MILC annealing splits of n-channel NW-TFTs with an additional
nitride capping layer on the channel. The samples were prepared with different peak PRTA
annealing temperature for 60 cycles. The results show that the three MILC splits (i.e.,
625°C, 650°C, and 675°C) almost have identical transfer characteristics when the length of
overall channel crystallinity when the channel length is short. When the channel length
increases, the split with polycrystalline silicon formed at 650 °C has better characteristics
in term of steeper subthreshold slope, compared with the other splits of 625 °C and 675 °C.
At higher annealing temperature such as 675 °C, the SPC mechanism of the a-Si layer takes
place quickly and clogs MILC grain growth. Thus, the resultant polycrystalline silicon NW
channel is believed to contain microstructural defects with random crystalline gain
orientation. Besides, the large number of grain boundaries existing in the channel would
degrade the device performance. Another reason of device degradation may relate to Ni
concentration. Higher annealing temperature leads to higher Ni concentration in the MILC
region, grain size decreases due to many NiSi2 crystallites formation during MILC
treatment. This phenomenon, albeit sensitive to annealing temperature, is insensitive to the
annealing time [53]. On the other hand, a relatively low temperature is desirable to form
good-quality MILC polycrystalline channel with larger grain size and less grain boundaries.
However, the MILC of a-Si becomes slower with lower temperature. It will take more time
to achieve the same MILC growth region at lower temperature. The trade-off between the
MILC and SPC should therefore be carefully taken into consideration. Nevertheless,
NW-TFTs without nitride capping layer fabricated by similar MILC annealing conditions
depict similar trends, as shown in Fig. 3-10.
3.4.2 Effects of Pulsed RTA Annealing Time
In the above discussions, the device performance of different PRTA annealing
temperature depends on the channel length of NW-TFTs. For longer channel, the annealing
time is prolonged beyond the incubation time of SPC. Arranging proper annealing period
during each cycle is another approach to suppress SPC mechanism. The samples were
prepared by PRTA anneal periodically for 60 times with 5 seconds per period (i.e., total
heating time of 5 min). The peak temperature was set at 675 °C to make sure that the MILC
recrystallization region is longer than the channel length. The transfer characteristics are
shown in Fig. 3-11, together with those of the sample with the same processing conditions,
except the total heating time of 10 minutes. It can be seen that the device performance is
not improved by reducing the annealing time. It is assumed that MILC lateral-growth
crystallinity does not dominate the entire NW channel. It has been reported by R.B. Iverson
et al. that the incubation time of SPC is roughly 40 minutes in furnace anneal at 675 °C
[54]. While from our material analysis in Section 3.1, the incubation time in RTA anneal at
675°C in our case is about 11 minutes. This suggests that SPC mechanism takes place
earlier in NW channel during PRTA MILC treatment. Thus, PRTA MILC with higher
temperature annealing appears to speed up SPC mechanism and is unfavorable for
achieving good-quality grains.
3.5 Leakage Mechanisms
The major off-state currents of NW-TFT fabricated by MILC process are related to
several possible paths as depicted in Fig. 3-12. One is through the drain/channel junction
(path 1) and the other is through the gate-to-drain overlap region (path 2). The conduction
mechanisms in the two regions are strongly dependent on the strength of local field which
is determined by the gate and drain biases, referred to as the gate-induced drain leakage
(GIDL). The field-dependent conduction mechanisms are shown in Fig. 3-13. When |VGD|
is high, strong electric field would lead to trap-assisted (Fig.3-13(b)) or band-to-band
tunneling (Fig. 3-13(c)). Major conduction path can be identified by investigating the
dependence of leakage of devices with same channel on the gate-to-drain overlap area [55]:
It is mainly through path 2 as the dependence is linearly proportional to the gate-to-drain
overlap area, and through path 1 as the leakage is independence of the gate-to-drain overlap
area. Typical poly-Si NW devices fabricated in our work follow the path 2 [56]. This is
mainly attributed to the low dopant concentration for the poly-Si layer near the oxide
interface and the relatively low density-of-state (DOS) of the poly-Si film so that the band
bending (related to the electric field) at interface of the poly-Si layer shown in Figs.3-13(b)
and (c) is easy to trigger. To address the issue, we’ve also proposed and demonstrated two
ways to suppress the leakage: (1) Use of a hardmask dielectric (e.g., nitride) on top of the
side-gate to reduce the field strength at the channel interface [57]. (2) Promotion of the
dopant concentration in the region of the poly-Si layer near the interface to hinder the
inversion of the drain region (Figs.3-13(b) and (c)) [58]. In one of our previous work, we
also found that, as a poly-SiGe layer is used to replace the poly-SiGe as the NW channel
and the S/D material, the dependence of leakage of devices with same channel is
independent of the gate-to-drain overlap area. This is ascribed to the DOS of the poly-Si
which is much larger than the poly-Si [59]. The high DOS in poly-SiGe would pin the
Fermi level and thus the band-bending is less likely to occur.
For MILC samples, one additional leakage mechanism is attributable to the
contamination of residual Ni. Ni-related species accumulated either at the inter- or
intra-grains may provide more trap states in the band gap of Si, resulting in trap-assisted
tunneling leakage current. Besides, the off-state current of NW-TFT with SSW devices is
more severe. Except the fronts of seeding Ni-silicide from the opposite sides may confront
each other causing metallic species left inside the channel, main reason is one of the
seeding windows located at the gate-to-drain overlap region. Many residual Ni-related
species trap in grain boundaries between the MIC and MILC region. Hence, either forward
or reverse operation modes were used; the leakage currents of SSW devices would be
identical and transfer characteristics are illustrated in Fig. 3-14. Here, the reverse mode of
operation represents the exchange of source and drain electrodes. An increase in leakage
can be seen if ASW devices operated under reverse mode, owing to the fact that the
seeding window is now located in the drain terminal instead of source terminal.
Chapter 4
NW-TFTs Fabricated Using Different Crystallization Strategy
4.1 The Effect of Stress on PRTA NW-TFTs
In this thesis, the effects of capping an additional 100 nm-thick PECVD Nitride film
over the 100 nm LTO layer prior to PRTA MILC treatment on the device characteristics are
studied. Figure 4-1 compares the transfer characteristics of NW-TFT devices with and
without the Nitride-capping layer. We can see that better subthreshold slope and higher
on-current are obtained with the Nitride capping. To study the effect of stress, a 100 nm
LTO and 100 nm Nitride films were deposited on a-Si layer and investigated by stress
measurement. The three layers were all blanket and stacked on a-Si wafer for the test
sample. The stress measurement was performed by probing the change in curvature before
and after the capping of the layer using light interference technique. It was found that a
compressive stress was introduced by nitride film. The measured parameters are listed in
Table 4-1. A compressive stress that exists during phase transformation from a-Si into
poly-Si is believed to be able to suppress the speed of solid phase crystallization owing to
the fact that elastic modulus of c-Si is lager than that of a-Si, and elastic strain does not
relax causing an increase of strain energy with phase transformation [60]. However, MILC
can still proceed under a compressive stress, since the lateral grain growth is determined by
the free energy difference of Ni atom at the NiSi2/a-Si or NiSi2/c-Si interface. Once the
effect of SPC during lateral grain growth is retarded, improved crystallinity of poly-Si with
less grain boundaries could be carried out during MILC process. The cumulative
probability of NW-TFTs with or without Nitride capping layer was measured and is shown
in Fig. 4-2. It can be seen that performance enhancement is indeed attained.
4.2 The Effect of Crystallization Approaches
4.2.1 Comparisons between Furnace and PRTA Annealing MILC
For comparison purpose, Fig. 4-3 shows the transfer and output characteristics of MILC
control samples annealed at 525 °C for 21 hr in a conventional furnace. Unlike the samples
fabricated by the PRTA MILC technique as discussed in Chapter 3, NW-TFTs with ASW
configuration exhibit superior device performance to that with SSW configuration. The
extracted field-mobility is 122.4cm2/V-sec for ASW case, which is higher than 88cm2/V-sec
of SSW case. This is interesting as two dissimilar MILC approaches to acquire
polycrystalline silicon from a-Si, one with higher temperature by short-time RTA anneal
and the other by furnace anneal with relatively low temperature but long processing time,
show different trends. The crystallinity of NW is verified to be associated with seeding
window arrangement, crystallization rate, annealing temperature, and annealing time. For
the devices with SSW configuration prepared by conventional MILC furnace anneal,
degraded on-state performance over the asymmetric case has been demonstrated to be
caused by trace amount of metallic species left inside the channel [61]. ASW case depicts
better electrical characteristics in terms of less grain boundaries and less metal
contamination in the channel region. Moreover, throughout the period of furnace annealing,
background SPC mechanism is also triggered as process time increases. When lateral
MILC grain growth is blocked by several small grains formed by SPC, the crystallinity of
NW is affected as well. On the other hand, since higher annealing temperature is exploited
for PRTA MILC technique, the undesired SPC mechanism occurs earlier than expected.
NW channels are crystallized simultaneously by symmetric seeding windows while better
polycrystalline silicon is obtained.
Figure 4-4 shows the transfer and output characteristics of SPC samples annealed at
600 °C for 24 hr in a conventional furnace. Transfer characteristics of MILC (by PRTA and
furnace anneal) and SPC (by furnace anneal) poly-Si TFT with NW channel are compared
in Fig. 4-5. As shown in the figures, two MILC approaches (with SSW configuration)
exhibit improved characteristics in terms of higher drain current, carrier mobility, and
reduced subthreshold slopes as compared with SPC devices. In addition, the trap density
(Nt) is extracted from the grain boundaries trapping model proposed by J. Levinson et al
[62], defined as
Where μ0 is a pre-exponential factor, q is the electric charge, Nt is the carrier trap-state
density per unit area, t is the channel thickness, and εs is the semiconductor permittivity. In
Fig. 4-6, the plots of ln(ID/VG) versus (1/VG) for three different approaches of
crystallization are shown, and trap density of each sample is extracted from the
corresponding slope. It can be found that the Nt of MILC devices is much smaller than that
of SPC device. This indicates that NW channel formed by MILC possesses better film
of SPC device. This indicates that NW channel formed by MILC possesses better film