Chapter 3 NW-TFTs Fabricated by Pulsed RTA MILC
3.5 Leakage Mechanisms
The major off-state currents of NW-TFT fabricated by MILC process are related to
several possible paths as depicted in Fig. 3-12. One is through the drain/channel junction
(path 1) and the other is through the gate-to-drain overlap region (path 2). The conduction
mechanisms in the two regions are strongly dependent on the strength of local field which
is determined by the gate and drain biases, referred to as the gate-induced drain leakage
(GIDL). The field-dependent conduction mechanisms are shown in Fig. 3-13. When |VGD|
is high, strong electric field would lead to trap-assisted (Fig.3-13(b)) or band-to-band
tunneling (Fig. 3-13(c)). Major conduction path can be identified by investigating the
dependence of leakage of devices with same channel on the gate-to-drain overlap area [55]:
It is mainly through path 2 as the dependence is linearly proportional to the gate-to-drain
overlap area, and through path 1 as the leakage is independence of the gate-to-drain overlap
area. Typical poly-Si NW devices fabricated in our work follow the path 2 [56]. This is
mainly attributed to the low dopant concentration for the poly-Si layer near the oxide
interface and the relatively low density-of-state (DOS) of the poly-Si film so that the band
bending (related to the electric field) at interface of the poly-Si layer shown in Figs.3-13(b)
and (c) is easy to trigger. To address the issue, we’ve also proposed and demonstrated two
ways to suppress the leakage: (1) Use of a hardmask dielectric (e.g., nitride) on top of the
side-gate to reduce the field strength at the channel interface [57]. (2) Promotion of the
dopant concentration in the region of the poly-Si layer near the interface to hinder the
inversion of the drain region (Figs.3-13(b) and (c)) [58]. In one of our previous work, we
also found that, as a poly-SiGe layer is used to replace the poly-SiGe as the NW channel
and the S/D material, the dependence of leakage of devices with same channel is
independent of the gate-to-drain overlap area. This is ascribed to the DOS of the poly-Si
which is much larger than the poly-Si [59]. The high DOS in poly-SiGe would pin the
Fermi level and thus the band-bending is less likely to occur.
For MILC samples, one additional leakage mechanism is attributable to the
contamination of residual Ni. Ni-related species accumulated either at the inter- or
intra-grains may provide more trap states in the band gap of Si, resulting in trap-assisted
tunneling leakage current. Besides, the off-state current of NW-TFT with SSW devices is
more severe. Except the fronts of seeding Ni-silicide from the opposite sides may confront
each other causing metallic species left inside the channel, main reason is one of the
seeding windows located at the gate-to-drain overlap region. Many residual Ni-related
species trap in grain boundaries between the MIC and MILC region. Hence, either forward
or reverse operation modes were used; the leakage currents of SSW devices would be
identical and transfer characteristics are illustrated in Fig. 3-14. Here, the reverse mode of
operation represents the exchange of source and drain electrodes. An increase in leakage
can be seen if ASW devices operated under reverse mode, owing to the fact that the
seeding window is now located in the drain terminal instead of source terminal.
Chapter 4
NW-TFTs Fabricated Using Different Crystallization Strategy
4.1 The Effect of Stress on PRTA NW-TFTs
In this thesis, the effects of capping an additional 100 nm-thick PECVD Nitride film
over the 100 nm LTO layer prior to PRTA MILC treatment on the device characteristics are
studied. Figure 4-1 compares the transfer characteristics of NW-TFT devices with and
without the Nitride-capping layer. We can see that better subthreshold slope and higher
on-current are obtained with the Nitride capping. To study the effect of stress, a 100 nm
LTO and 100 nm Nitride films were deposited on a-Si layer and investigated by stress
measurement. The three layers were all blanket and stacked on a-Si wafer for the test
sample. The stress measurement was performed by probing the change in curvature before
and after the capping of the layer using light interference technique. It was found that a
compressive stress was introduced by nitride film. The measured parameters are listed in
Table 4-1. A compressive stress that exists during phase transformation from a-Si into
poly-Si is believed to be able to suppress the speed of solid phase crystallization owing to
the fact that elastic modulus of c-Si is lager than that of a-Si, and elastic strain does not
relax causing an increase of strain energy with phase transformation [60]. However, MILC
can still proceed under a compressive stress, since the lateral grain growth is determined by
the free energy difference of Ni atom at the NiSi2/a-Si or NiSi2/c-Si interface. Once the
effect of SPC during lateral grain growth is retarded, improved crystallinity of poly-Si with
less grain boundaries could be carried out during MILC process. The cumulative
probability of NW-TFTs with or without Nitride capping layer was measured and is shown
in Fig. 4-2. It can be seen that performance enhancement is indeed attained.
4.2 The Effect of Crystallization Approaches
4.2.1 Comparisons between Furnace and PRTA Annealing MILC
For comparison purpose, Fig. 4-3 shows the transfer and output characteristics of MILC
control samples annealed at 525 °C for 21 hr in a conventional furnace. Unlike the samples
fabricated by the PRTA MILC technique as discussed in Chapter 3, NW-TFTs with ASW
configuration exhibit superior device performance to that with SSW configuration. The
extracted field-mobility is 122.4cm2/V-sec for ASW case, which is higher than 88cm2/V-sec
of SSW case. This is interesting as two dissimilar MILC approaches to acquire
polycrystalline silicon from a-Si, one with higher temperature by short-time RTA anneal
and the other by furnace anneal with relatively low temperature but long processing time,
show different trends. The crystallinity of NW is verified to be associated with seeding
window arrangement, crystallization rate, annealing temperature, and annealing time. For
the devices with SSW configuration prepared by conventional MILC furnace anneal,
degraded on-state performance over the asymmetric case has been demonstrated to be
caused by trace amount of metallic species left inside the channel [61]. ASW case depicts
better electrical characteristics in terms of less grain boundaries and less metal
contamination in the channel region. Moreover, throughout the period of furnace annealing,
background SPC mechanism is also triggered as process time increases. When lateral
MILC grain growth is blocked by several small grains formed by SPC, the crystallinity of
NW is affected as well. On the other hand, since higher annealing temperature is exploited
for PRTA MILC technique, the undesired SPC mechanism occurs earlier than expected.
NW channels are crystallized simultaneously by symmetric seeding windows while better
polycrystalline silicon is obtained.
Figure 4-4 shows the transfer and output characteristics of SPC samples annealed at
600 °C for 24 hr in a conventional furnace. Transfer characteristics of MILC (by PRTA and
furnace anneal) and SPC (by furnace anneal) poly-Si TFT with NW channel are compared
in Fig. 4-5. As shown in the figures, two MILC approaches (with SSW configuration)
exhibit improved characteristics in terms of higher drain current, carrier mobility, and
reduced subthreshold slopes as compared with SPC devices. In addition, the trap density
(Nt) is extracted from the grain boundaries trapping model proposed by J. Levinson et al
[62], defined as
Where μ0 is a pre-exponential factor, q is the electric charge, Nt is the carrier trap-state
density per unit area, t is the channel thickness, and εs is the semiconductor permittivity. In
Fig. 4-6, the plots of ln(ID/VG) versus (1/VG) for three different approaches of
crystallization are shown, and trap density of each sample is extracted from the
corresponding slope. It can be found that the Nt of MILC devices is much smaller than that
of SPC device. This indicates that NW channel formed by MILC possesses better film
crystallinity. Either furnace or PRTA MILC technique results in much fewer grain
boundaries and microstructural defects in the NW channel. However, rather high off-state
leakage caused by metal contamination is a foremost concern. Finally, the extracted
performance parameters are summarized in Table 4-2.
4.2.2 MILC NW-TFTs with Multiple Channels
Based on the devices structure, the drive current of NW-TFTs is much smaller than that
of conventional planar TFTs owing to its small effective conduction width which is in the
nano-scale dimension. Boosting the current driving ability can improve the circuit speed
and broaden the practical application of NW-TFTs. Fortunately, the NW channels are
formed simultaneously on the sidewall of poly-Si gate, so NW-TFTs with multiple channels
can be achieved simply by increasing the number of side gates, as depicted in Fig. 4-7.
Figures 4-8 and 4-9 demonstrate the transfer characteristics of NW-TFT with multiple
channels fabricated by furnace and PRTA MILC, respectively. Evidently, the on-current
increase is due to the current sum of all parallel NW channels. The driving ability, however,
is not exactly consistent with the number of multiple channels. Because the crystallinity of
each poly-Si NW is not ideally identical, the variation of transfer characteristics is observed,
as shown Fig. 4-10. When increasing the number of multiple channels, performance
fluctuation of NW-TFTs also becomes larger, as can be seen in Fig. 4-11. In addition, the
off-state leakage current is proportional to the number of channels as well. This is
reasonable since the effective gate-to-drain overlap regions are broadened with increasing
channel number.
4.3 The Fluctuation of NW-TFTs
As device size is scaled below deep-submicrometer regime, the fluctuation of devices
characteristics could be a critical issue for the device scaling. It may be caused by
manufacturing process or material-related factors. NW-TFT with MILC crystallized
channel depicts inherent fluctuation which contributes to device performance
non-uniformity. The distribution of metal-induced lateral grains and grain boundaries inside
the NW channel are plausible culprits. In MILC process, the crystallization proceeds
radially from the seeding window. Only lateral grain growth passes through the NW, so the
good quality of crystalline silicon can be achieved. Figure 4-12 compares the cumulative
probability of subthreshold swing and threshold voltage of NW-TFTs fabricated by three
different approaches (i.e., MILC by either PRTA or furnace anneal, and SPC by furnace
anneal). Since SPC nucleates homogeneously within the amorphous film or
heterogeneously on interfaces, small grains are formed randomly in the NW. NW-TFTs by
SPC approach shows the narrowest variation of electrical characteristics among the splits in
Fig. 4-12 which is acceptable as the channel film consists of a large number of small grains.
On the other hand, NW channel crystallized by MILC process in furnace depicts apparently
larger device fluctuation over that by PRTA. As discussed in Chapter 3, the activation
energy of MILC by furnace anneal is higher than that by PRTA, which means that
lateral-crystallization process in furnace is more sensitive to anneal temperature. Light
variation of processing temperature may bring about abnormal MILC growth region, so the
fluctuations of MILC by furnace anneal should be taken into consideration. On the other
hand, the activation energy for PRTA MILC is lower which implies less insensitivity to
annealing temperature. This leads to a smaller fluctuation observed in Fig. 4-12 as
compared with the MILC samples prepared by furnace. Moreover, a fast crystallization rate
by using PRTA MILC is believed to be capable of eliminating the fluctuation of NW-TFT
device performance, since the annealing time in crystallizing is substantially reduced in
contrast to MILC by furnace-anneal. Therefore, MILC process fabricated by PRTA
technique is promising as it not only reduces process time in crystallization which is
suitable for mass-production, but also achieves better uniformity in device characteristics.
Chapter 5
Conclusions and Future Work
5.1 Conclusions
In this thesis, a novel MILC technique using pulsed-RTA to crystallize NW channel is
studied. Our results indicate that PRTA MILC has a faster recrystallized growth rate than
that of conventional furnace anneal owing to higher crystallization temperature and lower
activation energy. The effects of PRTA annealing condition were also investigated as well.
The crystallinity of NW is explained by competing crystallization mechanisms between
MILC and SPC. Specifically, undesired SPC mechanism of the a-Si layer takes place
quickly and clogs MILC grain growth at higher annealing temperature. A lower
temperature is preferred to form good-quality of laterally-grown cryststalline grain,
however, the MILC of a-Si becomes slower with lower annealing temperature. The
trade-off between the MILC and SPC should therefore be carefully taken into
consideration.
The effect of additional stress on the NW channel is studied to improve MILC device
characteristics because it is capable of suppressing the speed of background solid phase
crystallization. We have also fabricated and characterized devices with multiple NW
channels. Our results show that the performance variation of NW-TFTs becomes larger as
the channel number increases. Moreover, the NW channels crystallized by MILC process in
furnace depict apparently wider device fluctuation than those by PRTA. Abnormal MILC
growth region may result in crystallinity difference in each poly-Si NW. MILC process
fabricated by PRTA technique, however, appears to be a promising approach as it not only
reduces process time in crystallizing which is suitable for mass-production, but also
achieves better uniformity in device characteristics.
5.2 Future Work
The development and characterization of NW-TFTs with PRTA and furnace annealing
MILC channels have been studied in this thesis. To further enhance the device performance,
several propositions are suggested for future work.
1. Through the post-treatments like high temperature annealing and hydrogenation
plasma passivation, further improvement in electrical performance is expected by
enlarging the grain size and eliminating defects in the MILC film.
2. Several reports have revealed that the growth rate of MILC can be enhanced by
incorporation of boron into a-Si channel (i.e., dopant effect of MILC) [63]. For
long-channel NW-TFT devices, the region of laterally-grown cryststalline grain in the
NW through additional BF2+ implantation.
3. Both MILC and SPC techniques have been studied in fabricating NW-TFTs. Another
interesting approach in the preparation of LTPS film, excimer laser annealing (ELA),
can also be explored to fabricate devices for comparisons.
References
[1] S. D. Brotherton, “Polycrystalline Silicon Thin Film Transistors,” Semicond. Sci.
Technol., vol. 10, pp. 721-738, 1995.
[2] A. G. Lewis, D. D. Lee and R. H. Bruce, “Polysilicon TFT Circuit Design and Performance,” IEEE J. Solid-State Circuits, vol. 27, pp. 1833-1842, 1992.
[3] A. Mimura, N. Konishi, K. Ono, J. I. Ohwada, Y. Hosokawa, Y. A. Ono, T. Suzuki, K.
Miyata and H. Kawakami, “High Performance Low-temperature Poly-Si n-channel TFT’s for LCD,” IEEE Trans. Electron Devices, vol. 36, pp. 351-359, 1989.
[4] S. W. Lee and S. K. Joo, “Low Temperature Poly-Si Thin-film Transistor Fabrication by Metal-induced Lateral Crystallization,” IEEE Electron Device Lett., vol. 17, pp.
160-162, 1996.
[5] T. Sameshima, M. Hara and S. Usui, “XeCl Excimer Laser Annealing Used to Fabricate Poly-Si TFT’s,” Jpn. J. Appl. Phys., vol. 28, pp. 1789-1793, 1989.
[6] G. Shi and J. H. Seinfeld, “Transient Kinetics of Nucleation and Crystallization: Part I.
Nucleation,” J. Mater. Res., vol. 6, pp. 2091-2096, 1991.
[7] G. Shi, J. H. Seinfeld, “Transient Kinetics of Nucleation and Crystallization: Part II.
Nucleation,” J. Mater. Res., vol. 6, pp. 2097-2102, 1991.
[8] Y. Masaki, P. G. LeComber and A. G. Fitzgerald, “Solid Phase Crystallization of Thin Films of Si Prepared by Plasma-enhanced Chemical Vapor Deposition,” J. Appl. Phys.
vol. 74, pp. 129-134, 1993.
[9] H. C. Cheng, F. S. Wang and C. Y. Huang, “Effects of NH3 Plasma Passivation on n-channel Polycrystalline Silicon Thin-film Transistors,” IEEE Trans. Electron Devices, vol. 44, pp. 64-68, 1997.
[10] I. W. Wu, A. G. Lewis, T. Y. Huang and A. Chiang, “Effects of Trap-state Density
Electron Device Lett., vol. 10, pp. 123-125, 1989.
[11] H. N. Chern, C. L. Lee and T. F. Lei, “The Effects of H2-O2-plasma Treatment on The Characteristics of Polysilicon Thin-film Transistors,” IEEE Trans. Electron Devices, vol. 40, pp. 2301-2306, 1993.
[12] U. Mitra, B. Rossi, and B. Khan, “Mechanism of Plasma Hydrogenation of Polysilicon Thin Film Transistors,” J. Electrochem. Soc., vol. 138, pp. 3420-3424, 1991.
[13] K. Shimizu, O. Sugiura and M. Matsumura, “High-mobility Poly-Si Thin-film Transistors Fabricated by a Novel Excimer Laser Crystallization Method,” IEEE Trans. Electron Devices, vol. 40, pp. 112-117, 1993.
[14] M. Yasushi and N. Takashi, “UV Pulsed Laser Annealing of Si+ Implanted Silicon Film and Low-temperature Super-thin Film Transistors,” Jpn. J. Appl. Phys., vol. 28, pp. 309-311, 1989.
[15] K. Mutsumi, I. Satoshi and S. Tatsuya, “Dependence of Polycrystalline Silicon Thin-film Transistor Characteristics on the Grain-boundary Location,” Appl. Phys., vol. 89, pp. 596-600, 2001.
[16] R. S. Sposili and J. S. Im, “Sequential Lateral Solidification of Thin Silicon Films on SiO2,” Appl. Phys. Lett., vol. 69, pp. 2864-2866, 1996.
[17] P. C. Wilt, B. D. Dijk, G. J. Bertens, R. Ishihara and C. I. Beenakker, “Formation of Location-controlled Crystalline Islands Using Substrate-embedded Seeds in Excimer-laser Crystallization of Silicon Films,” Appl. Phys. Lett., vol. 79, pp.
1819-1821, 2001.
[18] C. H. Oh, M. Ozawa and M. Matsumura, “A Novel Phase-Modulated Excimer-laser Crystallization Method of Silicon Thin Films,” Jpn. J. Appl. Phys., vol.37, pp.
492-495, 1998.
[19] A. Hara, M. Takei, F. Takeuchi, K. Suga, K. Yoshino, M. Chida, T. Kakehi, Y. Ebiko,
Y. Sano and N. Sasaki, “High Performance Low Temperature Polycrystalline Silicon Thin Film Transistors on Non-alkaline Glass Produced Using Diode Pumped Solid State Continuous Wave Laser Lateral Crystallization,” Jpn. J. Appl Phys., vol. 43, pp.
1269-1276, 2004.
[20] M. Tai, M. Hatano, S. Yamaguchi, T. Noda, S. K. Park, T. Shiba and M. Ohkura,
“Performance of Poly-Si TFTs Fabricated by SELAX,” IEEE Trans. Electron Devices, vol. 51, pp. 934-939, 2004.
[21] G. Radnoczi, A. Robertsson, H. T. Hentzell, S. F. Gong and M. A. Hasan, “Al Induced Crystallization of a-Si,” J. Appl. Phys., vol. 69, pp. 6394-6399, 1991.
[22] L. Hultman, A. Robertsson, H. T. Hentzell, I. Engström and P. A. Psaras,
“Crystallization of Amorphous Silicon During Thin-film Gold Reaction,” J. Appl.
Phys., vol. 62, pp. 3647-3655, 1987.
[23] S. F. Gong, H. T. Hentzell and A. E. Robertsson, “Initial Solid-state Reactions between Crystalline Sb and Amorphous Si Thin Films,” J. Appl. Phys., vol. 64, pp.
1457-1463, 1988.
[24] R. J. Nemanichi, R. T. Fulks, B. L. Stafford and H. A. Plas, “Initial reactions and Silicide Formation of Titanium on Silicon Studied by Raman Spectroscopy,” J. Vac.
Sci. Technol. A, vol. 3, pp. 938-941, 1985.
[25] S. W. Lee, Y. C. Jeon and S. Ki. Joo, “Pd Induced Lateral Crystallization of Amorphous Si Thin Films,” Appl. Phys. Lett., vol. 66, pp. 1671-1673, 1995.
[26] S. W. Lee and S. K. Joo, “Low Temperature Poly-Si Thin-film Transistor Fabrication by Metal-induced Lateral Crystallization,” IEEE Electron Device Lett., vol. 17, pp.
160-162, 1996.
[27] Y. G. Yoon, M. S. Kim, G. B. Kim and S. K. Joo, “Metal-induced Lateral Crystallization of a-Si Thin Films by Ni-Co Alloys and the Electrical Properties of
[28] M. Wang, Z. Meng and M. Wong, “The Effects of High Temperature Annealing on Metal-induced Laterally Crystallized Polycrystalline Silicon,” IEEE Trans. Electron Devices, vol. 47, pp. 2061-2067, 2000.
[29] C. Hayzelden and J. L. Batstone, “Silicide Formation and Silicide-mediated Crystallization of Nickel-implanted Amorphous Silicon Thin Films,” J. Appl. Phys., vol. 73, pp. 8279-8289, 1993.
[30] F. L. Yang, D. H. Lee, H. Y. Chen, C. Y. Chang, S. D. Liu and C. C. Huang, “5 nm-gate Nanowire FinFET,” VLSI Symp. Tech. Dig., pp. 196-197, 2004.
[31] X. Duan., Y. Huang and C. M. Lieber, “Nonvolatile Memory and Programmable Logic From Molecule-gated Nanowires,” Nano Lett., vol. 2, pp. 497-490, 2002.
[32] X. Duan, C. Niu, V. Sahi, J. Chen, J. W. Parce, S. Empedocles and J. L. Goldman,
“High-performance Thin-film Transistors Using Semiconductor Nanowires and Nanoribbons,” Nature, vol. 425, pp. 274-278, 2003.
[33] Q. Wei, H. Park and C. M. Lieber, “Nanowire nanosensors for Highly Sensitive and Selective Detection of Biological and Chemical Species,” Science, vol. 293, no. 5533, pp. 1289-1292, 2001.
[34] Z. Li, Y. Chen, X. Li, T. Kamins, K. Nauka and R. S. Williams, "Sequence-specific Label-free DNA Sensors Based on Silicon Nanowires," Nano Lett., vol. 4, no. 2, pp.
245-247, 2004.
[35] M. C. McAlpine, R. S. Friedman, S. Jin, K. H. Lin, W. U. Wang and C. M. Lieber,
“High-performance Nanowire Electronics and Photonics on Glass and Plastic Substrates,” Nano Lett., vol. 3, pp. 1531-1535, 2003.
[36] X. Duan and C. M. Lieber, “Laser-assisted Catalytic Growth of Single Crystal GaN Nanowires,” J. of American Chemical Society, vol.122, pp.188-189, 2000.
[37] X. Duan, Y. Huang, Y. Cui, J. Wang and C. M. Lieber, “Indium Phosphide Nanowires as Building Blocks for Nanoscale Electronic and Optoelectronic Devices,” Nature, vol.
409, pp.66-69, 2001.
[38] Y. Huang, X. Duan, Q. Wei and C. M. Lieber, “Directed Assembly of
[38] Y. Huang, X. Duan, Q. Wei and C. M. Lieber, “Directed Assembly of