Chapter 4 Conclusion and Future Work
4.2 Future Work
Fig.4.1 shows the diagram of the purposed ultra low voltage receiver. In this thesis, we have finished the design and measurement of the low voltage LNA and mixer. And there are many important blocks need to be implemented; Synthesizer, VGA, Gm-C filter, demodulator and A/D converter. Because our LNA is not design in the full differential configuration, an on-chip balun should be added to integrate with our differential mixer. Of course, the LNA can be redesigned in the differential topology. But the chip size and the power consumption will increase. Another solution is to design a low voltage micromixer. The RF input stage of micromixer is single-ended and can provide almost the same performance as the Gilbert double-balanced mixer. Therefore, the LNA and mixer can be integrated easily.
Fig.4.1 The diagram of the purposed ultra low voltage receiver
There are some other future works need to be implemented. First, the accurate RFMOS model and inductor model should be built. Second, the on-chip bias circuit should be designed to reduce the large numbers of DC pads. Final, the ESD protection must be designed within the thinner gate oxide process like modern 0.18
µ m
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Appendix
Concurrent Dual-Band Receiver
A.1 Introduction
With the increase demand of wireless communication with low cost and low power, recent research has been focusing on single chip solution. While it is already common to use the CMOS technology to develop base-band circuits, it is gaining popularity to use the CMOS technology to develop RF front-end circuits. As a result, a fully integrated dual-band receiver intended for GPS and Bluetooth is designed in CMOS technology in this work.
Conventional dual-band receiver architectures are achieved by building two individual receiving paths that increase the cost and power consumption [33]. The way to modify these disadvantages is using the concurrent architecture that is capable of simultaneous operation at two different frequencies without dissipating twice power and increase cost. This concurrent architecture can provide simultaneous narrow-band input matching and high gain at two frequency band while maintaining low noise figure.
A.2 Receiver Architecture
Most conventional receivers use individual receiving paths that need large hardware area. If the dual-band receiver uses concurrent architecture, its hardware cost will be high. As a result, the concurrent architecture should be taken into account.
The concurrent dual-band receiver is shown in Fig.A.1. It consists of a dual-band LNA, a dual-band sub-harmonic mixer, a dual-band Voltage-Controlled Oscillator (VCO) and a tunable Gm-C filter. Due to the modulation of the GPS is BPSK, it is either suitable for low IF architecture design [38-39]. Thus, our concurrent dual-band receiver is chosen low IF architecture (2MHZ) to reduce cost and power consumption.
In this work, we try to integrate the dual-band LNA and sub-harmonic mixer.
This work
Fig.A.1 Dual-band receiver block diagram
The architecture and frequency plan of the RF transceiver play a critical role and complexity and performance of the overall system. The receiver frequency plan is shown in the Fig.2. The receiver uses a local oscillator (LO) frequency of 0.784GHz and 1.224GHz, translating the input signal from 1.57GHz and 2.45GHz to IF of 2MHz. Because the LO frequency of the sub-harmonic mixer is half of the Gilbert type double balanced mixer, the two LO signals provided by VCO are at close range.
Therefore, the dual-band VCO can easily be designed and implemented. Then, the image frequency occurs at 1.566GHz and 2.446GHz and will be cancelled by the tunable Gm-C filter.
(a)
(b)
Fig.A.2 Receiver frequency plan (a) 1.57GHz for GPS (b) 2.45GHz for Bluetooth
A.3 Main Block Description
A.3.1 Concurrent Dual-Band LNA
The concurrent dual-band LNA is shown in Fig.A.3. The low noise and high linearity performance can be achieved by the optimization of M1 and M2, with almost no trade-offs. The optimum width of M1and M2 can be found using Eq.(2.9), where the center frequency is chosen the average of the two desired frequency. After calculation, the optimum width is approach 500µm. The input and output matching network are adding a LC tank and LC branch, respectively. The LC tank in the input is used in order to resonate the gate impedance and to provide the additional lower band gain transfer function [40-41]. The LC branch introduces a zero in the transfer function of the LNA and performs a notch between 1.57GHz and 2.45GHz to improve
receiver’s image rejection. To improve the sensitivity of the gate-induced current noise, we add a capacitor Cgs placed in parallel to the intrinsic gate to source capacitor of the input transistor. The insertion of this capacitor adds a degree of freedom to play with to achieve a better compromise between thermal and gate-inducted noise. Therefore, a new optimum condition with a lower noise figure can be achieved. But, this is paid by a slight lower forward gain.
Fig.A.3 Concurrent dual-band LNA
With a 1.8V supply, the LNA achieves power gain of 12.6dB, voltage gain of 20.9dB, S11 of -12.7dB, noise figure of 2.98dBm and IIP3 of -1.40dBm at 1.57GHz.
And at 2.45GHz, LNA provides power gain of 11.9dB, voltage gain of 20.0dB, S11 of -18.7dB, noise figure of 3.35dBm and IIP3 of 1.14dBm at 2.45GHz.The power consumption of the LNA is 18.96mW.
A.3.2 Sub-Harmonic Mixer
Fig.5 shows the schematic of the sub-harmonic mixer. The core of sub-harmonic mixer is the differential pair M1, M2 at RF ports and eight transistors M3 to M10 at LO port, where the LO is applied at roughly half the RF frequency. When operating with LO signals with large amplitude, the LO core acts as a mixer by commutating the load across the drains of the input transconductance stage at twice the LO input frequency. However, the sub-harmonic mixer topology relies on the phase relationship of the LO signals to provide a region where the 0/180o and 90/270o
quadrature ~FRF/2 signal applied to the LO inputs allows the RF signal to be switched on every quarter cycle of the LO drive waveform, creating an effective 2FLO signal [42]. There is no inductor used in the mixer for the small chip size purpose. And, the dual-band LO port matching is realized by using the off-chip element as shown in Fig.A.5.
Fig.A.5 Dual-band LO matching network
With a 1.8V supply, the sub-harmonic mixer achieves conversion gain of 2.39dB, noise figure of 8.12dBm, and IIP3 of -5.8dBm at 1.57GHz. On other hand, the mixer provides conversion gain of 1.44dB, noise figure of 9.89dbm, and IIP3 of -5.8dBm.
The power consumption is 3.24mW and IF is chosen at 2MHz.
A.4 Layout and Simulation Results
The layout of the dual-band receiver is shown in Fig.A.6. Because the receiver is measured on PCB rather than on wafer, the bond wire and pad parasitic capacitance should be considered. The RF input ports of the receiver are on the left side. The bias of the LNA and the LO input ports are on the top and bottom of the chip. The bias of the mixer and the IF output ports are on the right side. Here, the two circuits are surrounding by a guard ring to avoid the noise coupling. Then, the total chip size is 1.4mm*1.3mm.
R F I n put IF Outpu t & Mi xer Bias LNA Bias
LNA Bias
LO Input
LO Input Dual-Band LNA Mixer
Fig.A.6 Layout of the dual-band receiver
The simulation results are shown in Fig.A.7. The voltage gain of the receiver is 27.7dB at 1.57GHz and 24.2dB at 2.45GHz. The noise figure is 4.13dB and 6.84dB, the p1dB is -29.9dBm and -24.4dBm, IIP3 is -19dBm and -16dBm, and the total power dissipation is 22.2mw. And the summary of the simulation results are in the Table A.1.
(a) RF input RL (b) LO input RL
(c) NF @ 1.57GHz (d) NF @ 2.45GHz
(e) Gain vs. LO power @ 1.57GHz (f) Gain vs. LO power @ 2.45GHz
(g) Gain vs. RF power @ 1.57GHz
(i) IIP3 @ 1.57GHz
(h) Gain vs. RF power @ 2.45GHz
(j) IIP3 @ 2.45GHz
Fig.A.7 Simulation results
Specification @ 1.57 GHz @ 2.45 GHz
RF Input RL (dB) -17.4 -24.2
LO Input RL (dB) -9.87 -13.8
NF (dB) 4.13 6.84
Voltage Gain (dB) 27.7 24.2
P1dB (dBm) -29.9 -24.4
IIP3 (dBm) -19 -16
Power (mw) 22.2mw
Table A.1 Concurrent dual-band receiver simulation results summary
The specification of the GPS is conversion gain>85dB, NF<5dB, IIP3>-20dBm.
And the specification of Bluetooth is conversion gain>50dB, NF<8dB, IIIP3>-16.5dBm. By the simulation results, the NF is in the specification of the two applications. The conversion gain would be amplified by the IF amplifier or the variable gain amplifier (VGA). In general, the gain of the IF amplifier or VGA can be higher than 60dB. Therefore, performance of the conversion gain would be in specification too. But the linearity of the GPS is 1dBm lower than the specification and closely to the boundary of the specification. The main reason is the linearity of the mixer is not good enough that decrease the overall linearity. This could be modified by decreasing the gain of the LNA or mixer to increase the linearity. But consider the bad noise performance; we do not do this correction. Another solution is modified the topology of the mixer- adding an inductor between the drains of the
transconductance stage (M1, M2) to enhance the linearity. Because this modify will increase the chip area, we do not choose this change. We do the modification on the other way; do more strictly on the linearity of the VGA that would modify the linearity of receiver