Measurement Consideration - 0.7V 2.45GHz Mixer

Chapter 3 0.7V 2.45GHz Mixer

3.4 Measurement Consideration

Because the mixer is designed for PCB on-board testing, the parasitic effects of bond wires and bond-pads will greatly affect the impedance matching of all ports. For all outside 50

Ω

instruments, only input power of generators can be delivered into the chip or circuit output power can be received by measurement instruments more efficiently with good input or output impedance matching. Therefore, these parasitic effects must be included and considered throughout all simulation procedure very carefully. Typically, the inductance of the bond wire is about 1nH per 1mm and the parasitic capacitance of a 100um x 100um bond pad is approximate 150fF to the ground.

Because of fully differential configuration of the mixer, two Balun are required to transform single input to differential inputs. Here, we used a rat race shown in Fig3.7 to act as such Balun and the real S-parameter is as follow.

0.046 85.71 0.678 155.1 0.675 152.7 0.032 25.9 0.676 154.2 0.055 55.93 0.035 20.5 0.671 22.7 0.675 152.3 0.035 21.3 0.017 139.9 0.676 155.7 0.032 26.1 0.671 22.9 0.675 154.6 0.065 45.1

∠ ° ∠ ° ∠ ° ∠ − °

Although this experimental result still has little error, it is very close to that of ideal case and satisfies for our requirement.

Layout of PCB and practical FR4 PCB circuit with SMA connectors are shown in Fig.3.8 and Fig.3.9, respectively. The RF, IF and LO signal path are drawn as 50

Ω

line width for impedance matching. Several on board decoupling capacitances are added on the DC path to filter the noise from the power supply.

The measurement setup is shown in Fig.3.10. The measured parameters are conversion gain, P1dB, IIP3 and high frequency input return loss of RF and LO ports.

We use RFIC measurement system in CIC to complete our measurement. And the wide band Balun block used in the RF port is also provided by CIC. The loss of cable, Balun, SMA connector and board must be taken into account.

Fig.3.7 Photograph of LO port Rat-race

50 ohm Line

Blocking Capacitor &

Low Pass Filter Decouple CapacitorDecoupling Capacitor

Fig.3.8 PCB layout

RF input IF output

LO input

Fig.3.9 Practical FR4 PCB circuit

2 parallel bond wires

Fig.3.10 Photograph of low voltage mixer

(a)

(b)

(c)

Fig.3.11 Measurement setup of (a) Conversion gain (b) IIP3 (c) Input return loss

The practical measurement picture is shown in Fig.3.11 which include of the mixer, PCB board, Balun and cables.

Fig.3.12 Measurement picture

To find out the loss of RF port to IF port, and confirm if the loss would affect the circuit performance, we utilize the 50

Ω

line testing board for the loss testing. The loss of board and SMA connectors are about 0.4dB. The practical picture and measurement result are shown in Fig.3.11 and Fig.3.12. Furthermore, the loss of cable and Balun is calculated and compensated in CIC RFIC measurement system.

Fig.3.13 Loss testing board

Board Loss

Frequency (GHz)

0 1 2 3 4 5

-0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1

Measurement

Fig.3.14 Measurement results of the board loss

3.5 Simulation and Measurement Results Comparison

Upon previous measurement considerations and arrangement, we have made all PCB on-board testing for our design in CIC and our laboratory. It is found that the current in each transconductance stage is 0.2mA, a little larger but close to the simulation result in TT-core. On the other hand, the current in the switching stage is twice than that in simulation. Therefore, we can determine the PMOS transistors in the FF-core. Fortunately, the PMOS transistors act as a switched do not seriously affect the circuit performance. Therefore, we try to increase the bias of the PMOS transistors to decrease their current and make the PMOS transistors more close to the saturation and threshold region. With the supply voltage of 0.7V, the power consumption of the mixer is 2.11mw which is a little larger than the simulation results in the TT corner.

From 0.45GHz to 4.45GHz, the RF port input return loss at 2.45GHz in 50

Ω

measurement system is -8.9dB as shown in Fig.3.15. The peak value about -14dB is shifting down to 2.35GHz that may come from the larger bond wires inductance in the input network. Although two parallel bond wires are used in the ground pad to decrease the bond wire inductance, the inductance remains larger than we expected.

Here, we also add a modified simulation without changing the bias and power to find out the problems caused by frequency shifting. The LO input return loss include additional effect of π -matching circuit is about -12.5dB at 2.448GHz as shown in Fig.3.16. Even though it is 7dB less than the simulation result, -12.5dB must be satisfied for our specification.

RF port input return loss

Fig.3.15 Measurement RF port input return loss

LO port input return loss

Frequency (GHz)

Fig.3.16 Measurement LO port input return loss

When the RF input power is -30dBm and LO power is -3dBm, the measurement output power is only -9.48dB as shown in Fig.3.17. Deduct from the loss of the PCB board, the power gain is -9.08dB. By the modified simulation results shows the frequency shifting in the RF port and the bond wire variation in the LC tank will affect the performance seriously. Although we try to use several length of the bond wire to find the optimum performance of the mixer, we do not successful find this optimum length. Of course, no buffer added in the output so that the mixer could not push the 50 Ω load may be another reason.

Fig.3.17 Power Gain (RF power =-30dBm, LO power = -4dBm, IF=-39.48dBm)

Power gain vs. LO input power

LO input power (dBm)

Fig.3.18 Power gain vs. LO power

The linearity is better than simulation due to the low conversion gain. The P1dB is 0dBm and IIP3 is 10dBm as shown in Fig.3.19 and Fig.3.20, respectively. These two measurement results are also close to the modified simulation results. Finally, the IF output waveform is also measured by oscilloscope (1Meg Ω load), instead of spectrum analyzer (50 Ω load). Fig.3.21 shows that the peak-to-peak voltage of IF output waveform is 22.19mV while the RF input power is -30dBm. By the simple mathematics transform, the mixer exhibits 0.91dB of voltage gain. Because the gain

out the output impedance of the mixer. After calculation, the output impedance is about 125 Ω . This value is smaller than our resistive load of 200 Ω . As a result, we can say the smaller load resistor is another reason causes the conversion gain degradation.

Power gain vs. RF input power

RF input pwer (dBm)

Fig.3.19 Power gain vs. RF power

Fig.3.20 Measurement result of IIP3

Fig.3.21 IF output waveform

Although the current in the transconductance stage is larger than simulation, the gain is not larger than modified simulation result. This is because of the Gm in the transconductance stage is almost the same as simulation. As shown in Fig.3.22, the Gm value is the slope of the two curves. It is obviously that the slopes of the two curves are almost the same, so Gm of them is almost the same. As a result, the power gain and voltage gain do not increase with the more power consumption of the mixer.

There are two main reasons leading to the decrease of power gain and voltage gain.

The first is the bond wire in the Vd pad. As described in Sec.3.1, the resonant frequency of the LC tank is dependent with the bond wires. The simulation shows the difference of the two bond wires makes the resonant frequency offset that makes the voltage gain decrease. Second, the frequency shifting in the RF port also affects the performance of the mixer. Last, the smaller load resistor is a factor causes the conversion gain degradation.

Vgs vs. current in the transconductance stage

Vgs (V)

0.48 0.50 0.52 0.54 0.56 0.58 0.60 0.62

current (mA)

Fig.3.22 The characteristic of Vgs versus current in the transconductance stage

Table 3.2 shows the comparison of this work and recent mixer papers. As we described in Chapter 2, the simulation and measurement data are shown. Although the conversion gain of the mixer is not as high as other design, it is known that an active mixer has a gain of 5dB is enough. The reason why we do not design a high gain mixer is that we try to design a high linearity mixer to compensate the worse linearity performance in our LNA design. Therefore we should decrease the conversion gain to attain better linearity performance. Although the measurement power gain is only -9.08dB, it is obviously that our mixer has the best linearity performance than others.

And in the view of the integrated receiver, the load of the mixer is the high impedance of the VGA or IF filter instead of the 50 Ω load. Thus, the gain will be increased.

Even under a low IF configuration, the noise performance is still better than others.

This is because we choose the PMOS type folded cascode configuration that depresses the flicker noise in the switching stage. It is a pity that the noise figure could not be measured in this work. This is because the noise meter in CIC can’t operate in the frequency lower than 10MHz. Therefore, we can verify our noise performance. The measurement results show that the power consumption is only 2.11mw with the 0.7V supply voltage that is still lower than the greater part.

Specification Simulation Measurement

IF (MHz) 2 2

RF Input RL (dB) -11.1 -8.9

LO Input RL (dB) -19.3 -12.5

Voltage Gain (dB) 6.83 0.91

Power Gain (dB) 2.50 -9.08

P1dB (dBm) -2.5 0

IIP3 (dBm) 8 11

NF (dB) 9.13 NA

LO-to-RF Isolation (dB) -72.3 -36

Power (mw) 1.84 2.11

Table 3.1 Simulation and Measurement results summary

REF

Condition Sim. Meas. Sim. Meas. Meas. Meas. Sim.

Table 3.2 Comparison of recent mixer papers

Chapter 4 Conclusion and Future Work

4.1 Conclusion

This thesis contains two works：low voltage LNA and mixer. All of the simulation results are finished through Eldo-RF simulator. These two circuits are fabricated in TSMC 0.18

µ m

CMOS process through CIC. In this thesis, we have presented the design concepts and simulation versus measurement results.

4.1.1 Low Voltage Variable-Gain LNA

The fully integrated 0.7V variable-gain LNA has been designed and presented in this thesis. All measurements were finished through on-wafer measurement at CIC.

The power consumption is 7.27mw, being almost the same as the simulation. But, the measurement results show that the LNA only provide a gain of 2.2dB, noise figure of 6.2dB, and IIP3 of 8dBm at the high gain mode. The gain and linearity release can be 6.5dB and 7dBm. The major reason causing the low gain is the frequency shifting of the S11, which only achieves -4.35dB at 2.45G. This may come from the incorrect on-chip model or the large parasitic inductance on the input matching network.

However, the low gain performance led to the better linearity performance; IIP3 is 8dBm at high gain mode and 15dBm at low gain mode. Although the measurement results such as S-parameter and noise figure do not meet our expectation, the function of the linearity release is work.

4.1.2 Low Voltage Mixer

The modified 0.7V PMOS type folded cascode double-balanced mixer has been designed and presented in this thesis. All measurement results were finished through PCB on-board testing at CIC. With the 0.7V supply voltage, the mixer exhibits 0.91dB of voltage gain, -9.48dB of power gain, 0dBm of P1dB, 10dB of IIP3, and 2.11mW of power consumption. Although the power gain is not as expected, the high linearity is achieved in this work. These differences may come from the practical rat-race circuit generating deviations of non-equal power and non-180o phase difference, non optimum bond wires in the LC tank and the frequency shifting in the RF port. The measurement results show that the modified low voltage mixer exhibits a low power, high linearity than the conventional Gilbert type mixer architecture.

4.2 Future Work

Fig.4.1 shows the diagram of the purposed ultra low voltage receiver. In this thesis, we have finished the design and measurement of the low voltage LNA and mixer. And there are many important blocks need to be implemented; Synthesizer, VGA, Gm-C filter, demodulator and A/D converter. Because our LNA is not design in the full differential configuration, an on-chip balun should be added to integrate with our differential mixer. Of course, the LNA can be redesigned in the differential topology. But the chip size and the power consumption will increase. Another solution is to design a low voltage micromixer. The RF input stage of micromixer is single-ended and can provide almost the same performance as the Gilbert double-balanced mixer. Therefore, the LNA and mixer can be integrated easily.

Fig.4.1 The diagram of the purposed ultra low voltage receiver

There are some other future works need to be implemented. First, the accurate RFMOS model and inductor model should be built. Second, the on-chip bias circuit should be designed to reduce the large numbers of DC pads. Final, the ESD protection must be designed within the thinner gate oxide process like modern 0.18

µ m

CMOS process.

Reference

[1] Bluetooth Specification Version 1.0B

[2] T. H. LEE, “The Design of CMOS Radio frequency Integrated Circuit,” 2004

[3] B. Razavi, “RF microelectronic,” Prentice Hall 1998

[4] T. Cho, D. Kang, S. Dow, C. H. Heng, B. S. Song, “A 2.45-GHz Dual-Mode 0.18-um CMOS Transceiver for Bluetooth and 802.11b,” Solid-State Circuits, IEEE Journal of Volume 39, Issue 11, Nov. 2004 Page:1916 - 1926

[5] G. Ordu, S. Sappok, R. Wunderlich, S. Heinen, “A novel approach for IF selection of Bluetooth Low-IF receiver based on System Simulations,” SOC Conference, 2003. Proceedings. IEEE International 17-20 Sept. 2003 Page:43 - 46

[6] H. Darabi, J. Chiu, S. Khorram, H. Kim, Z. Zhou, H. M. Chien, B. Ibrahim, E.

Geronaga, L. H. Tran, A. Rofougaran, “A Dual-Mode 802.11b/Bluetooth Radio in 0.35-um CMOS,” Solid-State Circuits, IEEE Journal of Volume 40, Issue 3, March 2005 Page:698 - 706

[7] W. Sheng, B. Xia, A. E. Emira, C. Xin, A. Y. Valero-Lopez, S. T. Moon, E.

Sanchez-Sinencio, “A 3-V, 0.35-um CMOS Bluetooth Receiver IC,” Solid-State Circuits, IEEE Journal of Volume 38, Issue 1, Jan. 2003 Page:30 - 42

[8] W. Hioe, K. Maio, T. Oshima, Y. Shibahara, T. Doi, K. Ozaki, S. Arayashiki,

“0.18um CMOS Bluetooth Analog Receiver With -88-dBm Sensitivity,”

Solid-State Circuits, IEEE Journal of Volume 39, Issue 2, Feb. 2004 Page:374 -

377

[9] H. Komurasaki, T. Sano, T. Heima, K. Yamamoto, H. Wakada, I. Yasui, M. Ono, T.

Miwa, H. Sato, T. Miki, N. Kato, “A 1.8-V Operation RF CMOS Transceiver for 2.4-GHz-Band GFSK Applications,” Solid-State Circuits, IEEE Journal of Volume 38, Issue 5, May 2003 Page:817 - 825

[10] V. S. L. Cheung, H.C. Luong, “A 1V 10-mW monolithic Bluetooth receiver in a 0.35/spl mu/m CMOS process,” Solid-State Circuits Conference, 2003.

ESSCIRC '03. Proceedings of the 29th European 16-18 Sept. 2003 Page:687 - 690

[11] A. N. L. Chan, K. W. H. Ng, J. M. C. Wong, H. C. Luong, “A 1-V 2.4-GHz CMOS RF receiver front-end for Bluetooth application,” Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on Volume 4, 6-9 May 2001 Page:454 - 457 vol. 4

[12] M.N.EL-Gamal, K.H.Lee and T.K. Tsang, “Very low-voltage (0.8v) CMOS receiver frontend for 5GHz applications,” Circuits, Device and Systems, IEEE Proceedings vol 149, no.516, Oct 2002, page: 255-262

[13] M. K. Raja, T. T. C. Boon, K. N. Kumar, W. S. Jau, “A fully integrated variable gain 5.75-GHz LNA with on chip active balun for WLAN,” Radio Frequency Integrated Circuits Symposium, 2003 IEEE 8-10 June 2003 Page: 439 - 442

[14] E. A. Allam, T. Manku, “A LOW VOLTAGE DESIGN TECHINIQUE FOR LOW NOISE RF INTEGRATED CIRCUITS,” Circuits and Systems, 1998.

4, 21 May-2 June 1998 Page:272 - 277 vol.4

[15] K. K. Tommy, Tsang, N. E. G. Mourad, “Gain CONTROLLABLE VERY LOW VOLTAGE(<1V)8-9 GHZ INTEGRATED CMOS LNA’S,” Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE 2-4 June 2002 Page:205 - 208

[16] E. A. Allam, J. J. Nisbet, C. M. Maliepaard, “Low-Voltage 1.9-GHz Front-End Receiver in 0.5-um CMOS Technology,” IEEE JSCC, vol.26, no.10, Oct 2001 Page: 1424-1442

[17] T. Manku, G. Beck, E. J. Shin “A low-voltage design technique for RF integrated circuits,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 45, Issue 10, Oct. 1998 Page:1408 - 1412

[18] C. L. Hsiao, R. M. Wong, K.Y. Lin, “A 1V Fully Differential CMOS LNA For 2.4GHz Application,” Circuits and Systems, 2002. ISCAS '02. Proceedings of the 2002 International Symposium on Volume 1, 25-28 May 2002 Page:I-245 - I-248 vol.1

[19] D.K. Shaeffer, T.H.LEE, “A1.5-V, 1.5GHz CMOS Low Noise Amplifier,” IEEE JSSC, vol.22, no.5, pp.745-759, May 1997

[20] W. Guo, D. Huang, “NOISE AND LINEARITY ANALYSIS FOR A 1.9GHZ CMOS LNA,” Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on Volume 2, 28-31 Oct. 2002 Page:409 - 414 vol.2

[21] B.Leung, “VLSI for Wireless Communication,” Prentice Hall 2002

[22] L. Zhenying, S. C. Rustagi, M. F. Li, Y. Lian, “A 1V, 2.4GHz Fully Integrated LNA Using 0.18um CMOS Technology,” ASIC, 2003. Proceedings.5th International Conference on Volume 2, 21-24 Oct. 2003 Page:1062 - 1065 Vol.2

[23] T. K. K. Tsang, M. N. E. Gamal, “DUAL-BAND SUB-1V CMOS LNA FOR 802.11A/B WLAN APPLICATION,” Circuits and Systems, 2003. ISCAS '03.

Proceedings of the 2003 International Symposium on Volume 1, 25-28 May 2003 Page:I-217 - I-220 vol.1

[24] J. Chen, B. Shi, “A 2.4GHz CMOS LNA with Full ESD Protection,” ASIC, 2003.

Proceedings. 5th International Conference on Volume 2, 21-24 Oct. 2003 Page:1058 - 1061 Vol.2

[25] V. Vidojkovic, J. V. D. Tang, A. L. Leeuwenburgh, A. V. Roermund,

“A.FULLY-INTEGRATED DECT/BLUETOOTH MULTI-BAND LNA IN 0.18um CMOS,” Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on Volume 1, 23-26 May 2004 Page:I - 569-72 Vol.1

[26] D. Manstretta, R. Castello, F. Svelto, F., “Low 1/f Noise CMOS Active Mixers for Direct Conversion,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 48, Issue 9, Sept. 2001 Page:846 - 850

[27] K. J. Koh, M. Y. Park, C. S. Kim, H. K. Yu, “Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver,” Solid-State Circuits, IEEE Journal of Volume 39, Issue 6, June 2004 Page:871 - 884

[28] H. C. Wei, R. M. Weng, K. Y. Lin, “A 1.5V HIGH-LINEARITY CMOS MIXER FOR 2.4GHZ APPLICATIONS,” Circuits and Systems, 2004. ISCAS '04.

Proceedings of the 2004 International Symposium on Volume 1, 23-26 May 2004 Page:I - 561-4 Vol.1

[29] H. Komurasaki, T. Sano, T. Heima, K. Yamamoto, H. Wakada, I. Yasui, M. Ono, T. Miwa, H. Sato, T. Miki, N. Kato, “A 1.8-V Operation RF CMOS Transceiver for 2.4-GHz-Band GFSK Applications,” Solid-State Circuits, IEEE Journal of Volume 38, Issue 5, May 2003 Page:817 – 825

[30] A. Rofougaran, J. Y. C. Chang, M. Rofougaran, A. A. Abidi, “A 1GHz CMOS RF Front-end IC for a Direct-Conversion Wireless Receiver,” Solid-State Circuits, IEEE Journal of Volume 31, Issue 7, July 1996 Page:880 - 889

[31] J .C. Rudell, J. J. Ou, T. B. Cho, G. Chien, F. Brianti, J. A. Weldon, P .R. Gray,

“A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications,” Solid-State Circuits, IEEE Journal of Volume 32, Issue 12, Dec. 1997 Page:2071 - 2088

[32] H. Darabi, A. A. Abidi, “Noise in RF-CMOS Mixer: A Simple Physical Model,”

Solid-State Circuits, IEEE Journal of Volume 35, Issue 1, Jan. 2000 Page: 15 - 25

[33] S. Wu, B. Razavi, “A 900-MHz/1.8-GHz CMOS Receiver for Dual-Band Applications,” Solid-State Circuits, IEEE Journal of Volume 33, Issue 12, Dec.

1998 Page:2178 - 2185

[34] V. Vidojkovic, J. V. D. Tang, A. L. Leeuwenburgh, A. V. Roermund, “A HIGH GAIN, LOW VOLTAGE FOLDED-SWITCHING MIXER WITH

CURRENT-REUSE IN 0.18um CMOS,” Radio Frequency Integrated Circuits Symposium, 2004. Digest of Papers. 2004 IEEE 6-8 June 2004 Page:31 - 34

[35] V. Vidojkovic, J. V. D. Tang, A. L. Leeuwenburgh, A. V. Roermund, “MIXER TOPOLOGY SELECTION FOR A 1.8-2.5GHZ MULTI-STANDARD FRONT-END IN 0.18um CMOS,” Circuits and Systems, 2003. ISCAS '03.

Proceedings of the 2003 International Symposium on Volume 2, 25-28 May 2003 Page:II-300 - II-303 vol.2

[36] C. G. Tan, “A High-Performance Low-Power CMOS Double-Balanced IQ Down-Conversion Mixer for 2.45-GHz ISM Band Applications,” Radio Frequency Integrated Circuits Symposium, 2003 IEEE 8-10 June 2003 Page:457 - 460

[37] C. Yu; O, K.K., “Evaluation of Utilizing 0.18um PMOS Transistors in a 2.4-GHz Receiver,” Radio Frequency Integrated Circuits Symposium, 2004. Digest of Papers. 2004 IEEE 6-8 June 2004 Page:555 - 558

[38] G. Montagna, G. Gramegna, I. Bietti, M. Franciotta, A. Baschirotto, P. D. Vita, R.

Pelleriti, M. Paparo, R. Castello, ”A 35-mW 3.6-mm² fully integrated 0.18-um CMOS GPS radio,” Solid-State Circuits, IEEE Journal of Volume 38, Issue 7, July 2003 Page:1163 - 1171

[39] T. Kadoyama, N. Suzuki, N. Sasho, H. Iizuka, I. Nagase, H. Usukubo, M.

Katakura,“ A Complete Single-Chip GPS Receiver With 1.6-V 24-mW Radio in 0.18-um CMOS”, Solid-State Circuits, IEEE Journal of Volume 39, Issue 4, April 2004 Page:562 - 568

[40] H. Hashemi, A. Hajimiri “ Concurrent Miltiband Low-Noise Amplifiers--Theory, Design, and Applications,” IEEE Transactions On Micro Theory And Techniques, vol.50, no.1 Jan 2002

[41] X. Yang, T. Wu, J. McMacken “Design of LNA at 2.4 GHz Using 0.25µm technology,” Silicon Monolithic Integrated Circuits in RF Systems, 2001. Digest of Papers. 2001 Topical Meeting on, 12-14 Sept. 2001

[42] M. Goldfarb, E. Balboni, J. Cavey “Even Harmonic Double-Balance Active Mixer for Use in Direct Conversion Receivers,” IEEE J. Solid-State Circuits, vol.38,no.10 Oct. 2003.

Appendix

Concurrent Dual-Band Receiver

A.1 Introduction

With the increase demand of wireless communication with low cost and low power, recent research has been focusing on single chip solution. While it is already common to use the CMOS technology to develop base-band circuits, it is gaining popularity to use the CMOS technology to develop RF front-end circuits. As a result,

在文檔中應用於藍芽系統之超低電壓(0.7V)可調增益低雜訊放大器及混頻器設計 (頁 52-0)