Simulation and Measurement Results Comparison

Chapter 2 0.7V 2.45GHz Variable-Gain Low-Noise Amplifier

2.5 Simulation and Measurement Results Comparison

Fig.2.10 shows the simulation, measurement and modified simulation results of S21 and S11

Fig.2.10 Comparison between simulation and measurement of S21 and S11

We find that the S21 is appeared closely at the center frequency, but S11 is shifted down to the 1.7GHz. The simulation and measurement results are not meeting

the same way. Thus, we modify circuit parameters to fit the measurement results. By the Eq.(2.3), the larger inductor and gate to source capacitor the lower resonant frequency. Thus, a larger inductor and capacitor on the input matching network make the optimum matching peak of S11 shift down to the low frequency. We try to increase the inductors of M1 to fit the measurement results. Fortunately, the modified simulation results can achieve closed results as measurement. Therefore, we can prove the larger inductance appears in the input matching network make the frequency shifting. This may come from the incorrect model of the on chip inductor and the large parasitic inductor from the long RF line in the input matching network.

Although through the layout parasitic extraction (LPE), we still can not accurately predict the parasitic effects in the high frequency region. The larger parasitic inductor and capacitor can be avoided by advanced layout skill that is a worthy goal for designer to learn. Because of the resonant frequency of the LC tank is closed to 2.45GHz, the S21 parameter closely falls on desired band. And there are three possible reasons make the value be -15dB lower than simulation. First and the major reason is the frequency shifting of S11. Second, the inductance of

L

_dpand

L

_out is smaller than we expected. Third, the Q value of the LC tank is not good enough with the LNA layout design, that making the RF signal loss to ground.

Fig.2.11 shows the simulation, measurement and modified simulation results of S22 and S12. The peak of the output matching S22 is shifted down to 2GHz and is -10dB at 2.45GHz. By the modified simulation, we can find the smaller inductor and capacitor on the output matching network make a -10dB reduction. Although -10dB is achieved, it is enough for applications. From above discussion, the correct model for the on chip inductor is the most important in the LNA design. The S12 is as good as simulation results that prove the folded cascode configuration can provide good

isolation as the conventional cascode configuration.

Fig.2.11 Comparison between simulation and measurement of S22 and S12

The noise figure is measured from 100MHz to 3GHz as shown in Fig.2.12.

The noise performance is not good, rising to 6.22dB at high gain mode. The major reason is the gain of the LNA is only 2.21dB that can not suppress the noise contribution. And the measurement result is a little higher than modified simulation results. This is because the transistor model is not accurate enough which only

consider the thermal noise and gate induced noise is not included. But the peak value of noise figure is almost appeared at the center frequency. That is because the peak value of S21 is close to the center frequency. Thus, if we can achieve enough gain, the noise figure may go down to anticipated value below 2.5dB.

Fig.2.12 Comparison between simulation and measurement of NF

The LNA design can achieve better dynamic range and linearity of P1dB and IIP3 parameters in measurement than those in simulation. As shown in Fig.2.13, the modified simulation and the measurement results are almost the same, the IIP3 is 8dBm at the high gain mode and 15dBm at the low gain mode. Of course, that is due to the lower gain performance cause the high linearity. The difference of linearity between high and low gain mode is 7dB, being almost the same as simulation. Thus, the function of the linearity release is work. And the performance of the simulation and measurement is summarized in the Table 2.1. The total power consumption is 7.27mw at the high gain mode and 5.06mw at the low gain mode.

P1dB

Fig.2.13 Comparison between simulation and measurement of P1dB and IIP3

Table 2.2 shows the comparison of this work and recent LNA papers. Because the difference between simulation and measurement results, both data are showed.

According to the simulation results, power consumption and the noise figure is the lowest one. The forward gain, input matching, output matching are designed at a suitable value above 15dB. And the most important performance, noise figure, is designed to a lowest value. Although linearity is not good enough, it is in the specification for Bluetooth and 802.11b applications. Because of the linearity of the receiver is dominated by the later stage as mixer, our goal is to design a LNA with low

Simulation Measurement

Specification High gain mode

frequency(GHz) 2.45 2.45 2.45 2.45

S21 (dB) 17.5 12.8 2.21 -4.38

Table 2.1 Measurement and Simulation results Summary

REF [16]

Condition Sim. Meas. Meas. Meas. Sim. Meas. Sim.

Table 2.2 Comparison of recent LNA papers

Chapter 3 0.7V 2.45GHz Mixer

In this chapter, we will present a 0.7V mixer designed and fabricated in TSMC 0.18 mµ CMOS process. Like the design method applied in low voltage LNA, the differential PMOS type folded cascode configuration is used. We will analysis the conversion gain, noise and linearity of the low voltage mixer. The measurement results show that the mixer provides a voltage gain of 0.91dB, power gain of -9.68dB, P1dB of 0dBm, and IIP3 of 10dBm with the 2.11mW power consumption. The discussion of the difference between simulation results and measurement results and the comparison of other low voltage mixer papers will be in the last section.

3.1 Introduction

An essential element in modern transmitters and receiver is the mixer, being responsible for frequency up-conversion and down conversion. Modern wireless communication systems demand stringent dynamic range requirement that is often dominated by the mixer. Thus, mixer design focuses on balancing the tradeoff between gain, linearity, matching, port to port isolation, LO power, noise figure and power consumption. The noise performance of the mixer is not too stern because it is located after the LNA that will suppress the noise contributed from mixer. Therefore, a good mixer design is focused on the high linearity. The mixer would handle larger signal than LNA, and its non-linearity must be lower by at least a factor of the LNA gain if it is not to become the bottleneck to receiver dynamic range. And, integrated mixers become more desirable than discrete ones for higher system integration for cost and space saving.

Passive and active mixers are two common topologies in recent research. The name “passive” mixer comes from the characteristic that it does not provide any gain.

Since double balanced active mixer designs are more desirable for today’s integrated receiver designs due to its low spurious outputs, high common mode noise rejection, high port to port isolation and the most important, gain. Thus, our low voltage mixer is basically a double balanced active mixer configuration.

3.2 Mixer Design

Load Stage

Switching Stage

Transconductance Stage

Current Tail

Fig.3.1 Gilbert type double balanced mixer architecture

Fig.3.1 shows a most common seen topology for mixer called Gilbert-type double balanced mixer. It has the virtue of moderate gain, good RF-LO isolation, and

transconductanc stage, the switching stage and the load stage. Outputs are located between the switching stage and the load. The transconductance transistors first amplify the input voltage signal and convert the signal into a current signal. Then the switching stage performs the frequency translation, and the load converts the current signal back to voltage signal.

Because the above double balanced mixer has a stack of three transistors and a load resistor between the voltage rails. It is not suitable while the supply voltage decreases to 0.7V. Thus, folded cascode configuration is used to reduce the stack of the transistors. As described in Chapter 2, there are two topologies for folded cascode, PMOS type [16, 26-27] and NMOS type [17, 28] as shown in Fig.3.2. In the differential circuits like mixer, NMOS type will need four LC tanks that the chip area is much larger than PMOS type. And on the low IF receiver, flicker noise of the switching stage is the most important noise source for the mixer. It is know that PMOS has less flicker noise than NMOS, and the low voltage mixer is basically a PMOS type configuration to achieve better noise performance.

(a) NMOS type (b) PMOS type

Fig.3.2 Two types of the differential folded cascode configuration

Fig.3.3 Architecture of modified very low voltage mixer

Fig.3.3 shows the proposed low voltage mixer. As the typical double balanced mixer, NMOS M1 and M2 acts as transconductance stage, PMOS P1-P4 act as the switching stage and using two resistors as load stage. The current tail is not used because it will cost the voltage headroom and decrease the linearity. The high impedance LC tank is made by

L

_dp,

L

_dnand

C

_d unlike using two separated LC tanks in general design. The resonant frequency is designed at center frequency-2.45GHz.

Here, the bond wires, the parasitic capacitances and the

C

_gsof PMOS must be considered.

( ¹ )( )

2

bond dp d gsp

w ≈ L L C C

+ +

^(3.1)

It is obviously that the inductors are half of the two separate LC tanks design so we can save more chip size. The input matching network is made by

L

(

L

C

bp(

C

_bn),

C

_gp(

C

_gn),

C

_gsp(

C

_gsn)and the bond wires on RF input and on the source of M1 (M2). Using the Eq.(2.2) and assuming each bond wire be 3nH, we design the input matching network. Here, the resistor load

R

_ifp(

R

_ifn) is used instead of the active load to decrease the flicker noise contributed from load stage. Since the load is resistive, the need of a common-mode feedback (CMFB) circuit is avoided. In order to realize an on-chip band pass filter (BPF), the IF frequency should be lower, <3MHz, because a low-Q BPF is easy to design and the current consumption must be reduced.

Thus, an IF of 2MHz is chosen

3.2.1 Conversion Gain

In Fig.3.2, we assume that the mixer under large LO driver and the mixer commutates the RF transconductance current with a square wave. Suppose a unit sinusoidal input voltage of frequency

w

_RF is linearity converted to a current, and commutated by the switches at

w

_LO, which amounts to multiplying the sinusoidal current by a square wave,

sq w t (

_LO

)

, alternating between +1 and -1. Then the

where the square wave is expanded as a Fourier series, and the term containing the downconverted frequency at

w

_RF

− w

_LO is retained. Eq.(3.2) shows a current conversion loss of at least

2 π

through the mixer. The overall mixer voltage gain is

4

m RF ifp

Gain g R

= π

^(3.3)

If we consider the switching time of switching stage P1-P4, we can re-express Eq.(3.3) as Eq.(3.4) we can understand that the conversion gain is proportional to the input device transconductance, the IF load, the overdrive voltage of switching stage and the amplitude of the input LO signal. If we increase conversion gain by increasing

g

m RF ^and

V

_LO, the power consumption of the mixer and the VCO will rise simultaneously. Therefore the conversion gain forms a tradeoff with the circuit power consumption. In general, voltage and power conversion gain are not equal. The contrast between these two gains can be seen by expressing as

2 s

P V

A A R

= R

(3.5)

It indicates that the voltage and power conversion gain is equal only in the case where the differential load resistance is equal to the source resistance.

3.2.2 Noise

In the low IF receiver, flicker noise is the most important noise source of mixer.

And the double balanced mixer is composed of transconductance stage, switching stage, and load stage. Noise is present in all the transistors making up these functions.

First, the flicker noise contributed by the load stage can be reduced. It is know that the flicker noise only appears in the MOS transistors. Thus, the mixer loaded with polysilicon resistors instead of MOS transistors which are free of flicker noise from load stage. Then we discuss the flicker noise in the switching stage and transconductance stage. In [32], the signal to noise ratio of the switching stage is

( ²

^LO

)

ⁱⁿ

The relationship shows that SNR of switching stage can be improved by rising the amplitude of LO signal; by increasing the gate area of the switch transistor to lower the flicker noise

V

_n; and by lowering the transconductance transistor overdrive voltage. However, increasing switching transistor gate area is usually degraded the mixer bandwidth and lowering transconductance transistor overdrive voltage will reduce the conversion gain. Then, the signal to noise ratio due to the transconductance stage flicker noise leaking to the output is

2

_LO _in

trans

os n

A V

SNR = V ⋅ V

(3.7)

where

V

_os is the gate offset voltage due to the mismatch between switching stage.

V

_os

V

_GS

− V

_t , the switching stage induced much larger noise than the transconductance stage. Thus, we can reduce the noise by using PMOS transistor as switching stage. This is another reason why we choose folded PMOS type instead of NMOS type. Here, the width of the transconductance stage is chosen a little larger than that of Eq.(2.9) in order to lower the threshold voltage required to bias the transistors in the saturation region. The width of the switching stage is chosen one-third of the transconductance stage and is biased near threshold to minimize their switching time that reducing in the same time the output noise..

3.2.3 Linearity

Linearity is the most important parameter in mixer design. The constant current tail and the grounded sources circuits in Fig.3.4 demonstrate differential behavior in linearity.

(a) (b)

Fig.3.4 Transconductance stage with (a) constant current tail (b) grounded sources

In Fig.3.4(a)

The grounded source pair output contains no third order intermodulation products.

Thus, we note that the transconductance stage with a constant current tail exhibits higher third order nonlinearity than the grounded source pair biased at the same current and device dimensions. In practice, short channel effects such as nonlinear channel length modulation and mobility degradation with the vertical field in the channel give rise to the third order distortion, but this calculation points to the potentially higher linearity of the grounded source pair [33].

Assuming the distortion performance to be mostly constrained by the transconductance stage, we can derive a estimation on the IIP3 performance expressed as [31] distorted waveforms. Besides the voltage drop from the gate to the source of the input

device, the mismatches at the input stage also degrade the linearity performance.

As discuss above, the PMOS type folded cascode has many advantages. First, the reduction of the stack transistors let the supply voltage fall to 0.7V. Second, we use PMOS transistor as switching stage to decrease the flicker noise. Third and the most important one, the current in the transconductance stage and switching stage can be set independently to simultaneously optimize noise figure, linearity, and conversion gain. The high bias current in the transconductance stage can provide high conversion gain and better linearity performance. While minimize the flicker noise by choosing low bias current , wide device size and low gate to source overdrive voltage ( most approach zero) using in the switching stage. The size of the transconductance stage is the same as the first stage of the LNA that can decrease some thermal noise to enhance the noise performance. The input network is like the source degeneration configuration and can design by the formula in Chapter 2. Here we assume each bond wire has a 3nH inductance. The LO port matching is realized by using the off chip element as shown in Fig.3.5.

Fig.3.5 LO matching network

3.3 Layout Consideration

The most important layout guidelines are described in the Chapter 2. There is an additional guideline would be considered. The layout of the mixer should be as symmetrical as we can to avoid the phase difference and ensuring CMRR. The layout of the low voltage mixer is shown in Fig.3.6. Because the mixer is usually measured on PCB rather than on wafer, the order of pads does not need to follow the GSG (RF pad) or SGS (DC pad) rules. The RF and IF ports are on the bottom and top of the chip, and the LO port is on the right and left sides. Here, the circuit ground and substrate ground are separated to avoid the noise coupling. Then, the total chip size is 1.0mm*1.0mm.

IF Output

RF Input

LO Input LO Inp u t

Fig.3.6 Layout of the low voltage mixer

3.4 Measurement consideration

Because the mixer is designed for PCB on-board testing, the parasitic effects of bond wires and bond-pads will greatly affect the impedance matching of all ports. For all outside 50

Ω

instruments, only input power of generators can be delivered into the chip or circuit output power can be received by measurement instruments more efficiently with good input or output impedance matching. Therefore, these parasitic effects must be included and considered throughout all simulation procedure very carefully. Typically, the inductance of the bond wire is about 1nH per 1mm and the parasitic capacitance of a 100um x 100um bond pad is approximate 150fF to the ground.

Because of fully differential configuration of the mixer, two Balun are required to transform single input to differential inputs. Here, we used a rat race shown in Fig3.7 to act as such Balun and the real S-parameter is as follow.

0.046 85.71 0.678 155.1 0.675 152.7 0.032 25.9 0.676 154.2 0.055 55.93 0.035 20.5 0.671 22.7 0.675 152.3 0.035 21.3 0.017 139.9 0.676 155.7 0.032 26.1 0.671 22.9 0.675 154.6 0.065 45.1

∠ ° ∠ ° ∠ ° ∠ − °

Although this experimental result still has little error, it is very close to that of ideal case and satisfies for our requirement.

Layout of PCB and practical FR4 PCB circuit with SMA connectors are shown in Fig.3.8 and Fig.3.9, respectively. The RF, IF and LO signal path are drawn as 50

Ω

line width for impedance matching. Several on board decoupling capacitances are added on the DC path to filter the noise from the power supply.

The measurement setup is shown in Fig.3.10. The measured parameters are conversion gain, P1dB, IIP3 and high frequency input return loss of RF and LO ports.

We use RFIC measurement system in CIC to complete our measurement. And the wide band Balun block used in the RF port is also provided by CIC. The loss of cable, Balun, SMA connector and board must be taken into account.

Fig.3.7 Photograph of LO port Rat-race

50 ohm Line

Blocking Capacitor &

Low Pass Filter Decouple CapacitorDecoupling Capacitor

Fig.3.8 PCB layout

RF input IF output

LO input

Fig.3.9 Practical FR4 PCB circuit

2 parallel bond wires

Fig.3.10 Photograph of low voltage mixer

(a)

(b)

(c)

Fig.3.11 Measurement setup of (a) Conversion gain (b) IIP3 (c) Input return loss

The practical measurement picture is shown in Fig.3.11 which include of the mixer, PCB board, Balun and cables.

Fig.3.12 Measurement picture

To find out the loss of RF port to IF port, and confirm if the loss would affect the circuit performance, we utilize the 50

Ω

line testing board for the loss testing. The loss of board and SMA connectors are about 0.4dB. The practical picture and measurement result are shown in Fig.3.11 and Fig.3.12. Furthermore, the loss of cable and Balun is calculated and compensated in CIC RFIC measurement system.