Thesis Organization

This work discusses about the front-end circuit design and implementation for Bluetooth applications. The contents consist of two major topics: “0.7V 2.45GHz Variable-Gain Low-Noise Amplifier” and “0.7V 2.45GHz mixer”, respectively in Chapter 2 and Chapter 3. We will present the design flow and experimental results.

Moreover, we will discuss the reasons of differences between simulation and measurement results.

In Chapter 2, we will present the design and implementation of a low voltage variable-gain LNA. The LNA is the main block determined the noise performance of the whole receiver front-end circuit. We will discuss the configuration, variable gain mechanism, input/output matching, noise, and linearity of the LNA in this chapter.

In Chapter 3, we will present the design and implementation of a low voltage mixer. The mixer is the main block determined the dynamic range of the whole receiver front-end circuit. We will discuss the configuration, gain, linearity, and noise of the low voltage mixer in this chapter.

In chapter 4, we will make a conclusion and discuss the future work.

Finally, the appendix presents a concurrent dual-band receiver (LNA plus mixer).

Because the circuit does not tape out, we only show the simulation results. And this circuit will be implemented by our lab’s juniors.

Chapter 2

0.7V 2.45GHz Variable-Gain Low-Noise Amplifier

This chapter presents a 0.7V variable-gain LNA designed and fabricated in TSMC 0.18µm CMOS process. We will discuss the topology selection, design of input matching network, analysis of noise figure and linearity, and the variable gain mechanism in the low voltage LNA. The measurement results show that the LNA only provide a gain of 2.2dB, noise figure of 6.2dB, and IIP3 of 8dBm at the high gain mode. The gain and linearity release can achieve to 6.5dB and 7dBm. Then, the discussion of the difference between simulation and measurement results and the comparisons of other low voltage LNA papers will be in the last section.

2.1 Introduction

The low-noise amplifier (LNA) is the first stage in the receiver shown in Fig. 2.1.

Usually, it directly follows the filter inserted between the antenna and the LNA, and its output drive the mixer (or the image reject filter between the LNA and the mixer).

When the gain of the first stage is larger, the noise of the subsequent stage is reduced more. As a result, the noise performance is mainly determined by the first stage.

Therefore, the main function of the LNA is to provide enough gain to overcome the noise of subsequent stages while maintain low noise. Providing a 50

Ω

input impedance to terminate an unknown length of transmission line which delivers signal from the antenna to the amplifier is another important character. Finally, to prevent saturation of the receiver when the input signal is too large, the function of variable

gain is necessary. Thus, as so many considerations should be take into account, the design of LNA must be very carefully and completely.

Fig.2.1 Block diagram of RF receiver

2.2 LNA Design

At first sight, the LNA might be simple to design due to the relatively few components used in its implementation. However, LNA design is full of tradeoffs between optimum gain, low noise figure, input and output matching, linearity and power consumption. Generally, the LNA offers the highest gain and lowest NF in the high gain mode for the weak signal. But under strong received signal conditions, the LNA and the whole receiver may get saturated, thereby the LNA has to operate in the low gain mode to prevent saturation. Gain reduction in LNA can also reduce the dynamic range of the Automatic Gain Control (AGC), which is implemented in the IF after the down-conversion mixer. With the reduced dynamic range of the AGC, the SNR performance can be improved [13].

Conventional cascode configuration for LNA have many advantages such as enhance the gain, port to port isolation, stability and reduced Miller effect. But it is

rails. In order to be able to operate from a very low voltage supply and retain the advantages of the conventional cascode configuration, a folded cascode configuration is used as shown in Fig.2.2. The folding of the common gate stage helps to extend the cutoff frequency of the common source stage. Since it eliminates one level of transistor stacking, the supply voltage is only needed to bias a single transistor in the saturation region. Therefore, the supply voltage of the LNA can be reduced under 1V for the transistors to be biased in the saturation region. Folded cascode configuration have two types, PMOS type [12,14-16] and NMOS [17-18]type. It is obvious that NMOS type needs two LC tank networks, one more than PMOS type. Because the common gate stage acts as an current buffer and does not provide power gain for LNA, PMOS can achieve almost the same performance as NMOS. In order to save the die area, PMOS type is the common choice in recent research. And folded cascode configuration has another advantage that two transistors can be biased independently.

The first stage can be biased to provide low noise figure and the second stage can be biased at different dc current to minimize the Miller effect.

(a) NMOS type (b) PMOS type

Fig.2.2 Two types of the folded cascode configuration

Fig.2.3 Architecture of ultra low voltage variable-gain LNA

The proposed 0.7V LNA is shown in Fig.2.3. In this circuit, the RF signal is amplified by the NMOS device and the common gate current buffer is implemented by PMOS device to minimize Miller effect and to improve the response at high frequency. Then, use

C

_b2 to ac couple the RF signal to the last NMOS buffer. In the

low voltage design, we use an LC tank network (

L

_d ,

C

_d ), acting as a high impedance current source to decrease headroom dissipation. The resonant frequency of this LC tank is designed at the RF frequency of 2.45GHz. At resonant frequency, it provides a high impedance branch to force the RF signal to flow into the source of M2 and bypass other undesired signal to ground at other frequencies. Notice that the parasitic capacitance and

C

_gs2 have to be considered when determining the value of

C

_d.

(

2

)

1

o

d d gs

w ≈ L C C

+

^(2.1)

Because

C

_gs2 is eliminated or reduced at resonant frequency, it helps to suppress the noise contribution of the common gate stage at the output. Thus, the noise performance of the folded cascode configuration can be lower than conventional cascode configuration.

In order for this operation to be true, it is necessary to have the impedance of the LC tank at resonance much higher than the input resistance seen at the source of M2.

Fig.2.4 shows the characteristic of the LC tank, where

R

_sand

Q

are the resistance and the quality factor of the

L

_d. At the resonant frequency, the impedance of the LC tank attains the peak value of

R

_s

(1 + Q

²

) ≈ R Q

_s ². It can shown that this is satisfied approximately twice of the RF is sufficient to achieve the desired performance and this requirement can be easily satisfied with modern submicron PMOS devices [14].

Ld

Fig.2.4 Characteristic of LC tank

2.2.1 Input Matching

To design a LNA, the minimum noise figure and maximum power gain are the most important considerations. In fact, the noise behavior will depend on the LNA experimental results and appropriate architecture. Several architectures of the LNA for these design goals had been developed and inductive source degeneration used in the first stage of LNA is the most prevalent method for CMOS amplifiers [19]. This architecture applies a source inductor and a gate inductor to generate real impedance of the input port. This topology also has the possibility of reaching the best noise performance and is most practical for high frequency applications. A simple analysis of the input impedance of the source inductive degeneration architecture is shown blow. resistance of the MOS. For noise purposes, the effective gate resistance is given by

3

2 g

R R W

= n L

^, , where

R

_, is the sheet resistance of the poly silicon,

W

is the total gate width of the device, and

n

is the number of gate fingers used to layout the device. By interdigitating the device,

R

_g can be reduced to insignificant level. For high Q inductor,

R

_l may be negligible. If so, the real term in the input impedance is determined by

L

_s and typically is 50

Ω

. At the central frequency, the imaginary

term of

Z

_in will be zero, which gives

2.2.2 Noise Figure and MOS Width Selection

In CMOS process, drain current noise and gate noise are main noise sources in LNA design. The noise figure is related to SNR (signal to noise ratio) as

Tatol noise power at output

Noise power at output due to source only

in

If we, only consider the drain current noise of the M1 and P1, the noise figure of the LNA can be presented as [20]

where

C

_t represents the overall capacitance at M1 drain, including the parasitic capacitance at M1 drain and the gate to source capacitance of P1,g is the _do drain-source conductance at zero VDS, the parameter γ has a value of unity at zero V_DS and, in long device, decreases toward a value of 2/3 in saturation. And the noise

contribution of the P1 is

It indicates that the noise contribution of P1 decrease with

C

_t, which can be decreased

by the LC tank and layout skill. In general,

C

_tis in the same order of the gate to

and the noise contribution of P1 becomes

2 contribution of P1 is much less than M1, in other word, M1 dominates the noise figure of the LNA. Thus, the first stage of LNA should choose appropriate width size to minimize the noise figure. The optimum M1 size can be calculated by the

,

which is about 280um if minimum channel length of 0.18

um

is chosen. And the width of the PMOS is selected as twice of the M1 because the transconductance of PMOS is twice smaller than that of NMOS.

2.2.3 Linearity and Variable Gain Mechanism

In the cascade architecture, the later stage plays a more important role than the former stage. Thus, a buffer stage M2 is added to increase the linearity of LNA. The transfer function for a short channel MOSFET can be expressed as [20]

( )

factor has a typical value in the range of 0.1-1V^-1. Expanding Eq.(2.10) in Taylor series and neglecting the DC component and harmonics higher than the third-order, we get the coefficients of the transfer function as

( )

The input referred third order intercept point of M2 is

( )( )

²

As shown in Eq.(2.13), the input referred third order intercept point of M2 increases with the gate to source voltage. But increase the gate to source voltage will lead to a rise in power consumption at the same time. So, M2 is designed quarter of the M1 to save power consumption and then to provide suitable output matching and increase the linearity.

The gain control is achieve by adjusting the gate voltage of the PMOS without affecting the bias condition and input matching which are determined by M1. Hence, the NF is not affected seriously when controlling the overall gain of the LNA.

Conventional cascode LNA do not have this flexibility in gain control. Gain control could only be achieved by altering the bias current of M1 and affecting the whole input noise and input matching that we do not desire.

There are two useful formulas presented in [21]

1 2

It reveals that NF decrease as

L

_sdecreases and

L

_g increases, but the power will increase as

L

_s decrease. There is a trade-off between noise figure and power consumption. This is a very valuable design guideline.

2.3 Layout Consideration

Layout is the heart of the RFICs. The layout affects the performance significantly for RF circuit due to the parasitic components at high frequencies. We should not only take all of these parasitic into simulation but minimize these effects as low as possible.

There are several essential common senses should keep in our mind. First, wide metal connection is avoided because this cause large parasitic capacitance to ground that may induce AC signal leakage. Second, transistor with a large width is split into several small transistors that reduce both the S/D junction area and the gate resistance.

Third, due to the lowest parasitic resistance, metal 6 is the best layer for RF signal.

Fourth, the spiral inductors are as far as possible to the other device (at least 50um).

Fifth, the active devices are protected by the guard ring to minimize the noise coupling from substrate. Finally, to reduce noise coupling from the noisy silicon substrate, the shield signal PAD shown in Fig.2.5 (b) is used.

(a) (b)

Fig.2.5 (a) Cross section of 0.18

um

CMOS technology (b) The shielded signal PAD

The low voltage LNA is implemented in TSMC 0.18

um

process. The final layout is shown in Fig2.6 that all elements are fully integrated on a chip including RFMOS, spiral inductor, metal-insulator-metal (MIM) capacitor and poly-resistance.

Since LNA is designed for on wafer measurement, layout is set in uni-directional mode. The RF input and output are placed on opposite sides of the layout to avoid the high frequency signal coupling. And GSG (Ground-Signal-Ground) pad structures are used in both RF input and output ports. The total chip size is 1.1mm*1.0mm.

DC Bias

RF In put RF O u tp ut

Fig.2.6 Layout of the low voltage LNA

2.4 Measurement Consideration

The LNA is designed for on-wafer testing, so the layout allocation must fit the requirement of the CIC’s probe station testing rules as shown in Fig.2.7. We use one 6-pin dc probe card and two GSG RF probes on CIC. The measurement arrangement for our design of the LNA is represented in Fig.2.8. The measurement setup is show in Fig.2.9, which includes high frequency S-parameters, noise figure, P1dB and two-tone IIP3 linearity testing. The circuit is designed a frond-end in 50

Ω

system for the measurement system. All of the matching devices are on-chip components and then we can easily integrate the other frond-end circuit such as mixer and synthesizer in future work. Since we have finished the measurements from CIC, we will discuss and compare the simulation and measurement results in the next section.

Fig.2.7 CIC probe station layout rule

6-pins dc probe card

GSG probe GSG probe

Fig.2.8 LNA measurement arrangement

(a) S-parameter

(b) Noise figure

(c) P1dB

(d) IIP3

Fig.2.9 Measurement setups for LNA

2.5 Simulation and Measurement Results Comparison

Fig.2.10 shows the simulation, measurement and modified simulation results of S21 and S11

Fig.2.10 Comparison between simulation and measurement of S21 and S11

We find that the S21 is appeared closely at the center frequency, but S11 is shifted down to the 1.7GHz. The simulation and measurement results are not meeting

the same way. Thus, we modify circuit parameters to fit the measurement results. By the Eq.(2.3), the larger inductor and gate to source capacitor the lower resonant frequency. Thus, a larger inductor and capacitor on the input matching network make the optimum matching peak of S11 shift down to the low frequency. We try to increase the inductors of M1 to fit the measurement results. Fortunately, the modified simulation results can achieve closed results as measurement. Therefore, we can prove the larger inductance appears in the input matching network make the frequency shifting. This may come from the incorrect model of the on chip inductor and the large parasitic inductor from the long RF line in the input matching network.

Although through the layout parasitic extraction (LPE), we still can not accurately predict the parasitic effects in the high frequency region. The larger parasitic inductor and capacitor can be avoided by advanced layout skill that is a worthy goal for designer to learn. Because of the resonant frequency of the LC tank is closed to 2.45GHz, the S21 parameter closely falls on desired band. And there are three possible reasons make the value be -15dB lower than simulation. First and the major reason is the frequency shifting of S11. Second, the inductance of

L

_dpand

L

_out is smaller than we expected. Third, the Q value of the LC tank is not good enough with the LNA layout design, that making the RF signal loss to ground.

Fig.2.11 shows the simulation, measurement and modified simulation results of S22 and S12. The peak of the output matching S22 is shifted down to 2GHz and is -10dB at 2.45GHz. By the modified simulation, we can find the smaller inductor and capacitor on the output matching network make a -10dB reduction. Although -10dB is achieved, it is enough for applications. From above discussion, the correct model for the on chip inductor is the most important in the LNA design. The S12 is as good as simulation results that prove the folded cascode configuration can provide good

isolation as the conventional cascode configuration.

Fig.2.11 Comparison between simulation and measurement of S22 and S12

The noise figure is measured from 100MHz to 3GHz as shown in Fig.2.12.

The noise performance is not good, rising to 6.22dB at high gain mode. The major reason is the gain of the LNA is only 2.21dB that can not suppress the noise contribution. And the measurement result is a little higher than modified simulation results. This is because the transistor model is not accurate enough which only

consider the thermal noise and gate induced noise is not included. But the peak value of noise figure is almost appeared at the center frequency. That is because the peak value of S21 is close to the center frequency. Thus, if we can achieve enough gain, the noise figure may go down to anticipated value below 2.5dB.

NF

Fig.2.12 Comparison between simulation and measurement of NF

The LNA design can achieve better dynamic range and linearity of P1dB and IIP3 parameters in measurement than those in simulation. As shown in Fig.2.13, the modified simulation and the measurement results are almost the same, the IIP3 is 8dBm at the high gain mode and 15dBm at the low gain mode. Of course, that is due to the lower gain performance cause the high linearity. The difference of linearity between high and low gain mode is 7dB, being almost the same as simulation. Thus, the function of the linearity release is work. And the performance of the simulation and measurement is summarized in the Table 2.1. The total power consumption is 7.27mw at the high gain mode and 5.06mw at the low gain mode.

P1dB

Fig.2.13 Comparison between simulation and measurement of P1dB and IIP3

Table 2.2 shows the comparison of this work and recent LNA papers. Because the difference between simulation and measurement results, both data are showed.

According to the simulation results, power consumption and the noise figure is the lowest one. The forward gain, input matching, output matching are designed at a suitable value above 15dB. And the most important performance, noise figure, is designed to a lowest value. Although linearity is not good enough, it is in the specification for Bluetooth and 802.11b applications. Because of the linearity of the receiver is dominated by the later stage as mixer, our goal is to design a LNA with low

Simulation Measurement

Specification High gain mode

frequency(GHz) 2.45 2.45 2.45 2.45

S21 (dB) 17.5 12.8 2.21 -4.38

Table 2.1 Measurement and Simulation results Summary

REF [16]

Condition Sim. Meas. Meas. Meas. Sim. Meas. Sim.

Table 2.2 Comparison of recent LNA papers

Chapter 3

0.7V 2.45GHz Mixer

In this chapter, we will present a 0.7V mixer designed and fabricated in TSMC 0.18 mµ CMOS process. Like the design method applied in low voltage LNA, the

In this chapter, we will present a 0.7V mixer designed and fabricated in TSMC 0.18 mµ CMOS process. Like the design method applied in low voltage LNA, the

在文檔中 應用於藍芽系統之超低電壓(0.7V)可調增益低雜訊放大器及混頻器設計 (頁 18-0)