Conclusion and Future Work
7.2 Future Work
7.2 Future Work
After this research, the following researchers may keep on discussing other
analog parameters such as high-speed analog circuits, power dissipation analysis, cut
off frequency (fT), gm/Id, linearity, noise, logic delay, NBTI, PBTI and analog
reliability. However, some of those issues may trade-offs for mixed mode application.
How to make your choice is important for device designers. Maybe one day, it is
possible to create a standard mixed mode process.
The work has been finished about complete investigation on the HC effects of
0.13µm technology. The characterization skills of charge pumping and gated diode
techniques could also be used to do more accuracy analysis for quantity of the charge
and postition. The following researchers will focus on this issue such that more
accurate analysis can be performed. To keep the pace with the advance of technology,
HCI on 65nm node or smaller should be an interesting issue. Another important
107
So for matching degradation behavior, here it was only showed the impact after
HCI stress, there still many failure mechanisms from the device reliability viewpoint.
It will be more and more important in the industry today for device designers and
circuit designers. Since different products or processes have different concerns, for
example, analog circuit in DRAM will use the buried channel device, the NBTI will
not be a critical reliability limitation on device design. But for the next product stage
for DDR-III , the PMOS will be surface channel device. Therefore in that time, such
mismatching degradation will be an import topic for designers. Thus, there is room
for further investigation on those points. We fall into three categories as follows:
1. Matching performance should be considered under PBTI stress for
nMOSFETs and NBTI stress for pMOSFETs.
2. Matching performance of different layout structures should be considered
under the same stress case (HCI, PBTI, and NBTI).
3. Matching performance of different process steps or technologies also should
be considered under the same stress case (HCI, PBTI, and NBTI).
CMOS device is one of the candidates chosen to serve for the next generation of
wireless communications, especially for the upcoming system-on-a-chip (SoC) design
in which RF subsystem, mixed-mode subsystem, and digital subsystem will be
implemented on the same chip. To achieve a better performance of the analog
subsystem with current process major for the digital logic circuit, it is still a lot of
works needed to do.
109
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學經歷
(Reliability investigation for process improvement and on analog circuit application)