4.1 Introduction
It is well known that, under certain bias conditions, hot-carriers in a
metal-oxide-semiconductor (MOS) transistor will result in property degradation
due to damage in the gate oxide and its interface. Owing to the increasing phonon
scattering during the carrier’ movement, the substrate current (Ib) and hot-carrier
degradation of metal-oxide-semiconductor field-effect transistors (MOSFETs) are
prevalently believed to be smaller at elevated temperatures [1][2]. However, the
degradation of saturation drain current (Id,sat) at high temperatures was reported to
be larger due to the reduction of velocity saturation length, whereas the
degradation of linear drain current (Id,lin) was still smaller with increasing stress
temperatures [3][4]. Other related studies showed that the hot-carrier effect had a
transition point (voltage), which reversed the dependence of a MOSFET’s Ib on
temperature [5][6]. This finding was proved with the result in which the peak Ib
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correlated with the degradation and lifetime [5][6]. These seemingly consistent
findings now face new challenges as we examine the results of DC hot-carrier
stress on nMOSFETs of nanometer technology.
In this study, we found that the drain current degradation at room temperature
for 32 A gate oxide devices is still the worst condition by comparing to devices
stressed at high temperatures, regardless of whether the stressed drain voltage is
lower or higher than the transition point. Furthermore, for the first time, we show
that the hot-carrier degradation of Id.op is the worst case among those of Id,sat, Id.lin,
and Id.op from room temperature to as high as 125oC. This result should provide
valuable insight to analog circuit designers.
4.2 Experimental
Tested devices were based on logic technology. The nMOSFETs used in our
experiments have an effective channel length of Leff = 120nm with a gate oxide
thickness of 32A (I/O devices) and Leff = 90nm with a gate oxide thickness of 20A
(core devices), all with a width of W = 10 um. Stress conditions were (1) 25, (2)
75, and (3) 125oC, with all Vg is biased at the peak Ib. The measurement conditions
are summarized in Table I. The Id.op in the table is defined to simulate the bias
condition often used in analog circuits such as small-signal amplifiers and class-A
power amplifiers. Here, Vg is biased at the threshold voltage (Vt) plus 0.2V of
driving voltage
4.2.1 I/O devices
For 32A, 120nm input/output (I/O) devices, Figs. 1-3 show the experimental
substrate currents versus Vg at room and elevated temperatures for three different
drain voltages. When Vd = 2.2 V, a higher temperature causes a higher Ib. However,
when Vd = 3.0 V, a higher temperature causes a lower Ib. At Vd = 2.6 V, substrate
currents are almost independent of temperature. This voltage can be thus defined as
the transition point. The behavior of Ib versus Vg at different temperatures is
consistent with the findings of the previous studies [5][6].
As for the drain current degradation, Fig. 4 shows an example of the stress
bias set higher than the transition voltage (2.6 V). It is clear that Fig. 4 shows no
reverse temperature effect. The degradation of drain current at room temperature is
still more serious than the degradations of higher temperatures. The velocity
saturation length effect is not shown here [3][4]. In fact, not only on Id,sat, Fig. 5
shows the degradation ratios of three drain currents, Id,sat, Id.lin, and Id.op, after
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the worst case for digital circuit considerations. Also note that the trends in Fig. 5
clearly indicate that the room temperature situation is the most aggravated
condition.
In the case of the drain bias set lower than the transition voltage, Fig. 6 still
shows no reverse temperature effect at Vd = 2.2 V, in contradiction to a higher
temperature possessing a higher Ib. In addition, room temperature still reveals the
largest degradation among different temperatures for three types of drain current
as revealed in Fig. 7. Again, I!d.op is still the worst case among the three currents and Id.lin is worse than Id,sat.
Actually, in the case of the drain bias set at the transition voltage, i.e., Vd =
2.6 V, the results are the same as above.
4.2.2 Core devices
For 20A˚, 90 nm core devices, Fig. 8 shows the experimental substrate
currents versus Vg at room and elevated temperatures for Vd = 2.2 V. Here, a
higher temperature causes a higher Ib. In fact, for Vd = 1.8 and 2.0V experiments, a
higher temperature also causes a higher Ib, and the waveforms of Ib are very
similar. No further higher Vd was tested in order to avoid inducing oxide
breakdown. Therefore, it is presumable that there exits a transition point above Vd
= 2.2 V, and the reverse temperature effect is consistent with previous findings of
Aminzadeh and Wang [5][6].
Figure 9 shows the experimental Id,sat degradation versus stress time at
different temperatures stressed at Vd = 2.2 V. As expected, the degradations
increased as temperature rose from 25 to 125oC due to the reverse temperature
effect. Figure 10 shows the degradation ratios of drain currents at different
temperatures. Among them, the degradation of Id.op at 125oC is the worst case. For
digital circuits, Id.lin is worse than Id,sat.
4.3 Discussion and Conclusions
Although further studies spanning other nodes of technologies and sizes are
required, the study at least shows the complicated nature of hot-carrier effects. The
significant facts revealed here are (1) Ib commonly accepted as the parameter for
monitoring the drain avalanche hot carrier (DAHC) effect [7][8] needs to be
modified since Id degradation and Ib variations versus temperature have different
trends as shown for I/O devices here. This may be attributed to some holes flowing
to the gate oxide through the velocity saturation region, as was suggested by Koike
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formulation considering all holes of impact ionization flowing to the substrate [10]
may not reflect all the facts. However, if this problem is intended to be completely
solved, the question that needs to be dealt with is how the impact ionization and
two-dimensional electric field in the velocity saturation region are affected by
temperature and drain voltage variations. (2) In this paper, we show that, using
32A˚ I/O devices of 0.13um technology as an example, the hot-carrier degradation
of Id.op at room temperature is the worst case for temperature varying from 25oC to
an elevated value of 125oC and among Id.op, Id,sat and Id.lin, regardless of the
existence of the reverse temperature effect. (3) For the devices having a gate oxide
thinner than 20A˚ , the transition points are high above the operational voltages
and approach the edges of breakdown. Hence, the worst condition in considering
hot-carrier reliability should be placed at elevated temperatures.
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Fig. 1: Substrate current vs. gate voltage for Vd = 2.2V.
Fig. 2: Substrate current vs. gate voltage for Vd = 2.6V.
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Fig. 3: Substrate current vs. gate voltage for Vd = 3.0V.
Fig. 4: △Id,sat versus stress time at Vd = 3.0 V with different temperatures.
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Fig. 5: Drain current versus temperature at Vd = 3.0 V after stress 5000 seconds.
Fig. 6: △Id,op versus stress time at Vd = 2.2 V with different temperature.
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Fig. 7: Drain current degradation versus temperature at Vd = 2.2 V after stress 5000 seconds.
Fig. 8: Substrate current vs. gate voltage for Vd = 2.2 V.
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Fig. 9: △Id,sat versus stress time at Vd = 2.2 V with different temperatures.
Fig. 10: Drain current degradation versus temperature at Vd = 2.2 V after stress 5000 seconds.
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