6.1 Introduction
The mismatch properties of metal–oxide–semiconductor field-effect
transistors (MOSFETs) on the same wafer are great concerns for both manufacturers and designers, particularly when the wafer is carrying analog
circuits. The mismatches due to process variations are most commonly known
[1][2][3]. Another popular factor being considered is the effects of size on parameters such as channel length, width, gate area, and layout type
[2][3][4][5][6]. However, it is known that hot-carrier injection (HCI) in normal
operation will degrade MOSFET performance, but the mismatches due to this effect have not been fully explored. In perhaps the sole example of a related study, the mismatches of the parameters β (current gain factor) and Vt (threshold voltage)
due to HCI in nMOSFETs of one size were reported to monotonously increase with stress time [7]. It was concluded that the HC-induced transistor mismatches
have a great impact on the reliability of analog circuits, such as those having
mirrored transistors [7].
In this paper, we present the impact of hot carrier stress on the mismatch
properties of n and p MOS transistors with different sizes produced using 0.15 u
complementary MOS (CMOS) technology. The considerations particularly focus
on the concerns of analog applications.
6.2 Experiments
Test devices, nMOSFET and pMOSFET pairs, were fabricated using a 0.15
um CMOS process. Source/drain and extension structures were formed by arsenic
implantation for nMOSFETs and boron implantation for pMOSFETs. Devices in
each pair are adjacent to each other with a gate oxide thickness of 2.6 nm and a
minimum feature size of 0.15 um. In totally, 40 pairs of transistors having
identical layout structures with W/L =1/0.15, 1/0.5, 5/0.15, and 5/0.5 um, half n
and half p, on the same wafer were stressed to investigate the impact of HC on
mismatch properties. HCI stressed at 25 oC and up to 5000 s was performed using
the gate voltage Vg at maximal substrate current Isubmax while the drain was biased
at 2.4 V, and the source and substrate were grounded. [Often this kind of stress
condition is called drain avalanche hot carrier (DAHC).] After each stress period,
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was measured at Vg = Vt,op + 0.3V with Vds = 0.75V for all nMOSFETs; both
Vt,op and Ids,op were designed to simulate the operating conditions of analog
circuits, such as MOSFETs in small-signal amplifiers and class-A power
amplifiers. For pMOSFETs, the stress and measurement conditions were the same
except that Vds and Vg were negatively biased.
6.3 Results and Discussion
After some statistical arrangement of the tested data, the results are shown in
the following graphs and tables. Figures 1 and 2 show the standard deviations
of Vt,op and Ids,op! /Ids,op for all the related pairs. Although it is a common practice to express the mismatches in terms of 1= (gate area)^0.5 here the
distributions of the standard deviations are obviously not so uniform, to some
degree implicating the irregularity of the mismatch itself for deep submicron and
beyond devices. However, on the basis of their channel length and DAHC effect,
these can be interpreted as the following. For L = 0.15 um devices, 0.15 um is the
critical minimal length of this technology, so they should reveal larger standard
deviations than L = 0.5 um devices. This should also be the reason why, even for
the before-stress case, the shorter-channel-length devices exhibit higher levels of
standard deviation than their counterparts. In addition, because the DAHC effect is
proportional to the substrate current, which means that it is also proportional to
drain current and to the reciprocal of channel length [8], the longer-channel-length
devices showing much less variations in standard deviation after stressing seem
reasonable. Even so, the slopes of these lines, called area factors (or area
proportionality constants) [3][4] of corresponding properties as defined in eq. (1),
mostly have the same trends in spite of their differences in channel length or
differences before/after applying stress.
As stated in the above interpretation, since the shorter-channel devices are
more critical and more degraded due to DAHC, we shall focus our attention on the
L = 0.15 um devices from now on. From Figs. 1 and 2, one can observe that, for
nMOSFETs, the standard deviations of Vt,op and ! ∆Ids,op/Ids,op are enlarged after stress, which means that the mismatches of all transistor pairs are worse after
HCI. However, in the case of pMOSFETs, the changes are much smaller, although
they possess higher degrees of mismatch initially. The reason for initial
mismatches should be the contributions of irregular boron penetration, and the
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massive impact ionization. The latter is consistent with test data because we
recorded Isubmax values of pMOSFETs that were almost two orders of magnitude
smaller than those of nMOSFETs, and the ratios of Isubmax/Ids are about 20 times
smaller for the same DAHC biases and sizes.
A hint that may be valuable to an analog circuit designer is the after-stress
lines of n and pMOSFETs exhibit a cross point in the Vt,op figure, which means !
that the Vt,op mismatches are the same for the same gate area. It is suggested that
the cross point can be used to indicate the minimal size at which n and p pairs will
have the same or smaller degree of Vt,op mismatch in designing analog circuits
such as when a push–pull amplifier is involved. For the present case, the minimal
gate area should be 0.18 um2 (implying that the minimal width should be 1.22 um at this critical short channel length) at about !σ(∆Vt,opT) = 10 mV. For
∆Ids,op/Ids,op, it is difficult to find a cross point in Fig. 2, but the methodology
can still apply for other processes if Ids,op mismatch is to be considered first.
The mismatch characteristics of the area factors of n and pMOS transistors at
L = 0.15 um are summarized in Table I. All the positive area factors in Table I
reveal that the smaller the gate area WL is, the larger the mismatch will be. One
would also observe again that the mismatches of nMOSFETs are obviously
degraded after HCI, whereas the mismatch changes are minor and even better for
pMOSFETs. The table provides conveniences for designer to forecast the
mismatches of different sizes and can be used to compare with other factors also
causing mismatches. More details will be given in the following paragraphs.
For nMOSFETs, Figs. 3 and 4 can help explain the fact that the difference in
local damage is increased with stress time due to random variations in the number
and spatial distribution of electron traps formed near the drain region. Because of
this, the mismatch parameters are inclined toward becoming worse. The means of
the threshold voltage shifts and drain current degradation ratios of stressed
transistors at each size increase with stress time due to increasing electron trap density. Another observation is that the σ and means of the after-stress Ids,op of
nMOSFETs become significantly higher than the values before stress. The σ
enlargement of Ids,op also outweighs the changes in Vt,op. This is because the Ids variance is dominated by two factors, the variance in ∆Vt and the variance of ∆β
(change in current gain factor). However, ∆β is directly dependent on
∆µ [3][9][10] (change in mobility). Hence, we can conclude that the mobility
mismatch of nMOSFETs is greatly degraded after HCI.
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back and forth across the zero line particularly before the stress time reaches about
500 s. This indicates that not only holes but also electrons surmount the oxide
barrier to become trapped at the silicon–oxide interface and maybe into the oxide
near the drain region, and the holes and electrons compensate or compete with
each other on their influences on the change in Vt,op. Specifically, it is
presumable that the electrons are trapped inside the oxide, but the holes are
trapped at the Si–SiO2 interface to damage the channel mobility. Thus, even
though Vt,op zigzags around the zero line, Ids,op does not reveal any enhancement
but only continues its degradation. For the stress time after 500 s, it is also
presumable that the holes trapped at the interface become dominant and both Vt,op
and Ids,op degrade rapidly. Actually, the above findings and inferences agree well
with the pMOSFET HC mechanisms proposed by Woltjer[11] and later proved by
Polishchuk.[12]
An exception about the mismatches of drain saturated current Ids,sat is
worthy to disclose. Whereas the Ids,op of nMOSFETs exhibits a clear mismatch
degradation, the Ids,sat portion is small and random as shown in Fig. 7. At the
same time, the means of Ids,sat degradation ratios are apparently lower than the
means of Ids,op degradation ratios in Fig. 4. Figure 8 shows the same situation of
pMOSFETs as that in nMOSFETs. The above phenomena may be due to the
velocity saturation length of MOSFETs covering parts of the HC-damaged region.
This kind of mechanism has been used to interpret the anomalous HC degradation
of nMOSFETs at elevated temperatures.[13] Figure 9 shows a schematic drawing
depicting such a concept. Since velocity saturation length L increases as long as !
the MOSFETs are operated at Vd > Vd,sat and the saturated velocity is not liable
to be influenced by the interface states and oxide-trapped charges, the Ids,sat
mismatches after HC stress being considerably less degraded than the Ids,op of n
and pMOSFETs seems reasonable.
6.4 Conclusions
For the first time, we thoroughly present the impact of hot carrier stress on
the mismatches of the analog properties of n and p MOS transistors with different
sizes produced using 0.15 um CMOS technology. Comparing the mismatched
standard deviations with the means of the HC effect in each of Figs. 3–8, one
would not find it difficult to conclude that the HCI does degrade the matching
properties of MOSFETs. The degrees of degradation closely depend on the
strength of the HC effect. Therefore, under the stress condition of DAHC, the
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together may reveal cross points such as in Fig. 1. The cross points can be used to
indicate the minimal size at which n and p pairs will have the same degree of
mismatches in the design phase, such that circuit performance can be more
reliable.
Finally, the mismatch changes in Vt,op are believed to be due to the random
variations in the number and spatial distribution of trapped charges at the
silicon–oxide interface and inside the oxide. In addition to the threshold voltage
shift factor, the reasons of mismatch changes in Ids,op need to add the effect of
charges at the interface, which induce the degradation of mobility through the
scattering effect and aggravate the Ids,op mismatches. However, because some of
the interface charges are covered by the velocity saturation length and make them
ineffective, the mismatches of Ids,sat are obviously smaller than those of Ids,op.
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Fig. 1 Vt,op mismatches vs 1/(W*L)^0.5 gate area. Channel length/width and before or after stress of the tested data are indicated. The cross point of n and p MOS after-stress lines indicate the minimal size at which devices with a 0.15 um channel
length will have the same or smaller mismatches.
Fig. 2 Ids,op mismatches vs 1/(W*L)^0.5. The notation is the same as in Fig. 1. Note that the σ values of nMOSFET pairs particularly on L = 0.15 um devices are much
more aggravated than those of pMOSFET pairs after stress although they possess higher degrees of mismatch initially.
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Fig. 3 Time history of mismatches of ∆Vt,op of each transistor pair and means of Vt,op shifts of tested nMOSFETs. The mismatches and particularly the means of Vt,op shifts increase with stress time for nMOSFETs of L = 0.15 um. The data at t = 1
s corresponds to the mismatch before HCI stress. This is also applicable for Figs. 4 to 8.
Fig. 4. Time history of mismatches of ∆Ids,op/Ids,op of each transistor pair and means of Ids,op degradation ratios of tested nMOSFETs. The mismatches and the means of Ids,op degradation ratios increase with stress time for nMOSFETs of L =
0.15 um.
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Fig. 5 Time history of mismatches of ∆Vt,op of each transistor pair and means of Vt,op shifts of tested pMOSFETs. The Vt,op mismatches due to HC show different trends for different sizes, and the means of Vt,op shifts abnormally switch back and
forth across the zero line and are smaller compared with those of nMOSFETs.
Fig. 6 Time history of mismatches of ∆Ids,op/Ids,op of each transistor pair and means of Ids,op degradation ratios of tested pMOSFETs. The Ids,op mismatches due to HC
show different trends for different sizes, and the means of Ids,op shifts are smaller compared with those of nMOSFETs.
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Fig. 7 Time history of mismatches of ∆Ids,sat/Ids,sat of each transistor pair and means of Ids,sat degradation ratios of tested nMOSFETs. The variations of mismatches and the means of Ids,sat degradation ratios are smaller than those of
Ids,op in Fig. 4.
Fig. 8 Time history of mismatches of ∆Ids,sat/Ids,sat of each transistor pair and means of Ids,sat degradation ratios of tested pMOSFETs. The variations of mismatches and the means of Ids,sat degradation ratios are smaller than those of
Ids,op in Fig. 6.
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Fig.9 Schematic illustration showing that velocity saturation length ∆L will cover portion of local damage region.