Future work

Figure 1-1 Logic technology node and transistor gate length versus

calendar year.[1]

Figure 1-2 Transistor cost and lithographic tool cost versus years.[1]

Figure 1-3 Gate-current density against effective-oxide thickness with

various gate materials.[7]

Figure 1-4 Correlation of dielectric constant with band gap of candidate

[8].

Ge Si GaAs InSb InP

Bandgap (eV) 0.66 1.12 1.42 0.17 1.35

Electron affinity (eV) 4.05 4.0 4.07 4.59 4.38

μ_h (cm²V^-1s^-1) 1900 450 400 1250 150

μe (cm²V^-1s^-1) 3900 1500 8500 80000 4600

N_V (cm^–3) 6.0 x 10¹⁸ 1.04x10¹⁹ 7.0x10¹⁸ 7.3x10¹⁸ 1.1x10¹⁹ NC (cm^–3) 1.04x10¹⁹ 2.8x10¹⁹ 4.7x10¹⁷ 4.2x10¹⁶ 5.7x10¹⁷

Lattice constant (nm) 0.565 0.543 0.565 0.648 0.587

Dielectric constant, k 16.0 11.9 13.1 17.7 12.4

Melting point, T_m (°C) 937 1412 1240 527 1060

Table 1-1 Material characteristics of alternative channel materials.[17]

Chapter 2

Experiments

Before going deep into the characterization of gate dielectric on Si and Ge MOSFETs, The experimental instrument, analysis method and parameter extraction are described in this chapter.

2.1 High-pressure H

2

O system

In this work, a high-pressure H2O treatment is proposed as a post-gate dielectric treatment at 100~150°C to improve the electrical performance of gate dielectric on Ge substrate. Figure 2-1 shows the proposed high-pressure system. High-pressure H2O treatment was conducted using supercritical carbon dioxide (SCCO2) fluid that was mixed with 10 volume % of propyl alcohol and 10 volume % of pure H2O at 100~150 °C for 1 hour. In this section, author will introduce the properties of SCCO2 and high-pressure H2O.

A supercritical fluid can be defined as a substance heated above its critical temperature (TC), and which is also compressed above its critical pressure (pC). At the critical point, the fluid phase boundary between liquid and gaseous phase vanishes, and the properties of the new single “supercritical” phase are best described as a combination of those of liquid and gaseous phase.[29] Therefore, supercritical fluid provides good liquid-like solvency and high gas-like diffusivity, giving it excellent transport capacity.

In this work, author used SCCO₂ for carrier of H₂O due to its low T_C (30 °C), p_C (1072

psi) and environmental benefits, such as no waste, no damage of ozone layer, non-carcinogenic, non-toxic and non-flammable. The properties of SCCO2 are shown in Figs.

2-2 and 2-3. The solubility of H2O rises with increasing the CO2 pressure due to the density increase, as shown in Fig. 2-3. The propyl alcohol was used as a modifier to enhance the solubility of the polar H2O molecules in nonpolar CO2. The water was dissolved as small H2O molecule clusters with propyl alcohol assistance and uniformly mixed in SCCO2 fluid. The SCCO2 fluid exhibited a liquid-like property, giving it an excellent transport capacity. Also, supercritical fluid has gas-like properties and efficiently diffuses into nanoscale structures without damage. Therefore, the H2O effectively reacts with the thin film when dissolved in SCCO2.

It is also noted that high-pressure H2O has quit different properties to ambient. Figure 2-4 shows the ionic product of water at high temperature and high pressure.[29] The amounts of ionic products, H3O⁺ and OH⁺ radicals, in H2O at high pressure may be orders of magnitude higher than those obtained in ambient water. The higher amounts of free radicals are associated with a strengthened oxidation reaction between H2O and non-oxidized thin film owing to the higher collision frequency.

2.2 X-ray photoelectron spectroscopy

Of all the contemporary surface characterization methods, X-ray photoelectron spectroscopy (XPS) is the most widely used. XPS is also called electron spectroscopy for

chemical analysis (ESCA), and the two acronyms can be used interchangeably. The popularity of XPS as a surface analysis technique is attributed to its high information content, its flexibility in addressing a wide variety of samples, and its sound the sound theoretical basis.

XPS analysis provides useful information such as composition, chemical state, and thickness etc. of thin films. In this article, author used XPS analysis to exanimate the composition-depth profile and chemical states of gate dielectric on Ge substrate with various post gate treatment and further discriminate the chemical reaction within gate dielectric. The brief principle and main functions of XPS used in this article will be introduced as following content.

The principle of XPS is based on the photoelectric effect outlined by Einstein in 1905 where the concept of the photon was used to describe the ejection of electrons from a surface

when photons impinge upon it. This process can be expressed by the following equation,[30]

E_B^vac= ℎ𝑣 − KE + 𝜙_𝑒 (1)

Where EB is the binding energy of the electron in the atom, hv is the photon energy of X-ray source, KE is the kinetic energy of the emitted electron that is measured in the XPS spectrometer and ϕe is the spectrometer work function. The energy of the photoelectrons leaving the sample is determined using an analyzer and this gives a spectrum with a series of photoelectron peaks. The binding energy of the peaks is characteristic of each element. The peak areas can be used to determine the composition of the materials surface. The shape of each peak and the binding energy can be slightly altered by the chemical state of the emitting

atom. Hence XPS can provide chemical bonding information as well.[30] charged, resulting in an increase in binding energy.[31]

2.3 Parameter extraction

There are three parameters were presented in characteristics of MOS capacitors, namely capacitance-equivalent thickness, flat-band voltage and hysteresis.

The capacitance-equivalent thickness (CET) is defined as following formula, C_𝑎𝑐𝑐 = ^𝜀_𝐶𝐸𝑇^{𝑆𝑖𝑂2} =^{𝜀𝐷𝑖𝑒𝑙𝑒𝑐𝑡𝑟𝑖𝑐}_𝑑

𝑃𝐻𝑌 (2)

Where Cacc is measuring capacitance of per cm² at accumulation region, ɛSiO2 is the permittivity of SiO2, and ɛDielectric is the permittivity of gate dielectric deposited on Si or Ge substrate and dPHY is the physical thickness of gate dielectric.

The flat-band voltage (VFB) was extracted at flat-band capacitance (CFB) given as

Where CD,FB is the capacitance at depletion region, ɛSbustrate is the permittivity of substrate, LD

is Debye length and Nsub is the substrate doping concentration.

The value of hysteresis (△VFB) was defined as difference of VFB for forward and reverse

gate bias sweeping. The hysteresis is related to border traps in gate dielectric. The border traps in near-interfacial oxide are in charged or discharged state by rapid electrical communication with Si or Ge substrate, causing hysteresis behavior during forward and reverse C-V sweeping.

2.4 Experimental Designs

In the Chapter 3, different nitrogen profiles (N-profile) within SiON were fabricated to explore the N-profile effect on gate tunneling current. The buffer oxide layer was firstly growth by dry-oxidation and nitridation was performed by plasma method. After nitridaion of gate dielectric, the re-oxidation process was performed and oxygen-rich nearly Si substrate was therefore formed. The shapes of N-profile within SiON can be modulated through control thickness of buffer oxide layer and process of re-oxidation. Additionally, the effect of stress memorization technique (SMT) on SiON for Si-MOSFETs was also examined in Chapter 3.

Two NMOSFETs with different strain level were compared to investigate the effect of strain on gate tunneling current. The different strain level of SMT transported in channel region were modulated by control thickness of buffer oxide under strain nitride capping films.

In the Chapter 4, the effect of high-pressure (HP) H2O treatment on gate dielectric upon Ge substrate was systematically investigated. The HP H2O treatment was respectively

performed on SiO2/Ge stack for exploration of Ge substrate, on ZrO2/Si for exploration of ZrO2 thin film and finally realized on ZrO2/Ge capacitors. Additionally, the thermal stability of gate dielectric on was examined by rapid thermal annealing system and vacuum annealing system. After investigate the effect of high-pressure H2O treatment, it is observed that the H2O and H2 were helpful to eliminated GeOX formation and reduce gate leakage current after thermal annealing. Further, the H2O and H2 were added into RTA system and presented in Chapter 5 to verify the suppression of GeOX formation with H2O and H2 ambiences.

Figure 2-1 The high-pressure H

2

O system.

Table 2-1 The critical temperature and pressure of various substances.

Figure 2-2 The pressure and temperature phase diagram of CO

2

.

Table 2-2 The density, diffusivity and viscosity of CO

2

at various phases.

Psi

Figure 2-3 The plot of density variation with respect to pressure and temperature for CO

2

.[29]

Figure 2-4 The ionic product of water at high temperature and high

pressure.[29]

Figure 2-5 The example of binding energy shift with oxide formation.[32]

Chapter 3

Ultrathin Nitrided Oxides for Si-based MOSFET

3.1 Review and motivation

Improvement of Si-based MOSFETs was initially achieved by simply reducing the physical thickness of SiO2 as gate dielectric layer. The downscaling of dielectric thickness causes gate tunneling-current (Jg) to increase exponentially and boron penetration issue to emerge. This poses incredible challenge to continue with device scaling. To overcome these issues, silicon oxinitride (SiON) was firstly adopted. Downscaling continues with the scaling of physical thickness and increasing nitrogen concentration within SiON. Nevertheless, excessive nitrogen concentration poses several issues of device and reliability, such as severe threshold voltage shift, lower mobility and degraded Negative Bias Temperature Instability (NBTI) [33]. Hence, the need to control N-profile in ultra-thin SiON becomes more and more critical [5]. Successful N-profile engineering will definitely alleviate these issues mentioned [6].

Additionally, the introduction of stressors to boost mobility has received a lot of attention in recent years. Stressors can be introduced in two key forms, the bases of the substrate strain and the process-induced strain. The substrate-strain based makes use of material with different lattice spacing, such as SiGe/Si epitaxial stack, to generate biaxial strain in the channel. This method introduces a global strain to the substrate. It boosts mobility effectively, at the

expense of higher cost [11]. On the other hand, the process-induced strain based method provides a lower cost solution. They could appear in the forms of shallow trench isolation (STI), contact etching stop layer (CESL) and stress memorization technique (SMT), which introduce uniaxial strain to boost mobility [12-15]. Both nMOSFET and pMOSFET have different requirements in strain. N-type MOSFET performed better under the presence of tensile strain, while p-type MOSFET performs better under the compressive strain.

In this chapter, we explored the effects of N-profile and high tensile mechanical stress on ultra-thin SiON for 45-nm generation. Firstly, experimental results show that N-profile within SiON has different impact of gate tunneling current on nMOSFETs and pMOSFETs. A model based on Wentzel-Kramers-Brillouin (WKB) approximation was proposed to expound effect of N-profiles on gate leakage current. Secondly, although high tensile mechanical stress boots the channel electron mobility, experimental results show that mechanical stress causes higher gate leakage current for nMOSFT owing to induced damage in gate dielectric edge.

3.2 Modeling of nitrogen profile effects on ultrathin nitrided oxides

There are numerous publications on how gate tunneling-current could be suppressed through nitrogen incorporation. For the same effective oxide thickness (EOT), a lower tunneling-current is possible by increasing the nitrogen concentration. Numerous models have been proposed to explain the dependence of nitrogen dosage on gate-tunneling current [25-27].

In these models, uniformly distributed N-profile is normally assumed. Little attention has

been paid to study the influence of N-profile. Typically, the nitrogen profile is intentionally engineered to optimize the benefits in both device and reliability. In this article, the effect of different N-profiles within an ultra-thin SiON on the eventual gate tunneling-current will be investigated. A model based on WKB approximation^[28] will be proposed to answer why steeper N-profile produces higher Jg. Also, it will well explain the change of tunneling current by taking into consideration of the local variations in dielectric constant, band profile and effective mass.

To investigate the impact of N-profile to gate tunneling current, two kinds of SiON samples (“Sample-A” and “Sample-B”) with different N-profiles were fabricated. Sample-A had a steeper N-profile than Sample-B, as illustrated in Fig. 3-1. The N-profile was measured using high resolution angle-resolved XPS. To have a fair comparison, both thickness and N-dosage were kept equal. The corresponding electrical data in terms of EOT, inversion gate tunneling-current (Jg), and Jg-ratio (defined as Jg-A/Jg-B) are shown in the Fig. 3-2. Two key observations were made from the experimental data: firstly, Sample-A is having a higher Jg

than Sample-B, for both n- and pMOSFET. Secondly, Jg-ratio (defined as Jg-A/Jg-B) is higher in pMOSFET than nMOSFET, indicating pMOSFET has a higher sensitivity in Jg towards N-profile change. A model, based on the change of tunneling probability, arising from localized band bending, is proposed to explain these experimental data. This model was built based on Wentzel-Kramers-Brillouin (WKB) approximation,^[28] as will be explained as

follows.

In this model, WKB approximation is adopted to calculate the change of tunneling probability under various biasing conditions. The tunneling probability (Tt) could be

expressed by: effective mass and x≡distance into SiON, determined from Poly/SiON interface.

To solve Tt, two parameters: υSiON(x) and m*(x), under different biases must first be extracted. To simplify the model, several assumptions were made in this model. Firstly, the nitrogen concentration is assumed to vary linearly within the bulk of SiON. Secondly, the bulk of SiON is assumed to consist of “n” number of very thin SiON strips, with uniformly distributed nitrogen in each strip. Thirdly, the energy barrier height (υ), dielectric constant (ε) and effective tunneling mass (m*) for SiON are assumed to vary linearly with nitrogen dosage between oxide material constants and those for nitride, as reference to Philip A. et al.[27, 34]

Following that, the various input parameters could be simplified to:

 x a₁x a₂

where a1and a2are constants, and we can obtain a variety of linear N profile shapes by modifying those values. The N and NSiN are nitrogen concentrations (atom %) in the oxynitride film and the pure nitride film, respectively. The other used constants are summarized in the Table 3- 1 and Fig. 3-3. Substituting these parameters [φ(x), ε(x) and m*(x)]

into the main expression in Eq. (1), we could simulate the tunneling probability through the different potential barriers. Figure 3-4 and Figure 3-5 respectively shows the simulated N-profiles and corresponding band diagram under a bias (V^OX) of 0 V.

For VOX ≠ 0, Poisson’s equation shall be adopted to describe the non-homogeneous SiON with different N-profiles, as shown in Fig. 3-6. Therefore, the corresponding tunneling probability nMOSFET under VOX > 0 V and for pMOSFET under VOX<0 V can be simulated.

To examine our model, the case of two SiON samples with different N-profiles is considered, as depicted in Fig. 3-4. Both samples are having the equal nitrogen concentrations and thickness. Under zero bias (i.e., VOX = 0V), the simulated energy band diagram are shown in Fig. 3-5 and Fig. 3-6. The SiON sample with steeper N-profile exhibits a steeper conduction band (CB) and valence band (VB) bending. Take note that the degree of VB

bending is steeper than that of CB. This is attributed to the greater VB offset (than CB offset) difference comparing SiO2 to Si3N4, as shown in the Table 3- 1.

Under nonzero biasing (i.e., V_OX  0), there will be an additional voltage drops across the silicon oxinitride (VSiON). Hence, it is necessary to consider both υ(x) and VSiON(x) for constructing the potential barrier, while simulating the energy band diagrams. Considering minority carriers under operation mode (at low electric field),[35] the simulated tunneling probability for electrons (in nMOSFET) under positive biasing, and holes (in pMOSFET) under negative biasing are plotted in Fig. 3-7. These experimental results are also shown in Fig. 3-8. These I-V curves in Fig. 3-8 are the average results of five devices for each kind of samples. The gate current density (Jg) ratios of the steep profile to the smooth profile for n/pMOSFETs are also presented. The range of gate bias for measuring Jg ratios is just shown between -1.25 to -0.5V for pMOSFET and between 0.5 to 1.5 V for nMOSFET. The carrier transport mechanism in the bias range can be attributed to the direct tunneling behavior, which is verified by conduction processes fitting.[28]

According to simulated results, it shows that sample with steeper N-profile exhibits a higher tunneling probability, valid for both n- and pMOSFETs. This result agrees well with our experimental data in Fig. 3-8. On the other hand, defining the tunneling probability ratio (TP-ratio) as TPsteep/TPsmooth, it is observed holes (in the pMOSFET) have a higher TP-ratio than electrons (in the nMOSFET). In other words, SiON with steeper N-profile gives rise to a

higher JG increase. This is particularly true for pMOSFET because VB bending is more sensitive to N-profile change than CB bending, as predicted by our model.

3.3 Effect of high tensile stress on ultrathin nitrided oxides

The introduction of strain into the channel region does not only enhance the mobility of electrons and holes by altering the in-plane mass, it also changes the gate tunneling current by altering the out-plane mass and SiO2/Si barrier height. However, the change of strain will make a great impact on the gate tunneling current.[11] Previous articles have reported the reduction of gate tunneling current by introducing the tensile strain in nMOSFET.[13, 16] In the course of boosting nMOSFET mobility using SMT with high tensile strain, the gate tunneling current was also found to be increased at the same time. This is particularly evident when the channel is driven into accumulation mode. This observation is rather different from previous reports. In this study, two possible factors will be investigated to analyze the anomalously high gate tunneling currents. One is the strain-induced excessive lateral dopant diffusion, and the other is the strain-induced polysilicon gate damage at the edges.

The nMOSFET used in this work was fabricated using state-of-the-art CMOS processes.

The device went through the gate dielectric, gate poly, spacer and source/drain (S/D) formation.[36-38] The lightly-doped drain-source (LDD) and S/D regions were implanted with arsenic and phosphorous, respectively. High tensile SMT film is then deposited and followed by high temperature activation treatment. Process details can be found elsewhere.[15]

Two NMOSFETs (sample-A and sample-B) with different strain level were compared to investigate the effect of strain on gate tunneling current. Sample-A is having a higher tensile strain than Sample-B. Keithely 4200 Semiconductor Characterization System and Agilent 4294 Precision Impedance Analyzer are the key instruments used to extract various device parameters.

In Fig. 3-9 and Fig. 3-10, the electrical characteristics of nMOSFET devices show that Sample-A (with higher tensile strain) has approximately 4% higher mobility than Sample-B (with lower tensile strain). Figure 3-9 also shows that the sample with higher strain also exhibits a higher drain leakage current (Id-off) at off states. This is particularly evident when the device is biased at a linear mode (Vd=0.05V). Electrical measurement shows that the higher Id-off is mainly contributed from the higher gate tunneling current.

Carrier separation measurement was performed to identify the source and the type of carriers tunneling through the gate dielectric.[39] The gate tunneling current is plotted as a function of gate bias (Vg) in Fig. 3-11.The measured gate current could be divided into two distinctive regions. For the low Vg region, Sample-A exhibits a much higher Jg than Sample-B.

As Vg increases, the difference in Jg diminishes. Carrier-separation measurement shows electron and hole tunneling currents dominate at a low and a high gate biasing regions, as respectively shown in Fig. 3-12 and Fig. 3-13. At the low biasing region, the gate tunneling current flows primarily to the S/D regions. Sample-A is found to exhibit a higher gate

tunneling current than Sample-B. This could be originated from the different tensile strain. It has been reported that tensile strain from a SMT is huge at the gate edge.[16, 40] Therefore, it is reasonable to deduce that the anomalously high gate tunneling current in Sample-A is a result of higher tensile strain.

Figure 3-14 examines the gate tunneling current of nMOSFET devices with gate bias at -0.75 V for various channel lengths. The results show that the gate tunneling current is a function of channel length. As the channel length is decreased, the impact from strain becomes more evident. The mechanical stress induced by SMT is not only originated from the vertical compressive strain or restraining polysilicon gate from re-growth, it also comes from the tensile strain experienced by the S/D regime (SMT). This explains the dependence to channel length [41, 42]. In other words, the tensile strain experienced from SMT will be increased with the reduction of channel length, resulting in the increased gate tunneling current.

On the other hand, it is also observed that Sample-A is having approximately 9% higher gate-to-S/D overlapping capacitance than Sample-B, as shown in the Fig. 3-15. Excessive strain was reported to induce point defects, such as interstitials and vacancies in silicon. The presence of these defects assists dopant diffusion. Hence, both the tensile and compressive strain would influence the dopant diffusion behavior.[43] In our samples, the LDD was implanted with arsenic. The presence of higher tensile strain in Sample-A could enhance the

lateral arsenic diffusion. This explains Sample-A is having a higher gate-to-S/D overlapping capacitance. In addition, the change in overlapping capacitance increases gate tunneling current at gate edge.

Figure 3-16 shows transfer characteristics of Sample-A and Sample-B in the linear mode, at a drain voltage of 0.05V. The drain current of Sample-A is higher than that of Sample-B in

Figure 3-16 shows transfer characteristics of Sample-A and Sample-B in the linear mode, at a drain voltage of 0.05V. The drain current of Sample-A is higher than that of Sample-B in

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