Enhanced NBTI degradation by SMT in short-channel pMOSFET

gain will be achieved at the expense of poorer pMOSFET’s performance and reliability, particularly when the device dimension is continued being scaled.

Mobility enhancement from the introduction of stressor has received a lot of attention.

Stressors can be introduced in two main forms: substrate-strain based or process-induced strain based. The substrate-strain based makes use of material with different lattice spacing, such as SiGe/Si epitaxial stack to generate biaxial strain in the channel. This method introduces a global strain to the substrate. It boosts mobility effectively but at a higher cost [11]. On the other hand, process-induced strain based method provides a lower cost solution.

They could appear in the forms of shallow trench isolation (STI), contact etching stop layer (CESL) and stress memorization technique (SMT), which introduce uniaxial strain to boost mobility [14, 77]. Both nMOSFET and pMOSFET have different requirements in strain.

nMOSFET performed better under the presence of tensile strain, while pMOSFET performs better under the compressive strain. This article reveals that SMT enhances nMOSFET’s

performance. Nevertheless, the gain will be achieved at the expense of poorer pMOSFET’s

performance and reliability, particularly when the device dimension is continued being scaled.

The MOSFETs used in this work were fabricated using conventional CMOS processes.

SMT stack layer was introduced after source/drain implantation and followed by high temperature activation. Process details can be found elsewhere [15]. The impact of SMT process to device performance was examined from device’s transfer characteristics. Since NBTI is of growing importance for modern ICs,[78] the impact of SMT on NBTI will be the key focus in this section. Charge pumping measurement will also be performed to substantiate the NBTI results.

Figure A-5(a) shows the linear mode Id-Vg for nMOSFET with and without SMT, at a drain voltage of 0.05V. Figure A-5(b) compares the corresponding mobility, as inferred from Gm_maxT_ox parameters. It is evident that the incorporation of SMT boosts the device performance for nMOSFET. The SMT layer introduces an uniaxial tensile strain along the channel direction and enhances electron mobility. Figure A-6(a) shows the linear mode Id-Vg for a pMOSFET with and without SMT, measured at Vd = -0.05V. Similarly, fig. A-6(b) compares the holes mobility from Gm_maxT_ox parameters for pMOSFET. Result shows the introduction of SMT degrades pMOSFET performance by lowering holes mobility. In summary, the introduction of SMT produces tensile strain in the direction of channel. This tensile strain boosts electrons mobility but “retards” holes mobility. Figures A-7 and A-8 show

the Id-Vd plots for both nMOSFET and pMOSFET, respectively. Both were plotted to compare the effect of SMT. Device with SMT was found to enhanced Id-Vd performance, valid for both nMOSFET and pMOSFET. This is consistent with the observations in Figs. A-5 and A-6. Again, the different observation could be attributed to the presence of tensile strain, introduced by SMT.

In addition to device performance, the impact of SMT to NBTI was also assessed. The NBTI stressing was performed under a constant negative gate biasing with the source, drain and substrate terminals grounded. Stressing was carried out at elevated temperature of 125^OC.

Device is considered failed when its Idsat drifts by 10% from its initial value. Figure A-9 correlated to the generation defects at the Si/SiO2 interface during electrical stress. Interface traps could exist in the form of silicon trivalent dangling bonds [78]. The presence of tensile strain, introduced by SMT, could enhance the interfacial hydrogen release to form more interface traps than that without SMT. For long channel device, the difference in strain could

be relatively smaller. As the channel length is being scaled down progressively, the difference Fig. 5 data, showing better NBTI performance at shorter channel length. On the other hand, comparing samples with and without SMT, the difference in Dit0 is found to become larger as channel length shrinks. This verifies our model that the difference in tensile strain will be “felt more strongly” as the channel length shrinks. The key implication of this finding is that SMT incorporation boost nMOSFET’s performance but it degrades pMOSFET’s performance and NBTI at the same time. Degradation will be further enhanced as the device dimension continues to be down-scaled. So, removing the SMT over pMOSFET could be an option to bypass these issues.

Figure A-12 shows the lifetime of NBTI as a function of gate biasing for pMOSFET with short channel length of 0.06 μm. Devices with SMT device, has their NBTI lifetime deteriorates by 2-3 times. This result shows that if we pay much attention to nMOSFET

performance improvement and ignore the tensile stress impact in pMOSFET, it will not only degrade CMOS performance but also bring on reliability issues.

This article reveals that the SMT process increases the nMOSFET electrical performance (Id-Vg and Id-Vg) but at the expense of device performance and NBTI reliability for pMOSFET. In this study, we also clarified the dependence of NBTI on channel length. The incorporation of SMT causes more severe impact on pMOSFET, particularly when the device is continued becomes smaller.

Figure A-1 Schematic cross-sectional views of the proposed gated PIN

diode.

Figure A-2 Transfer characteristics and gate leakage current of p-channel

poly-Si TFT after NBTI stress for different time durations.

Figure A-3 Schematic operation regimes of the gated poly-Si PIN diode

under the junction reverse bias condition with gate sweeping.

Figure A-4 (a) Electrical characteristics, and (b) current variation of the

gated poly-Si PIN diodes under NBTI stress with time

progressing.

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Figure A-5 Comparison of (a) linear mode transfer characteristic (Id-Vg) and (b) mobility for nMOSFET with and without SMT.

- 0 .8 - 0 .6 - 0 .4 - 0 .2 0 .0 0 .2 0 .4 0 .6 0 .8

-145-

Figure A-6 Comparison of (a) linear mode transfer characteristic (Id-Vg) and (b) mobility for pMOSFET with and without SMT.

- 0 .8 - 0 .6 - 0 .4 - 0 .2 0 .0 0 .2 0 .4 0 .6 0 .8

Figure A-7 Output characteristics of nMOSFET with and without SMT.

Figure A-8 Output characteristics of pMOSFET with and without SMT.

0 .0 0 .2 0 .4 0 .6 0 .8 1 .0 1 .2

Figure A-9 NBTI lifetime for pMOSFET with and without SMT.

Figure A-10 Charge-pumping current versus base voltage for pMOSFET

with and without SMT.

Figure A-11 Maximum charge pumping current as function of channel

Curriculum Vitae

姓 名: 黃震鑠 Chen-Shuo Huang

性 別: 男

出生日期: 1979 年 09 月 24 日

出 生 地: 高雄市

地 址 : 高雄市林園區林園里仁愛路 248 號

學 歷 : 國立鳳山高中 1995 年 09 月~1998 年 06 月

國立中山大學物理學系 1998 年 09 月~2003 年 06 月

國立清華大學電子工程研究所碩士班 2003 年 09 月~2005 年 06 月

國立交通大學光電工程研究所博士班 2008 年 09 月~2011 年 06 月

論文題目: 閘極介電層於矽型與鍺型金氧半場效電晶體之研究

Study of Thin Gate Dielectrics on Silicon and Germanium MOSFETs

Publication List

A. International Letter:

1. Chi-Wen Chen, T. C. Chang, P. T. Liu, H. Y. Lu, K. C. Wang, C. S. Huang, C. C.

Ling, T. Y. Tseng, “High-performance hydrogenated amorphous-Si TFT for AMLCD and AMOLED applications”, IEEE Electron Device Lett., 26, 731, (2005).

2. Po-Tsun Liu, C. S. Huang, and C. W. Chen, “Enhanced Planar Poly-Si TFT EEPROM Cell for System on Panel Applications”, Electrochem. Solid-State Lett. 10,

J89 (2007).

3. Po-Tsun Liu, C. S. Huang, and C. W. Chen, “Nonvolatile low-temperature

polycrystalline silicon thin-film-transistor memory devices with oxide-nitride-oxide stacks”, Appl. Phys. Lett. 90, 182115 (2007).

4. Po-Tsun Liu, C. S. Huang, D. Y. Lee, P. S. Lim, S. W. Lin, C. C. Chen, H. J. Tao, and Y. J. Mii, “Modeling of nitrogen profile effects on direct tunneling probability

in ultrathin nitrided oxides”, Appl. Phys. Lett. 92, 022112 (2008).

5. Po-Tsun Liu, C.S. Huang, P. S. Lim, D, Y, Lee, S. W. Tsao, C. C. Chen, H. J. Tao and Y, J, Mii, “Anomalous Gate Edge Leakage Induced by High Tensile Stress in NMOSFET” IEEE Electron Device Lett., 29, 1249( 2008).

6. Po-Tsun Liu, Chen-Shuo Huang, Yi-Ling Huang, Jing-Ru Lin, Szu-Lin Cheng, Yoshio Nishi, and S. M. Sze, “Effects of postgate dielectric treatment on

germanium-based metal-oxide semiconductor device by supercritical fluid ZnO Thin Film Transistors with Oxidation Treatment”, IDMC’ 07

2. Chen-Shuo Huang, P. T. Liu, P. S. Lim, C. C. Chen, H.J. Tao and Y.J. Mii,

“Enhanced NBTI Degradation by SMT in Short-Channel pMOSFET”, SSDM’ 07

3. Y. T. Chou, C. S. Huang, S. J. Shiau, P. T. Liu, L.W. Chu, “Investigation on

Thin-Film-Transistors with a Transparent Material Zinc-Oxide Layer with DC sputter deposition system”, International Display Manufacturing Conference,

(IDMC, 2007)

4. C.-S. Huang, P.-T. Liu, “Repair of Thermal Damage in Gate Dielectric for Germanium-Based Metal-Oxide-Semiconductor Device by Supercritical Fluid

Technology”, International Conference On Metallurgical Coatings And Thin Films

( ICMCTF, 2011) C. Patent:

1. 張鼎張，李泓緯，劉柏村，黃震鑠，“反堆積型薄膜電晶體”，中華民國專利 申請案號：095132324

2. 張鼎張，李泓緯，劉柏村，黃震鑠，“具有埋藏層的薄膜電晶體及其製造方 法”，中華民國專利申請案號：095132357

3. 劉柏村，黃震鑠，黃羿霖，鄭斯璘，施敏，“一種形成鍺半導體表面保護層 的方法”，(申請中)

4. Po-Tsun Liu, Chen-Shuo Huang, Yi-Ling Huang, Szu-Lin Cheng, Simon M. Sze, and Yoshio Nishi, “METHOD FOR FORMING AN INTERFACIAL PASSIVATION LAYER ON THE GE SEMICONDUCTOR” (Application)