Chapter 6 Summaries and Future Work
A.1 Impact of Negative-Bias-Temperature-Instability on channel bulk of polysilicon TFT
Polycrystalline silicon thin-film transistors (poly-Si TFTs) are widely used as switch and driving devices in active matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs). These poly-Si TFTs are suitable for multifunctional displays, because they enable the integration of driver electronics, sensors, memories, and peripheral circuits on glass substrates, to afford system-on-panel (SOP) displays.
Complementary poly-Si TFTs operate with high duty cycles in peripheral driving circuit applications, and thus TFTs would suffer long-term negative and positive bias stress, at elevated ambient temperatures. Negative bias temperature instability (NBTI) is a critical reliability issue for metal-oxide-semiconductor field-effect transistors (MOSFETs), with single crystal silicon, also particularly for p-MOSFETs. It was reported that the electrochemical reaction between hydrogenated trivalent Si (Si-H) bonds and accumulated holes, triggers NBTI degradation, causing the formation of interface states and positive fixed charges [69]. Recently, the effects of NBTI on p-channel poly-Si TFTs have attracted much
research interest. One group reported that grain boundaries with many Si-H bonds experience greater NBTI degradation than usual degradation.[4, 70, 71] Both the Levinson and Proano method[70], and charge pumping method [72], provide the estimation of grain boundary traps.
The presence of interface states complicates the calculation of grain boundary traps, additionally; the estimation applies only to a channel region just beneath the gate insulator.
Thus, it is hard to investigate the grain boundary properties of poly-Si bulk under NBTI stress any further. Gated diodes are generally used to distinguish the interface trap states from bulk trap states in the single-crystal MOSFET technology.[73] However, the gated diodes were little used for the investigation of NBTI effects on the poly-Si. In this work, we used the gated P-intrinsic-N (PIN) diodes to investigate defect formation in the poly-Si bulk under NBTI stress, by analyzing the reverse defect-generation current.
The top gate p-channel poly-Si TFT were fabricated on a Corning 1737 glass substrate.
First, the buffer nitride/oxide layer, and then a 50 nm-thick a-Si:H film were deposited by plasma enhanced chemical vapor deposition (PECVD) at 380 °C. The a-Si:H film was dehydrogenated in a furnace at 450 °C for 60 minutes. The dehydrogenated a-Si was sequentially crystallized by XeCl excimer laser irradiation with a wavelength of 308 nm at 350 mJ/cm2. Microlithography and plasma dry etching processes were used to pattern the active poly-Si region, and then a 100 nm-thick TEOS (Tetra-Ethyl-Ortho-Silicate) base oxide film was formed as a gate insulator layer. It was followed that a layer of Mo thin film was
sputter-deposited and patterned as the gate electrode. The formation of source/drain regions was self-aligned by born implantation process through the metal gate electrode as a mask with a dosage of 8×1014 cm-2. Dopant activation was performed by rapid thermal annealing at 580
°C for 60 seconds. Hydrogen plasma passivation was carried out in a RF parallel-plate plasma reactor to passivate residual Si dangling bonds at the SiO2/poly-Si interface, and in the poly-Si grain boundaries. SiO2/SiNx films acting as post-metal dielectrics were deposited and etched for contact holes. Mo/Al/Mo metal layers were deposited and patterned to form the source and drain electrodes, and finally complete the p-channel TFT fabrication. The gated PIN diode was also adopted to investigate the NBTI degradation in the poly-Si channel bulk simultaneously. The structure and manufacture processes of the gated PIN diode are similar to the one of the proposed p-channel TFT. However, there are two doping regions in the gated PIN diode, including p-side (p+ doping with the boron dose of 8×1014 cm-2) and n-side regions (n- doping with the phosphorous dose of 1×1013 cm-2 and n+ doping with a dose of 8×1014 cm-2). When the gated PIN device was under NBTI stress, the negative gate bias sweep was applied to the gate electrode of the gated PIN diode, 0 V on the p-side region, and n-side floated. The gate bias stressing was relaxed periodically to explore device operation characteristics. The electrical operation conditions for device characterization are schematically shown in Fig. A-1. The reverse generation current of the gated PIN diode was determined at VP = -2.5 V, with n-side grounded and gate bias sweeping.
Figure A-2 shows transfer characteristics of p-channel poly-Si TFT after periodic NBTI stress. The NBTI degradation of single crystal MOSFETs was reported to be related with the electrochemical reaction between Si-H bonds near the Si/SiO2 interface, and the accumulated hole-carriers at the surface. This led to the generation of Si dangling bonds at the interface and fixed oxide charges. The similar NBTI degradation results also occurred in the poly-Si TFT, namely a negative threshold voltage shift and the elevated sub-threshold swing. Especially, the effects of NBTI on the poly-Si TFT device are expected to be even significant, due to a great deal of Si-H bonds at the grain boundaries of poly-Si film.[70] Trap states at the surface and in the bulk of poly-Si channel are supposed to play critical roles in the increased drain leakage at off state since gate leakage current nearly kept almost intact after NBTI stress, as shown in Fig. A-2.
The gated poly-Si PIN diode was used to explore the properties of poly-Si bulk under NBTI stress, and schematically illustrated in Fig. A-3. The diode was kept in the reversed state with -2.5 V applied to the p-side, and gate bias was swept from the negative to the positive voltages. The reverse current arises from the generation of electron-hole pairs in defect trap centers, and relates to depleted interface states and bulk states. The diode reverse current is given by [28]
where IR, IS, Ige, IBulk and IInt are total reverse diode current, diode saturation current,
total generation current, bulk generation current, and interface generation current, respectively.
The τg, ni, v, σ, vth, and Neff are the carrier generation lifetime, intrinsic carrier concentration,
volume of depletion regime, cross-section area, thermal velocity, and effective defect concentration, respectively. The generation current is proportional to the effective defect concentration. When a conductive channel layer of electron or hole is formed, as shown in Figs. A-3(a) and A-3(c), thermal emission of charges generated from interface trap states is effectively suppressed, since large amount of electrons or holes occupy most interface traps [74]. In this case, the IBulk of poly-Si dominates the reverse current. On the contrary, charge emission from the interface traps occurs, and IInt contributes to the reverse current, while the channel surface is at the depletion state under the operation condition of VP < VG < 0, as shown in Figs. A-3(b) and A-3(d). In addition, a dramatic increase of leakage current is observed at the high gate bias shown in Fig. A-3(d). It can be attributed to the carrier transportation at poly-Si grain boundaries near n-side or p-side depletion region by trap-assisted tunneling (TAT) mechanism. This is also expressed as followed, [75]
(A-3) where VTH is the threshold voltage for the formation of electron or hole channel, and α is a constant.
Figure A-4 shows electrical characteristics of the gated PIN diode under NBTI stress. It ITAT ∝ Neff × e−α/√ VP× (VG−VTH) (3)
is noted that the reverse current is elevated, due to defect creation at the interface and in the poly-Si bulk. The negative curve shift corresponds to the formation of positive fixed charges in the gate dielectric layer during the NBTI stress process. Additionally, the curve distortion at VG < VP in Fig. A-4, can be attributed to the spatial distribution of bulk trap states. The asymmetric TAT current arises from the asymmetric structure of n/p-side regions. The n-side has a n- doping region and reduces the lateral electric field across the hole channel to the n-layer under negative bias. However, it does not influence our estimation of IInt and IBulk.
Figure A-4(b) shows the progression of NBTI over time durations. The power-law time (tn) dependence of VTH and IInt are consistent with a reaction-diffusion mode.[76]
Additionally, the similar power-law time dependence of IBulk is observed in Fig. 4(b).
Therefore, we consider that the creation of bulk defects shares the same cause as the interface defect creation by NBTI process. It has been reported that grain boundaries with enriched Si-H bonds also suffer from NBTI degradation.[4, 70] The evidence of increasing IBulk
produced in this study also have shown that NBTI degradation has a spatial distribution and the Si-H bonds at grain boundaries of the poly-Si bulk interact with hole-carriers.
In summary, we proposed a gated poly-Si PIN diode device to investigate the effects of NBTI on the channel bulk of poly-Si TFTs. The gated diodes at a reversed state with gate bias sweeping can individually detect the evolution of interface states and bulk states in the poly-Si film, during the NBTI degradation process. Experimental results have shown that
interface states and bulk states of the PIN diode share power-law time dependences, and are consistent with a reaction-diffusion model. Additionally, NBTI degradation has a spatial distribution and Si-H bonds at the grain boundaries of the poly-Si bulk interact with hole-carriers.