Chapter 2 Theory of Filed-effect-transistor Based Switch
3.3 MOS-PHEMT switch process
The MOS-PHEMT switches were grown on semi-insulating GaAs substrates by
MOCVD. The sketch of the MOS-PHEMT cross section is shown in Fig. 3.4. The structure, from bottom to top, is comprised of a 600 nm GaAs/AlGaAs superlattice buffer layer, a 13 nm undoped In0.2Ga0.8As channel, a 3 nm undoped Al0.25Ga0.75As spacer, a delta-doped layer, a 37 nm undoped Al0.25Ga0.75As barrier layer, a 1.5 nm AlAs etch-stop layer and a 60 nm n+-GaAs cap layer.
The switches use dual-fingers 0.5 µm gate length MOS-PHEMT. Its processing includes the following steps: mesa isolation, wet chemical recess, oxidedeposition, ohmic formation, gate formation, interconnect metallization, and passivation. The mesa isolation was achieved by H3PO4/H2O2/H2O solution. The n+-GaAs cap layer was selectively etched by citric acid/H2O2/H2O solution with AlAs layer as etch stop layer. The AlAs layer was removed by HCl (10 %) solution. Then, the AlGaAs was treated with (NH4)2Sx at 60 for 30 mins before Al 2O3 deposition [33]. (NH4)2Sx
treatment before ALD Al2O3 deposition can reduce the interface trap density between oxide and semiconductor and form a thin layer 5 ± 1 Å of sulfide on the surface [34], which results in further reduction of device leakage current. After (NH4)2Sx treatment, 16 nm Al2O3 was deposited at 300 as gate dielectric by ALD and was annealed at 500 for 60 s in forming gas. Ohmic contacts were Au/Ge/Ni/Au and were annealed at 410 for 30 s. Ti/Pt/Au gate metal was formed on Al2O3 layer. PECVD Si3N4 was used as the dielectric layer for the capacitors and for final passivation. The interconnect metals are comprised of a Ti/Pt adhesion layer with 2 µm plated Au.
FIGURES
Figure 3.1 Schematic cross section of the PHEMT switch.
Figure 3.2 Epitaxy structure of the PHEMT used in the Cu-metallized AlGaAs/InGaAs SPDT switches.
Figure 3.3 Circuit schematic of the series/shunt SPDT switch.
Figure 3.4 Sketch of the MOS-PHEMT cross section.
Chapter 4
widely used for the fabrication of GaAs based field effect transistors and MMICs and the reliability of the metal system has been well proven. In this study, we use Cu metal instead of Au metal as the interconnect metal for the AlGaAs/InGaAs PHEMT SPDT switches. The employment of Cu as the metallization metal has several major advantages over Au, such as lower resistivity, higher thermal conductivity, and lower cost.Nevertheless, Cu diffuses very fast into GaAs if without any diffusion barrier and forms a deep acceptor to capture carrier in GaAs. It will lead to the failure of the electrical properties of the GaAs devices. In our previous research, we have demonstrated backside Cu metallization on GaAs MESFET using TaN as the diffusion barrier [9], Cu airbridge on low noise GaAs HEMTs using WNx as the diffusion barrier [11], and fully Cu metallized InGaP/GaAs HBT using Pt as the diffusion barrier [12]. In this study, we choose Pt as the diffusion barrier metal since Pt is commonly used as the plate metal for the MIM capacitor of the switch. The Pt diffusion barrier was very effective in preventing Cu from diffusing into the conventional Schottky and ohmic metal in this study. The fabrication and the electrical performance of the SPDT MMIC switches using Cu metallization technology are reported for the first time.
4.2 Results and discussion
The switch developed in this study can be used in the WLAN system for switching between the transmitting and receiving modes. In this study, the series/shunt SPDT switch uses 0.5-µm gate length, dual-fingers AlGaAs/InGaAs PHEMTs. The gate resistor between the signal and control terminal has a value of 3 kΩ. Fig. 3.3 presents the circuit schematic of the series/shunt SPDT switch in Chapter 3. When the control voltage 1 (VCTRL1) is biased at 3 V and the control voltage 2 (VCTRL2) at 0 V, the RF signal is flowing from RFin to RFout1. Oppositely, the RF signal path is from RFin to RFout2 as VCTRL1 is biased at 0 V and VCTRL2 at 3 V.
Compared with the HEMTs in the switch fabricated with conventional Au interconnects, the HEMTs in the switch fabricated using Cu metallization in this study showed similar DC characteristics. The HEMTs used in the Cu-metallized SPDT switches exhibited a drain saturation current density of 160 mA/mm and a transconductance of 140 mS/mm at VDS = 3 V. The devices had threshold voltage of -1.5 V. The performances of insertion loss and isolation of the SPDT switches with Cu metallization and with Au metallization were measured at 2.5 GHz, respectively, and the results are as shown in Fig. 4.1. The Cu-metallized switch had an insertion loss of 0.33 dB and an isolation of 36.7 dB (control voltage = +3/0 V, input power = 0 dBm) at 2.5 GHz. The results in the RF characteristics showed very little deviation for the switches with Cu interconnects and the switches with Au interconnects. The deviation of these two switches is primarily due to the nonuniformity of the wet chemical etch in the gate recess process, which may influence the on-state resistance and off-state capacitance of the transistor dominating insertion loss and isolation.
These RF results were consistent with the DC characteristics, which indicates that the use of Cu metallization would not increase the on-state resistance and the off-state capacitance of the active channel of the transistors and implies that the Cu
metallization could be applied to the interconnects of the SPDT switches without effecting the switch performance.
4.3 Reliability test
To test the thermal stability of the Pt diffusion barrier for long-term period, the Cu-metallized switches were annealed at 250 for 20 h, the DC characteristics of the HEMT device in the circuits after annealing are shown in Figs. 4.2 and 4.3.
Although small degradation of the ohmic contact resistance was observed in Fig. 4.3, the drain saturation current density and the extrinsic transconductance of the device were not obviously influenced with very little change after annealing at 250 for 20 h, as shown in Figs. 4.2 and 4.3 (less than 1 % difference in drain saturation current density and less than 3 % difference in extrinsic transconductance). These results indicate that Cu–Pt interconnect layers are quite stable and that Pt is an effective diffusion barrier against Cu diffusion after thermal annealing. Thus, the Cu-metallized SPDT switches have maintained the electrical performance without any significant change during the high-temperature ambient test. Overall, the Cu-metallized SPDT switches have sustained the high temperature environment test without obvious DC performance degradation.
The RF performance of the Cu-metallized switches was also evaluated at high temperature. As shown in Fig. 4.4, the switch has an insertion loss of 0.33 dB and an isolation of 36.7 dB at 2.5 GHz before thermal test. After 144 h of high temperature storage life (HTSL) evaluation at 150 under nitrogen atmosphere, the Cu-metallized switches still possessed very good reliability with similar RF performance. The Pout–Pin relationships of the Cu-metallized switches at 2.5 GHz after annealing at 150 under nitrogen atmosphere for different annealing time are as shown in Fig. 4.5. Input P1dB was kept at about 27 dBm without significant change
and maintained the same level without any obvious degradation after the long term test. Fig. 4.6 reveals that input third-order intermodulation intercept point (input IP3) of 50 dBm can be achieved at the input power of 15 dBm, and the trend of control current still remained stable. It suggests that no Cu diffusion into the active device region, and no degradation of on-state resistance and power handing capability for the transistors after thermal annealing occurred for the Cu-metallized SPDT switches using Pt as the diffusion barrier. Hence, the Cu-metallized switches demonstrated very good reliability and showed similar switch power handling capability after 144 h of HTSL environment test.
To test the operation reliability of the Cu-metallized switches, the Cu-metallized switches were subjected to an on/off stress test (control voltage = +3/0 V exchange) for 24 h at room temperature. As shown in Fig. 4.7, the Cu-metallized switches showed very little change after the stress test. The insertion loss and isolation still remained stable. Almost no obvious change in the insertion loss and isolation occurred, which indicated that no significant degradation of on-state resistance and off-state capacitance took place. It implies no Cu diffusion into the active device region for the transistors after control voltage exchange stress for the Cu-metallized SPDT switches using Pt as the diffusion barrier.
4.4 Conclusions
An SPDT GaAs switch fabricated with Cu-metallized interconnects using Pt as the diffusion barrier has been reported for the first time. The RF characteristics of the Cu-metallized SPDT switch exhibited an insertion loss of 0.33 dB and an isolation of 36.7 dB at 2.5 GHz, the performance is comparable to the SPDT switches fabricated using conventional Au interconnects. High power handling capability was achieved with input P1dB of 27 dBm and IIP3 of 50 dBm. Based on the high temperature
reliability tests including thermal stress test (annealing at 250 for 20 h) and HTSL environment test, no significant changes in the DC and RF characteristics were observed for the SPDT switches after these tests. To test the operation reliability of the Cu-metallized switches, the Cu-metallized switches were subjected to an on/off stress test for 24 h at room temperature and showed very little change of the insertion loss and isolation. It is evident from these data that the Cu metallization process developed is very reliable and can be used for the GaAs MMICs fabrication.
FIGURES
Figure 4.1 Insertion loss and isolation vs frequency of the SPDT switches with Cu and Au metallizations.
Figure 4.2 Transconductance and drain-to-source current versus VGS bias characteristics of the Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches for 0.5-µm gate length before and after annealing at 250 for 20 h.
Figure 4.3 I–V characteristics of the Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches for 0.5-µm gate length before and after annealing at 250 for 20 h.
Figure 4.4 Insertion loss and isolation of the Cu-metallized SPDT switches at 2.5 GHz after annealing at 150 for different hours.
Figure 4.5 Insertion loss of the Cu-metallized SPDT switches with different input power levels at 2.5 GHz after annealing at 150 for different annealing periods.
Figure 4.6 Input IP3 and control current of the Cu-metallized SPDT switches with different input power levels at 2.5 GHz after annealing at 150 for different annealing periods.
Figure 4.7 Insertion loss and isolation versus frequency of the Cu-metallized AlGaAs/InGaAs 0.5-µm PHEMT SPDT switches before and after on/off stress test for 24 h at room temperature.
Chapter 5
Evaluation of Electrical Characteristics of the Copper-Metallized SPDT GaAs Switches at Elevated Temperatures
5.1 Introduction
Cu has been used instead of Al as the interconnect metal for Si integrated circuit technology since IBM adapted Cu metallization in the Si 0.18-µm technology [1, 2, 3].
The advantages of using Cu metallization for Si technology include low resistivity and high electromigration resistance; however, there are only a few reports on the Cu metallization of GaAs devices. Ti/Au interconnect metal has been extensively used for the manufacture of GaAs-based field-effect transistors and MMICs, and the reliability of the metal system has been well proven. The application of Cu as the metallization metal for GaAs devices has several superior advantages over Au, such as lower resistivity, higher thermal conductivity, and lower cost, as compared with Au.
In this paper, we characterized the electrical performance of the Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches and compare the performance with the Au-metallized GaAs SPDT switches.
Cu diffuses very fast into GaAs if without any diffusion barrier and forms a deep acceptor in GaAs, which leads to the failure of the electrical properties of the GaAs devices. It was previously demonstrated that TaN can be used as the diffusion barrier for the backside Cu metallization on GaAs MESFETs [9, 10] and that WNx can be used as the diffusion barrier for Cu airbridges on low-noise GaAs HEMTs [11].
Furthermore, Pt was used as the diffusion barrier layer for Cu-metallized switches [13], and an Au-free fully Cu-metallized InP HBT was also realized using Ti/Pt/Cu nonalloyed ohmic contacts with Pt as the diffusion barrier [14]. It has also been demonstrated that the Ti/Pt/Cu system structure was very stable even after being
annealed up to 350 and that Cu started to diffuse through the Pt diffusion barrier and formed a Cu4Ti phase after being annealed at 400 , as investigated by X-ray diffraction data, Auger electron spectroscopy depth profiles, and the sheet resistance measurement [12]. In this paper, the temperature-dependent characteristics of the Cu-metallized switches are studied. The thermal stability of the Pt diffusion barrier and the electrical reliability are also investigated.
5.2 Results and discussion
The HEMTs in the switch fabricated using Cu metallization showed similar DC characteristics in comparison with those in the switch fabricated with traditional Au metallization. As shown in Figs. 5.1 and 5.2, a drain saturation current density of 160 mA/mm and an extrinsic transconductance of 140 mS/mm at VDS = 3 V were measured both for the Cu- and the Au-metallized switches. The devices had a threshold voltage (Vth) of −1.5 V. The insertion loss, return loss, and isolation characteristics of the SPDT switches with Cu metallization and with Au metallization measured at 2.5 GHz are shown in Figs. 5.3 and 5.4, respectively. The Cu-metallized switch had an insertion loss of 0.33 dB, a return loss of 23.3 dB, and an isolation of 36.7 dB (control voltage = +3/0 V; input power = 0 dBm) at 2.5 GHz. There is very little difference in the RF characteristics for the switches with Cu interconnects and with Au interconnects. The small differences of these two switches were due to the nonuniformity of the wet chemical etch in the gate recess process. The nonuniformity of the wet chemical etch could cause the fluctuation of the on-state resistance and off-state capacitance of the transistors which dominate insertion loss and isolation [13]. It appears from these data that Cu metallization does not affect the SPDT HEMT switch performance.
In order to evaluate the temperature-dependent effect on the DC and RF
characteristics of the Cu-metallized switches, the switches were evaluated at different temperatures. The DC characteristics of the device were measured at different temperatures from 300 °K to 500 °K. Fig. 5.5 shows the current–voltage (I–V) characteristics at different high-temperature ambients. The extrinsic transconductance and the drain-to-source current versus the temperature for the Cu-metallized SPDT switches were shown in Fig. 5.6. A drain saturation current density of 188 mA/mm and an extrinsic transconductance of 159 mS/mm at VDS = 3 V at 300 °K were measured for the devices. While the background carrier concentration from the substrate rises exponentially with temperature, causing the 2-DEG concentration (n2DEG) to increase in the active layer, the carrier velocity (ν) degraded seriously by the lattice scattering and carrier–carrier scattering mechanisms [35]. Therefore, IDSS0
drops at high temperatures due to the enhanced scattering mechanisms even though the carrier concentration increases at high temperatures.
Furthermore, the gate leakage current (IG) as a function of the gate-to-drain voltage (VGD) is shown in Fig. 5.7. When the gate-to-drain voltage was biased at −22 V, the gate leakage currents were 430, 450, and 490 µA/mm at the temperatures of 300 °K, 380 °K, and 500 °K, respectively. The gate leakage current increases with increasing temperature mainly due to the tunneling mechanism with thermionic emission and partly caused by the reduction of barrier height [36].
Fig. 5.8 shows that the Vth decreases with increasing temperature. The Vth of a δ-doped HEMT can be obtained by solving the 1-D Poisson’s equation (5.1) as Among the aforementioned parameters, ΦB is the Schottky gate barrier height, ∆Ec is the conduction-band discontinuity between the Schottky layer and the InGaAs
channel, dd is the distance between the gate and the n2DEG location, (dd +∆d) is the effective distance between the gate and the n2DEG location, and ε is the permittivity of the Schottky layer. Based on Eq. (5.1), when the temperature is increased, the threshold voltage decreases owing to the increase of the intrinsic channel carrier concentration n2DEG [35] and the lowering of the Schottky barrier height [38, 39].
Moreover, the decrease of Vth is partly caused by the leakage current from a semi-insulating substrate with increasing temperature [36]. Based on the relationship of Vth = Vth0 − K(T − T0), Vth is relatively temperature insensitive. The Vth shift from 300 °K to 500 °K was only −0.05 V, and δVth/δT = −0.25 mV/°K as a result.
As shown in Fig. 5.8, the maximum extrinsic transconductance (gm,max) decreases with increasing temperature, which is attributed to the decrease of the intrinsic transconductance [35] and the increase of the ohmic contact resistance [40], respectively. Therefore, it can be seen that when the temperature is increased, the degradations of the device performance include the increase of the leakage current and the decrease of the breakdown voltage, threshold voltage, extrinsic transconductance, and drain saturation current density.
Furthermore, RF performances of the device were measured at high temperatures.
Fig. 5.9 shows the insertion loss and isolation versus frequency of the SPDT switches with Cu metallization from 300 °K to 380 °K. The isolation characteristics of the Cu-metallized switches degrades slightly because of the increase of the leakage current from the semi-insulating substrate with increasing temperature. For this reason, the isolation is closely related to the off-state threshold characteristics which were affected by the leakage current. Although isolation of the Cu-metallized switch was influenced by the thermal effect, it still maintained excellent isolation value higher than 35 dB.
In addition, the transistor had a small on-state resistance which resulted in low
insertion loss. However, the on-state resistances of the Cu-metallized switches measured at VGS = 0 V and VDS = 0.5 V increased gradually from 300 °K to 500 °K, as shown in Fig. 5.10. The series resistance increased as the source, drain, and gate resistances increased with increasing temperature because of the carrier scattering [41]
which would result in the reduction of the carrier transport velocity (υ) and the electron mobility (µe) in the channel due to the lattice scattering and carrier–carrier scattering at elevated temperatures [35]. The degradation of on-state resistance was also caused by the increase of the electrode contact resistance with temperature as verified in the previous reports [42]. This phenomenon led to the slight degradation of the insertion loss, but the increase in the insertion loss from 300 °K to 380 °K was only 0.08 dB, as shown in Fig. 5.9. Overall, for high-temperature operation, the Cu-metallized switch had an insertion loss of 0.46 dB and an isolation of 42.79 dB (control voltage = +3/0 V; input power = 0 dBm) when tested at 2.5 GHz at 380°K. It demonstrates that the Cu metallization can be applied to the interconnects of the SPDT switches at high temperatures without affecting the switch performance.
Fig. 5.11 shows the thermal effect on the switching time for the Cu-metallized switches. The switching time increases with increasing temperature primarily due to the degradation of the on-state resistance.
The power limitation of the switch operation is as explained in [17, 19, 26, 32], and the maximum input power Pmax is expressed as in Chapter 2:
0 harmonic characteristics of the Cu-metallized switches as a function of temperature
measured at 2.5 GHz are shown in Fig. 5.12. The value of the input P1dB with different temperatures remained considerably steady because the threshold voltage shift was small and did not influence the power handling capability. The characteristics of the second and third harmonics from 300 °K to 380 °K under the input power of 20 dBm are shown in Fig. 5.12. The second and third harmonics of the device remained quite
measured at 2.5 GHz are shown in Fig. 5.12. The value of the input P1dB with different temperatures remained considerably steady because the threshold voltage shift was small and did not influence the power handling capability. The characteristics of the second and third harmonics from 300 °K to 380 °K under the input power of 20 dBm are shown in Fig. 5.12. The second and third harmonics of the device remained quite