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Low Cost, Low Power Consumption SPDT GaAs Switches with
Copper Metallization and Gate Dielectric
Student: Yun-Chi Wu
Advisor: Dr. Edward Yi Chang
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A Dissertation
Submitted to Department of Materials Science and Engineering College of Engineering
National Chiao Tung University In Partial Fulfill of the Requirements
For the Degree of
Doctor of Philosophy in Engineering 2009
Hsinchu, Taiwan, Republic of China
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Low Cost, Low Power Consumption SPDT GaAs Switches with
Copper Metallization and Gate Dielectric
Student: Yun-Chi Wu Advisor: Dr. Edward Yi Chang Department of Materials Science and Engineering
National Chiao Tung University
Abstract
In this dissertation, the performances of the copper (Cu)-metallized AlGaAs/InGaAs pseudomorphic high-electron-mobility transistor (PHEMT) single-pole-double-throw (SPDT) switches and the AlGaAs/InGaAs metal-oxide-semiconductor PHEMT (MOS-PHEMT) SPDT switches with Al2O3 were
studied.
Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches utilizing platinum (Pt, 70 nm) as the diffusion barrier is reported. In comparison with the gold (Au)-metallized switches, the Cu-metallized SPDT switches exhibited comparable performance with insertion loss of less than 0.5 dB, isolation larger than 35 dB and the input power for one dB compression (input P1dB) of 27 dBm at 2.5 GHz. To test
the thermal stability of the Pt diffusion barrier, these switches were annealed at 250
for 20 h. After the annealing, the switches showed no degradation of the DC
characteristics. In addition, after 144 h of high temperature storage life (HTSL) environment test at 150 , these Cu-metallized switches still remained excellent and
reliable radio frequency (RF) characteristics and power handling capability. To test the operation reliability of the Cu-metallized switches, the Cu-metallized switches were subjected to on/off (control voltage = +3/0 V exchange) stress test for 24 h at
room temperature. The devices maintained excellent RF characteristics after the stress test.
The electrical characteristics of these Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches were also evaluated at elevated temperatures. Compared to the Au-metallized switches, the Cu-metallized SPDT switches exhibited comparable performance with insertion loss less than 0.5 dB, return loss larger than 20 dB, isolation larger than 35 dB, and the input P1dB of 28.3 dBm at 2.5 GHz. In order to
evaluate the temperature impact on DC and RF characteristics of the Cu-metallized switches for high-temperature applications, the switches were tested at different temperatures. The device exhibits low thermal threshold coefficients (δVth/δT) of
−0.25 mV/°K from 300 °K to 500 °K, good microwave performance at 380 °K with insertion loss less than 0.5 dB, isolation higher than 40 dB, and the input P1dB of 28.45
dBm at 2.5 GHz.
An AlGaAs/InGaAs MOS-PHEMT SPDT switch using Al2O3 high-κ gate
dielectric by atomic layer deposition (ALD) is fabricated for RF switch application. The MOS-PHEMT exhibited the comparable DC performance and much lower gate current as compared to the conventional PHEMT. RF test shows the MOS-PHEMT switch has an insertion loss of less than 0.5 dB, an isolation larger than 30 dB, a return loss larger than 15 dB, and an input P1dB of 31.4 dBm at 2.5 GHz.
Overall, we have successful developed the Cu metallization process for the AlGaAs/InGaAs SPDT switch and the Al2O3 high-κ gate dielectric process for the
MOS-PHEMT SPDT switch, and have reported the fabrication process and electrical performances of the Cu-metallized switches and the MOS-PHEMT switches with Al2O3 dielectric for low cost and low power consumption SPDT switches for wireless
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Contents
Abstract (in Chinese)……….…i
Abstract (in English)………iii
Acknowledge (in Chinese)………....v
Contents………..vi
Table Captions……….... ix
Figure Captions………...x
Chapter 1 Introduction………1
1.1 General Background and Motivation………….………..1
1.2 Outline of the Dissertation……...………....4
Chapter 2 Theory of Filed-effect-transistor Based Switch……..…7
2.1 Comparisons between FET Switch and PIN Switch………..7
2.2 Antenna Switch Design………..………8
2.3 Equivalent Circuit of a Switch Used FET………8
2.4 RF Characteristics of a Switch………..10
2.4.1 Insertion Loss (IL)……….………..10
2.4.2 Isolation………...10
2.4.3 Power Handing Capability..……….11
2.4.4 Input Third-order Intermodulation Intercept Point and Third-order Intermodulation Distortion………12
Chapter 3 Fabrication of Copper-Metallized GaAs Switch and
MOS-PHEMT Switch………..………....19
3.1 Introduction of PHEMT Switch Process………..19
3.2 Cu-metallized switch process………..19
3.2.1 Device active region definition………...19
3.2.2 Ohmic Contact Formation………...………...20
3.2.3 Recess and Gate Formation.……….21
3.2.4 Device Passivation…...………22
3.2.5 Interconnect Metal Line...………22
3.3 MOS-PHEMT switch process………...………..23
Chapter 4 SPDT GaAs Switches With Copper-Metallized
Interconnects………....29
4.1 Introduction………...………..29
4.2 Results and Discussion………...……30
4.3 Reliability Test………31
4.4 Conclusions………...………32
Chapter 5 Evaluation of Electrical Characteristics of the
C opp er-M e ta ll i ze d SP D T Ga As S wi tc hes a t Ele va ted
Temperatures………..41
5.1 Introduction………...………..………….41
5.2 Results and Discussion………42
Chapter 6 An Al
2O
3AlGaAs/InGaAs MOS-PHEMT SPDT Switches
with Low Control Currents for Wireless Communication
Applications………...…..61
6.1 Introduction………..…...………..………….61
6.2 Results and Discussion………62
6.3 Conclusions..………..……….………64
Chapter 7 Conclusions………..……….70
References……….72
Vita (in Chinese)
Publication List
Table Captions
Chapter 1
Figure Captions
Chapter 2
Figure 2.1 Radio frequency front-end system………..…...……….13 Figure 2.2 (a) Specific schematic of an antenna switch. (b) Circuit schematic of a single-pole-double-throw antenna switch………..…...………….14 Figure 2.3 Typical I-V characteristics of a depletion mode field-effect transistor…..15 Figure 2.4 Equivalent circuit of a switching FET. ………..…...……….16 Figure 2.5 (a) Equivalent circuit schematic for a GaAs FET for switching applications.
(b) Simplified off-state equivalent circuit for a FET switch in high-impedance state. ………..…...………...17 Figure 2.6 Output power spectrum of the two-tone input signal. ………..…..18
Chapter 3
Figure 3.1 Schematic cross section of the PHEMT switch..………..…...…...25 Figure 3.2 Epitaxy structure of the PHEMT used in the Cu-metallized AlGaAs/InGaAs SPDT switches..………..…...…...26 Figure 3.3 Circuit schematic of the series/shunt SPDT switch..………..…....27 Figure 3.4 Sketch of the MOS-PHEMT cross section..………..…...…...28
Chapter 4
Figure 4.1 Insertion loss and isolation vs frequency of the SPDT switches with Cu and Au metallizations..………..…...…...34 Figure 4.2 Transconductance and drain-to-source current versus VGS bias
characteristics of the Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches for 0.5-µm gate length before and after annealing at 250 for 20
h..………..…...…...35 Figure 4.3 I–V characteristics of the Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches for 0.5-µm gate length before and after annealing at 250 for 20
h………....………..…...…...36 Figure 4.4 Insertion loss and isolation of the Cu-metallized SPDT switches at 2.5 GHz after annealing at 150 for different hours..………..…...…...37
Figure 4.5 Insertion loss of the Cu-metallized SPDT switches with different input power levels at 2.5 GHz after annealing at 150 for different annealing
periods..………..…...…...38 Figure 4.6 Input IP3 and control current of the Cu-metallized SPDT switches with different input power levels at 2.5 GHz after annealing at 150 for
different annealing periods..………..…...…...39 Figure 4.7 Insertion loss and isolation versus frequency of the Cu-metallized
AlGaAs/InGaAs 0.5-µm PHEMT SPDT switches before and after on/off stress test for 24 h at room temperature..………..…...…...40
Chapter 5
Figure 5.1 I–V characteristics of AlGaAs/InGaAs PHEMT SPDT switches for 0.5-µm gate length with Cu and Au metallizations…....………..…...…...48 Figure 5.2 Extrinsic transconductance and drain-to-source current versus VGS bias
characteristics of the AlGaAs/InGaAs PHEMT SPDT switches for 0.5-µm gate length with Cu and Au metallizations…...49 Figure 5.3 Insertion loss and return loss versus frequency of the SPDT switches with
Cu and Au metallizations..………..…...…...50 Figure 5.4 Isolation versus frequency of the SPDT switches with Cu and Au metallizations...………..…...…...51 Figure 5.5 I–V characteristics of the 0.5-µm gate length PHEMT used in the
Cu-metallized switches tested at 300 °K, 380 °K, and 500 °K, respectively………..………..…...…...52 Figure 5.6 Extrinsic transconductance and drain-to-source current versus VGS bias
characteristics of the 0.5-µm gate length PHEMT used in the SPDT switches when measured at 300 °K, 380 °K, and 500 °K, respectively...53 Figure 5.7 Gate leakage current (IG) as a function of the gate-to-drain voltage (VGD)
for the PHEMTs used in the switches when tested at 300 °K, 380 °K, and 500 °K..………..…...…...54 Figure 5.8 Threshold voltage (Vth), drain saturation current density (Idss), and extrinsic
transconductance (gm) characteristics as a function of temperature for the
Cu-metallized AlGaAs/InGaAs PHEMT used in the SPDT switches…...55 Figure 5.9 Insertion loss and isolation versus frequency of the Cu-metallized SPDT switches measured from 300 °K to 380 °K...………..…...…...56 Figure 5.10 On-state resistance as a function of temperature for the SPDT switches.57 Figure 5.11 Switching time as a function of temperature at 2.5 GHz for the SPDT
switches..………..…...…...58 Figure 5.12 Input power 1-dB compression and second and third harmonic characteristics for the SPDT switches as a function of temperature when tested at 2.5 GHz..………..…...…...59 Figure 5.13 Input IIP3 as a function of temperature under different input power
Chapter 6
Figure 6.1 The circuit schematic of the series/shunt AlGaAs/InGaAs MOS-PHEMT SPDT switch..………..…...…...65 Figure 6.2 (a) I-V characteristics of the 0.5 µm gate length MOS-PHEMT and PHEMT. (b) Transconductance and drain-to-source current vs VGS
characteristics of the 0.5 µm gate length MOS-PHEMT and PHEMT…66 Figure 6.3 Gate leakage current (IG) as a function of the gate-to-drain voltage (VGD)
for the MOS-PHEMT and the PHEMT..………..…...…...67 Figure 6.4 (a) Insertion loss, isolation, and (b) return loss of the MOS-PHEMT SPDT switch..………..…...…...68 Figure 6.5 (a) Insertion loss of the MOS-PHEMT SPDT switch and the PHEMT
SPDT switch with different input power levels at 2.5 GHz. (b) Control currents of the MOS-PHEMT SPDT switch and the PHEMT SPDT switch at different control voltage levels...………..…...…...69
Chapter 1
Introduction
1.1 General Background and Motivations
Copper (Cu) metallization and high-k dielectrics have been used in Si technology to resolve the RC delay issue and for lower power consumption at higher operating frequencies. The Cu metallization process has been widely used in Si integrated circuit technology since IBM announced its success with Cu metallization instead of aluminum (Al) in the Si 0.18-µm very large scale integration technology [1, 2, 3]. The advantages of using Cu metallization for Si technology include low resistivity and high electromigration resistance, high stress voiding resistance, and feasible for Damascene process for smaller line dimensions VLSI. However, Cu diffuses very fast into Si in absence of any diffusion barrier [4, 5, 6]. Cu also diffuses very fast into GaAs when Cu is in direct contact with the GaAs substrate without any diffusion barrier [7]. Even though the use of Cu as metallization metal has become very popular in Si devices, there are only a few reports on the Cu metallization of GaAs devices. Traditionally, titanium (Ti)/Au interconnect metal is widely used for the fabrication of GaAs-based field effect transistors and monolithic microwave integrated circuits (MMICs) and the reliability of the metal system has been well proven. In this study, Cu metal instead of gold (Au) metal is used as the interconnect metal for the AlGaAs/InGaAs pseudomorphic high-electron-mobility transistor (PHEMT) single-pole-double-throw (SPDT) switches. The employment of Cu as the metallization metal has several major advantages over Au, such as lower resistivity (1.67 µΩ-cm for Cu; 2.2 µΩ-cm for Au), higher thermal conductivity (3.98 W/cm°K for Cu; 3.15 W/cm°K for Au), and lower cost, as compared with Au.
price of Cu is 5400 times cheaper than that of Au, and thus the production cost will be reduced. However, Cu diffuses very fast into III-V semiconductors as well as Si. The diffusion barrier between the Cu interconnections and the semiconductor for GaAs devices has to possess the following properties:
(1) High resistance to diffusion of foreign atoms;
(2) High conductivity, thermal stability and crystallization temperature; (3) Inert with Cu and underlying metal or substrate;
(4) Good adhesion between Cu and underlying materials; (5) Smooth surface and low stress;
(6) Lack of grain boundaries and with an amorphous texture;
(7) The loss rate of barrier layer into overlying metal and underlying substrate should be small.
As mentioned above, Cu diffuses very fast into GaAs if without any diffusion barrier and forms a deep acceptor to capture carriers in GaAs. It will lead to the failure of GaAs devices. In our previous researches, we have demonstrated backside Cu metallization on GaAs semiconductor field-effect transistors (MESFET) using TaN as the diffusion barrier [9, 10], Cu airbridge on low noise GaAs high-electron-mobility transistors (HEMTs) using WNx as the diffusion barrier [11],
fully Cu metallized InGaP/GaAs heterojunction bipolar transistor (HBT) using platinum (Pt) as the diffusion barrier [12, 13] and a Au-free fully Cu-metallized InP HBT was also realized using Ti/Pt/Cu nonalloyed ohmic contacts with Pt as the diffusion barrier [14]. It has also been demonstrated that the Ti/Pt/Cu system structure was very stable even after being annealed up to 350 and that Cu started to diffuse
through the Pt diffusion barrier and formed the Cu4Ti phase after annealed at 400 ,
as investigated by X-ray diffraction method, Auger electron spectroscopy depth profiles, and the sheet resistance measurement [12]. In this study, the electrical
performance of the PHEMT SPDT switches using Cu metallization technology are evaluated in Chapter 4. We characterized the electrical performance of the Cu-metallized PHEMT SPDT switches and compare the performance with the Au-metallized PHEMT SPDT switches. Pt was used as the diffusion barrier layer for Cu-metallized switches and we choose Pt as the diffusion barrier metal since Pt is commonly used as the plate metal for the metal-insulator-metal (MIM) capacitor of the switch. Moreover, the thermal stability of the Pt diffusion barrier and the electrical reliability are also investigated. In Chapter 5, the temperature-dependent characteristics of the Cu-metallized switches are studied.
For the low power consumption demands, the GaAs PHEMT based switches, which demonstrate low gate current, have an obvious advantage over Si p-i-n (PIN) diode based switches due to lower DC power consumption [15]. Overall, GaAs switches have lower control voltage, higher power handling capability, and higher electron mobility compared to other solid-state switches, which makes them suitable for cellular handset, wireless local area network (WLAN), and bluetooth applications. However, III-V HEMT using Schottky gate for current modulation usually results in higher gate leakage current as compared to MOSFET using high-κ dielectric for device modulation. The use of high-κ gate dielectric for III-V HEMT can significantly suppress direct-tunneling gate current and results in considerable reduction in power consumption. In Chapter 6, atomic layer deposition (ALD) Al2O3 with a high
dielectric constant (8.6-10) and a high breakdown field (5~10 MV/cm) was used as high-κ material for AlGaAs/InGaAs MOS-PHEMT switches [16]. The major requirements for good RF switch are low insertion loss, high isolation, high power handling capability and low control current [17]. To achieve low control current, the methods include reducing the gate current and the size of devices. The MOS-PHEMT switches with extra high resistance between control electrode and signal path provide
good isolation and results in much lower control current as compared to conventional PHEMT switches.
1.2 Outline of the Dissertation
This dissertation covers the related studies of the novel SPDT switch technologies including the Cu-metallized AlGaAs/InGaAs PHEMT switches and the MOS-PHEMT switches. The contents are divided into 7 chapters. In Chapter 2, the introduction to the GaAs switch characteristics and the device equivalent circuit schematic are briefed. Then, the detailed fabrication process of the Cu-metallized switch and the MOS-PHEMT switch is described in Chapter 3.
In Chapter 4, the Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches utilizing Pt (70 nm) as the diffusion barrier is reported. In comparison with the Au-metallized switches, the RF performance and the power handling capability of the Cu-metallized switches at 2.5 GHz were evaluated. To test the thermal stability of the Pt diffusion barrier, these switches were annealed at 250 for 20 h. In addition, after
the high temperature storage life (HTSL) environment test at 150 for 144 h was
carried out for these Cu-metallized switches, the RF characteristics and the power handling capability were observed. To test the operation reliability of the Cu-metallized switches, the Cu-metallized switches were subjected to on/off (control voltage = +3/0 V exchange) stress test for 24 h at room temperature.
In Chapter 5, in order to evaluate the temperature-dependent impact on DC and RF characteristics of the Cu-metallized switches for high-temperature applications, the switches were tested at different temperatures. The low thermal threshold coefficients (δVth/δT) of the device were evaluated from 300 °K to 500 °K, the
microwave performance at 380 °K at 2.5 GHz was evaluated.
Al2O3 high-κ gate dielectric by ALD for RF switch application. The MOS-PHEMT
exhibited the comparable DC performance and much lower gate current as compared to the conventional PHEMT. The RF test and an input power for one dB compression (input P1dB) of the MOS-PHEMT switch at 2.5 GHz were measured. The
MOS-PHEMT MMIC switch was realized using ALD Al2O3 gate dielectric in this
study.
TABLE
Table 1.1 Properties comparisons of the possible interlayer metals [8].
Property\Metal Cu Ag Au Al
Resistivity (µΩ cm) 1.67 1.59 2.35 2.66
Young’s modulus(10-11 dyn/cm2) 12.98 8.27 7.85 7.06
Thermal Conductivity (W/cm°K) 3.98 4.25 3.15 2.38
CTE(106) 17 19.1 14.2 23.5
Melting Point ( ) 1085 962 1064 660
Specific heat Capacity (J/Kg•K) 386 234 132 917
Corrosion in air Poor Poor Excellent Good
Deposition
Sputtering Yes Yes Yes Yes
CVD Yes No No No
Evaporation Yes Yes Yes Yes
Etching
Dry No No No Yes
Wet Yes Yes Yes Yes
Resistance to Electromigration High Very Low Very High Low
Chapter 2
Theory of Filed-effect-transistor Based Switch
2.1 Comparisons between FET Swicth and PIN Switch
The transmitter/receiver (Tx/Rx) switches are important components as common
as amplifiers and mixers in microwave systems as shown in Fig. 2.1. Because of the booming demands for RF switches in cellular handset, base station, bluetooth, and WLAN systems, high performance GaAs RF switches become very important. Tx/Rx
switch is for changing the RF signal path to transmitter or receiver. Therefore, a low insertion loss, high isolation and high power handling capability characteristics are needed for switches to improve the overall system performance for wideband frequency. Traditionally the PIN diode has been widely used for switching RF signals. However, PIN diodes have high insertion loss with high bias current. Thus, the GaAs switches predominate over the commercial RF switches because of its low on resistances, low off capacitances and high linearity for the switch market. GaAs PHEMT has been commercially applied in RF switches and power amplifier for wireless communication applications. Owing to its higher charge density and higher saturated electron velocity in InGaAs channel compared to the GaAs MESFET, PHEMT performs lower insertion loss for switch, and higher power gain and power added efficiency for power amplifier [18]. For realizing practical RF switch based on AlGaAs/InGaAs PHEMTs, two major factors must be emphasized: First, reduction of the on-state-resistance (Ron) at Vgs = 0 V for insertion loss. Second, reduction of the
off-state-capacitance (Coff) when the Vgs is below Vth for isolation [19]. Besides, the
depletion mode PHEMT is used for most commercial RF switches. Although switches can also use the enhancement mode PHEMT device, the performance of the power handling capability is poor. Therefore, it is straightforward to design the depletion
mode PHEMT switches [15]. Therefore, PHEMT switches have become prevalent because the field effect transistor (FET) switches have advantages over diode switches for low power consumption, good RF performance, and easy monolithic circuit integration [20].
2.2 Antenna Switch Design
The typical circuit schematic of the antenna SPDT switch is shown in Figs. 2.2(a) and 2.2(b) for the transceiver construction and the SPDT switch is designed for two control voltages to inversely feed to the transistor pairs. One control voltage is high and the other control voltage is low. In transmit mode, the shunt FET in the transmit path is off, whereas the series FET is on. The transmit signal is flowing to the antenna. Meanwhile, the shunt FET in the receiver stem is on, while the series FET is off preventing the transmit signal in the receiver. Oppositely, in the receive mode the control voltages are reversed. Therefore, switch isolation can easily be improved by joining shunt mounted FET without excessive increase of insertion loss [15]. As mentioned above, the gate widths of the series and shunt devices have to be detailed designed to optimize tradeoff between insertion loss in on-state and isolation in off-state [21].
2.3 Equivalent Circuit of a Switch Used FET
The drain-to-source resistance of the FET in the channel behaves as a voltage variable resistor for a switch, and the gate-to-source voltage (Vgs) controls the
resistance. Therefore, the FET switch is a three-terminal device in which the Vgs
determines the on/off states. A FET for a switch is biased with the drain and source at zero voltage DC. The RF signal path is flowing from drain to source and the gate is the control terminal. Fig. 2.3 shows the typical current-voltage characteristics of a
depletion mode FET about Vds = 0 V at different Vgs. The Vds/Ids characteristic
approaches a resistance (Ids/Vds) in the region of Vds= 0V. This is a low resistance at
Vgs = 0 V. Oppositely, the FET is off as Vgs below pinch-off voltage with a high
resistance. This simple equivalent circuit is shown in Fig. 2.4. The gate resistor (Rg)
with the value of several kΩ is designed to provide extra isolation between the signal and control terminal. Very little gate current below 0.5 mA/mm for FETs can be obtained. Therefore, the FET switches have very low DC power consumption as compared to PIN diode switch [15].
Fig. 2.5(a) depicts an equivalent circuit schematic for a GaAs FET used in switching applications. The FET serves as a passive two-terminal device, which the gate terminal acts as the control signal port in passive mode. The RF signal flows between the drain and source. The gate terminal determines the RF impedance between the drain and source. The drain-to-source impedance varies from a low value under open channel when the gate is biased at zero voltage, to a high value when the gate is biased at pinch-off voltage to prevent current from flowing through the transistor.
When the low-impedance state of the FET switch is dominated by the fully open channel in passive mode, the device channel resistance is low. Owing to the low channel resistance, the insertion loss is independent of frequency [22]. The practical equivalent circuit is the “on” resistance for the transistor, and the reduction of on-state resistance and insertion loss can be improved by the large device width. In the high-impedance state, the PHEMT is dominated by the pinched-off channel or large “off” resistance as shown the switch equivalent circuit in Fig. 2.5(b). While rg is much
smaller than the reactance of Cg
[
rg ≤1/(ωCg)]
, the equivalent circuit of Fig. 2.5(a) can be substituted by a parallel combination of Roff and Coff as shown in Fig. 2.5(b),where Roff and Coff are expressed as shown in equation (2.1) and (2.2): 2 g sd off C C C = + (2.1) g g d d off r C r r R 2 2 2 2 ω + = (2.2) where ω is the operating frequency in radians/second [23]. The “off” state resistance Roff is an inverse function of the operating frequency ω, and reduces as frequency
increases according to the equation (2.2). The off-state performance of the switch will degrade at high frequency [24]. Furthermore, the degradation of the isolation in the off-state would be also resulted from increases of gate-to-source, gate-to-drain capacitance, and source-to-drain fringing capacitance by large device width [22]. Therefore, the device gate width must be optimized for better RF performance.
2.4 RF Characteristics of a Switch 2.4.1 Insertion Loss (IL)
Insertion loss (IL) in the on state is defined as the difference (dB) between the power received at the load before and after the insertion of the switch [25]. In view of this definition, insertion loss for the switch in the on state is expressed as shown in equation (2.3): ) ( log 10 0 10 P P IL=− L (2.3) where
P0= power delivered to the load with an ideal switch in the on state.
PL= power delivered to the load with the practical switch in the on state.
2.4.2 Isolation
delivered to the load for an ideal switch in the on state and the actual power delivered to the load when the switch is in the off state [25]. In view of this definition, isolation is expressed as shown in equation (2.4):
) ( log 10 0 ' 10 P P Isolation=− L (2.4) where
P0 = power delivered to the load with an ideal switch in the on state.
P’L = power delivered to the load with the practical switch in the off state.
2.4.3 Power Handing Capability
The FET switch maximum handling power (Pmax) is evaluated in the on-state and
in the off-state. Pmax is expressed in equation (2.5) and (2.6) [17]:
2 0 2 max Z I P dss = (on-state) (2.5) and 0 2 max 2 )) ( ( Z V V n P = p − BR (off-state) (2.6) where
Idss: saturation drain current;
Z0: system impedance;
n: number of stacked FETs; VBR: breakdown voltage.
From the practical consideration for the power limitation of the switch operation is explained in [26], and the maximum input power Pmax is expressed by equation
(2.7): 0 2 max 2 ) ( Z V V P = C − th (2.7) where Z0 is the line impedance, Vcis the absolute of the control voltage, and Vth is the
threshold voltage.
2.4.4 Input third-order intermodulation intercept point and third-order intermodulation distortion
In wireless communication system, multi-channel transmission is practically used for signal transmission [27]. The transmission bandwidth of communication system was divided into multiple information bandwidths and used multiple frequencies for data transmission to increase the transmission capacity. Nevertheless, when the system operating frequencies are more than two and the neighboring frequencies are located closely to each other, the device used in system will generate intermodulation distortion.
For analyzing the intermodulation distortion, two-tone signal consists of two signals as the input with the same amplitude at two closely spaced signals 5-10 MHz apart as shown in Fig. 2.6. Among all the intermodulation distortions of the devices, third-order intermodulation distortion (IM3) and the third-order intercept point (IP3) will dominate the device linearity because of device gain compression. Therefore, IM3 and IP3 of the devices have become the important factors for wireless communication applications. Input third-order intermodulation intercept point (IIP3) is defined as shown in equation (2.8):
) ( 2 ) ( ) ( 3 dBm P dBm dB IIP = in +∆ (2.8) where
IIP3: input third-order intermodulation intercept point; Pin: input power;
FIGURES
(a) Vdd VCT RL 1 VCT RL 2 Rg Rg Rg Rg (b)
Figure 2.2 (a) Specific schematic of an antenna switch. (b) Circuit schematic of a single-pole-double-throw antenna switch [21].
C
gC
gr
gr
gC
dsS o u rc e
D ra i n
r
dG a t e
(a) (b)Figure 2.5 (a) Equivalent circuit schematic for a GaAs FET for switching applications. (b) Simplified off-state equivalent circuit for a FET switch in high-impedance state [23].
Chapter 3
Fabrication of Copper-Metallized GaAs Switch and MOS-PHEMT Switch
3.1 Introduction of PHEMT switch process
The five major steps of the series/shunt SPDT PHEMT switch process are device active region definition, ohmic metal deposition and annealing, gate formation by wet chemical recess and gate photolithography, device passivation, and interconnection formation [27]. The schematic cross section of the PHEMT switch is shown in Fig. 3.1. The detailed fabrication process of the Cu-metallized switch and the MOS-PHEMT switch will be described in the following section.
3.2 Cu-metallized switch process 3.2.1 Device active region definition
Device active region definition is to confine the electrically conductive part of the device to specific parts of its surface area so that electrical current is prevented from flowing to other active areas [28]. The electrically conductive region is called the “active region”. The GaAs PHEMT was etched to separate each device and to reduce the leakage current from the substrate for the isolation. The functions of the active region definition consist of the active region formation, device isolation, reduction of parasitic capacitance, parasitic resistance, leakage current, and back-gating effect.
The AlGaAs/InGaAs PHEMT SPDT switch wafer was grown by metal organic chemical vapor deposition (MOCVD) on a 4-in semi-insulating GaAs substrate. The structure, from bottom to top, is composed of a 600-nm GaAs/AlGaAs superlattice buffer, a 13-nm undoped InGaAs channel, a 3-nm undoped AlGaAs spacer, a delta-doped layer, a 37-nm undoped AlGaAs Schottky layer, and a 60-nm n+-GaAs
capping layer, as shown in Fig. 3.2. The Hall electron mobility and sheet carrier concentrations at room temperature are 6500 cm2/V s and 3.0 x 1012 cm-2, respectively.
The device fabrication was carried out by the use of traditional lithography and lift-off technique. In the PHEMT switch fabrication, the device active region and the epitaxial resistor formation are defined by photolithography. The wafer was etched to buffer layer to obtain a good isolation. Then the mesa isolation and epitaxial resistors were formed utilizing H3PO4/H2O2/H2O mixing solution. After mesa etching, we
measured the etching depth by α-stepper to achieve the etch depth of about 400 nm, and checked the etched profile by scanning electron microscope (SEM).
3.2.2 Ohmic contact formation
The ohmic contact is formed by ohmic metal deposition and annealing. An ohmic contact is a low resistance junction between metal and semiconductor interface. Lower contact resistance will reduce device on-resistance and device power consumption. Therefore, in order to obtain good ohmic contact with low parasitic resistance, the semiconductor is doped heavily to form good contacts. After the ohmic metals deposition, a high temperature alloying process using rapid thermal anneal (RTA) was conducted to form the ohmic contacts.
For the ohmic metal layer formation, the germanium (Ge) is used for doping the GaAs and the nickel (Ni) is acted as a wetting agent and prevents the AuGe metal from “balling up” during alloy. In the PHEMT switch fabrication, Au/Ge/Ni/Au was used as the ohmic metal with total thickness of 410 nm. The Au/Ge alloy at 410 is commonly used to form low ohmic contact resistance and has good reliability.
For the ohmic contact formation, the ohmic contact was defined by conventional photolithography with undercut profile. Then O2 plasma descum was applied to
remove the residual photoresist on the pattern. The wafer was dipped in 10 % HCl solution for 1 min to remove native oxide from the surface before the ohmic metal deposition. Finally, Au/Ge/Ni/Au ohmic metal was deposited by e-gun evaporation. The ACE was used to lift-off for devices, and then the wafer was alloyed by RTA at 410 for 30 seconds to form ohmic contacts. The typical ohmic contact resistance was 0.12 Ωmm.
3.2.3 Recess and gate formation
The gate process includes wet chemical recess and gate photolithography. The gate recess process has two advantages. One is the gate is placed below the surface depletion layer of the surrounding material, preventing surface depletion from preventing current under forward gate bias, and the other one is gate recess will reduce channel thickness and drain-to-source saturation current. Consequently, gate recess process can increase device breakdown voltage, and decrease source-to-gate and gate-to-drain parasitic resistances. In the PHEMT switch fabrication, the wet chemical etching process was used for gate recess. The recess slot was defined by conventional photolithography. Then, a citric acid/H2O2/H2O solution was used to
etch the cap layer and AlAs as the etch stop layer until it reaches the target current for the gate-recess process. The target current will influence the PHEMT RF performance. The drain-to-source current is measured during the recess process to control the target current by curve tracer. After removing the recess photoresist, the gate openings were also defined by conventional lithography to form the gate lift-off photoresist profile. Before the gate metal deposition, the wafer was dipped in 10 % HCl solution for 1 min to remove the native oxide from the surface. Then that gate metal was deposited by e-gun evaporation. The gate metal is Ti/Pt/Au= 100/100/300 nm and the gate length of the devices was 0.5 µm. Ti has good adhesion to GaAs, Pt has a barrier to
prevent Au diffusing into GaAs, and Au has high electrical conductivity. Finally the wafer was immersed into ACE to lift-off the undesired metal.
3.2.4 Device passivation
Plasma enhanced chemical vapor deposition (PECVD) silicon nitride (Si3N4)
was used on the device for surface encapsulation because Si3N4 is less permeable to
ions than silicon dioxide (SiO2). The major purpose of the Si3N4 protective
encapsulation is simply for the surface passivation. This passivation protects the critical area of the originally exposed wafer surface from humidity, chemicals, gases, and particles. The Si3N4 film was grown at 300 . The precursors were SiH4/Ar, NH3,
and N2. The film refractive index was about 2.0, which were measured by
ellipsometer. In the PHEMT switch fabrication, the Si3N4 films were used for
passivation and as the dielectric for capacitors and were deposited by PECVD. The capacitance per unit area of the MIM capacitor was 0.25 fF/µm2 and the thickness of the dielectric was 200 nm.
After the passivation process, the contact via was defined for interconnections. Then the Si3N4 film was etched by reactive ion etching (RIE) system. The reactive
plasmas are CF4 and O2. The RF power is 80 W, and the pressure is 60 mtorr.
3.2.5 Interconnect metal line
The first metal consists of the adhesion layer Ti (30 nm) and the diffusion barrier Pt (70 nm), which was also used as the top plate of a MIM capacitor and the bottom layer of the interconnects. [12, 13]. A 2-µm-thick electroplated Cu was formed on the first metal (Ti/Pt) layers with an electroplated Cu seeding layer for interconnects. Then, the electroplated Cu was annealed at 200 for 2 h for eliminating the hydrogen embrittlement effect [29] and obtaining the film with the lowest resistivity
and the smoothest surface [30, 31]. Finally, a 100-nm-thick Si3N4 was deposited for
final passivation.
The AlGaAs/InGaAs PHEMTs used in the switches had a 0.5-µm gate length with dual fingers, and the drain-to-source spacing was 9 µm. The ohmic contact resistance for the PHEMTs was 0.12 Ω·mm, and the MIM capacitors used in the switches with 200-nm Si3N4 had a capacitance of 0.25-fF/µm2. A 3 kΩ of gate resistor
(Rg) between the signal and control terminal was designed to provide isolation
between the signal and control paths. The circuit schematic of the series/shunt SPDT switch is shown in Fig. 3.3. The control current of the GaAs SPDT switch is typically < 0.5 mA/mm.
The DC and RF electrical characteristics of the Cu switches were characterized to demonstrate the practicability of using the Cu interconnection on the SPDT switches. Thermal stability of the Pt diffusion barrier is a major concern in this study. To demonstrate the reliability of the Cu switches with the Pt diffusion barrier, the devices with the Cu interconnects were furnace annealed at 250 for 20 h in the nitrogen atmosphere. The DC characteristics before and after thermal annealing were compared to verify the thermal stability of the Cu-metallized switches. Besides, the long-term thermal stress of Cu switches was evaluated by using HTSL method, which was carried out by annealing at 150 for 144 h with no bias [18, 19, 20, 32]. To test the operation reliability of the Cu-metallized switches, the Cu-metallized switches were subjected to an on/off stress test (control voltage = +3/0 V exchange) for 24 h at room temperature. Furthermore, the temperature-dependent characteristics of the Cu-metallized switches are also studied.
3.3 MOS-PHEMT switch process
MOCVD. The sketch of the MOS-PHEMT cross section is shown in Fig. 3.4. The structure, from bottom to top, is comprised of a 600 nm GaAs/AlGaAs superlattice buffer layer, a 13 nm undoped In0.2Ga0.8As channel, a 3 nm undoped Al0.25Ga0.75As
spacer, a delta-doped layer, a 37 nm undoped Al0.25Ga0.75As barrier layer, a 1.5 nm
AlAs etch-stop layer and a 60 nm n+-GaAs cap layer.
The switches use dual-fingers 0.5 µm gate length MOS-PHEMT. Its processing includes the following steps: mesa isolation, wet chemical recess, oxidedeposition, ohmic formation, gate formation, interconnect metallization, and passivation. The mesa isolation was achieved by H3PO4/H2O2/H2O solution. The n+-GaAs cap layer
was selectively etched by citric acid/H2O2/H2O solution with AlAs layer as etch stop
layer. The AlAs layer was removed by HCl (10 %) solution. Then, the AlGaAs was treated with (NH4)2Sx at 60 for 30 mins before Al 2O3 deposition [33]. (NH4)2Sx
treatment before ALD Al2O3 deposition can reduce the interface trap density between
oxide and semiconductor and form a thin layer 5 ± 1 Å of sulfide on the surface [34], which results in further reduction of device leakage current. After (NH4)2Sx treatment,
16 nm Al2O3 was deposited at 300 as gate dielectric by ALD and was annealed at
500 for 60 s in forming gas. Ohmic contacts were Au/Ge/Ni/Au and were annealed at 410 for 30 s. Ti/Pt/Au gate metal was formed on Al2O3 layer. PECVD Si3N4 was used as the dielectric layer for the capacitors and for final passivation. The interconnect metals are comprised of a Ti/Pt adhesion layer with 2 µm plated Au.
FIGURES
Figure 3.2 Epitaxy structure of the PHEMT used in the Cu-metallized AlGaAs/InGaAs SPDT switches.
Chapter 4
SPDT GaAs Switches with Copper-Metallized Interconnects
4.1 Introduction
The Cu metallization process has been widely used in Si integrated circuit technology since IBM announced its success with Cu metallization in the Si very large scale integration process [1, 2, 3]. Traditionally, Ti/Au interconnect metal is widely used for the fabrication of GaAs based field effect transistors and MMICs and the reliability of the metal system has been well proven. In this study, we use Cu metal instead of Au metal as the interconnect metal for the AlGaAs/InGaAs PHEMT SPDT switches. The employment of Cu as the metallization metal has several major advantages over Au, such as lower resistivity, higher thermal conductivity, and lower cost.
Nevertheless, Cu diffuses very fast into GaAs if without any diffusion barrier and forms a deep acceptor to capture carrier in GaAs. It will lead to the failure of the electrical properties of the GaAs devices. In our previous research, we have demonstrated backside Cu metallization on GaAs MESFET using TaN as the diffusion barrier [9], Cu airbridge on low noise GaAs HEMTs using WNx as the
diffusion barrier [11], and fully Cu metallized InGaP/GaAs HBT using Pt as the diffusion barrier [12]. In this study, we choose Pt as the diffusion barrier metal since Pt is commonly used as the plate metal for the MIM capacitor of the switch. The Pt diffusion barrier was very effective in preventing Cu from diffusing into the conventional Schottky and ohmic metal in this study. The fabrication and the electrical performance of the SPDT MMIC switches using Cu metallization technology are reported for the first time.
4.2 Results and discussion
The switch developed in this study can be used in the WLAN system for switching between the transmitting and receiving modes. In this study, the series/shunt SPDT switch uses 0.5-µm gate length, dual-fingers AlGaAs/InGaAs PHEMTs. The gate resistor between the signal and control terminal has a value of 3 kΩ. Fig. 3.3 presents the circuit schematic of the series/shunt SPDT switch in Chapter 3. When the control voltage 1 (VCTRL1) is biased at 3 V and the control voltage 2
(VCTRL2) at 0 V, the RF signal is flowing from RFin to RFout1. Oppositely, the RF
signal path is from RFin to RFout2 as VCTRL1 is biased at 0 V and VCTRL2 at 3 V.
Compared with the HEMTs in the switch fabricated with conventional Au interconnects, the HEMTs in the switch fabricated using Cu metallization in this study showed similar DC characteristics. The HEMTs used in the Cu-metallized SPDT switches exhibited a drain saturation current density of 160 mA/mm and a transconductance of 140 mS/mm at VDS = 3 V. The devices had threshold voltage of
-1.5 V. The performances of insertion loss and isolation of the SPDT switches with Cu metallization and with Au metallization were measured at 2.5 GHz, respectively, and the results are as shown in Fig. 4.1. The Cu-metallized switch had an insertion loss of 0.33 dB and an isolation of 36.7 dB (control voltage = +3/0 V, input power = 0 dBm) at 2.5 GHz. The results in the RF characteristics showed very little deviation for the switches with Cu interconnects and the switches with Au interconnects. The deviation of these two switches is primarily due to the nonuniformity of the wet chemical etch in the gate recess process, which may influence the on-state resistance and off-state capacitance of the transistor dominating insertion loss and isolation. These RF results were consistent with the DC characteristics, which indicates that the use of Cu metallization would not increase the on-state resistance and the off-state capacitance of the active channel of the transistors and implies that the Cu
metallization could be applied to the interconnects of the SPDT switches without effecting the switch performance.
4.3 Reliability test
To test the thermal stability of the Pt diffusion barrier for long-term period, the Cu-metallized switches were annealed at 250 for 20 h, the DC characteristics of the HEMT device in the circuits after annealing are shown in Figs. 4.2 and 4.3. Although small degradation of the ohmic contact resistance was observed in Fig. 4.3, the drain saturation current density and the extrinsic transconductance of the device were not obviously influenced with very little change after annealing at 250 for 20 h, as shown in Figs. 4.2 and 4.3 (less than 1 % difference in drain saturation current density and less than 3 % difference in extrinsic transconductance). These results indicate that Cu–Pt interconnect layers are quite stable and that Pt is an effective diffusion barrier against Cu diffusion after thermal annealing. Thus, the Cu-metallized SPDT switches have maintained the electrical performance without any significant change during the high-temperature ambient test. Overall, the Cu-metallized SPDT switches have sustained the high temperature environment test without obvious DC performance degradation.
The RF performance of the Cu-metallized switches was also evaluated at high temperature. As shown in Fig. 4.4, the switch has an insertion loss of 0.33 dB and an isolation of 36.7 dB at 2.5 GHz before thermal test. After 144 h of high temperature storage life (HTSL) evaluation at 150 under nitrogen atmosphere, the Cu-metallized switches still possessed very good reliability with similar RF performance. The Pout–Pin relationships of the Cu-metallized switches at 2.5 GHz after
annealing at 150 under nitrogen atmosphere for different annealing time are as shown in Fig. 4.5. Input P1dB was kept at about 27 dBm without significant change
and maintained the same level without any obvious degradation after the long term test. Fig. 4.6 reveals that input third-order intermodulation intercept point (input IP3) of 50 dBm can be achieved at the input power of 15 dBm, and the trend of control current still remained stable. It suggests that no Cu diffusion into the active device region, and no degradation of on-state resistance and power handing capability for the transistors after thermal annealing occurred for the Cu-metallized SPDT switches using Pt as the diffusion barrier. Hence, the Cu-metallized switches demonstrated very good reliability and showed similar switch power handling capability after 144 h of HTSL environment test.
To test the operation reliability of the Cu-metallized switches, the Cu-metallized switches were subjected to an on/off stress test (control voltage = +3/0 V exchange) for 24 h at room temperature. As shown in Fig. 4.7, the Cu-metallized switches showed very little change after the stress test. The insertion loss and isolation still remained stable. Almost no obvious change in the insertion loss and isolation occurred, which indicated that no significant degradation of on-state resistance and off-state capacitance took place. It implies no Cu diffusion into the active device region for the transistors after control voltage exchange stress for the Cu-metallized SPDT switches using Pt as the diffusion barrier.
4.4 Conclusions
An SPDT GaAs switch fabricated with Cu-metallized interconnects using Pt as the diffusion barrier has been reported for the first time. The RF characteristics of the Cu-metallized SPDT switch exhibited an insertion loss of 0.33 dB and an isolation of 36.7 dB at 2.5 GHz, the performance is comparable to the SPDT switches fabricated using conventional Au interconnects. High power handling capability was achieved with input P1dB of 27 dBm and IIP3 of 50 dBm. Based on the high temperature
reliability tests including thermal stress test (annealing at 250 for 20 h) and HTSL environment test, no significant changes in the DC and RF characteristics were observed for the SPDT switches after these tests. To test the operation reliability of the Cu-metallized switches, the Cu-metallized switches were subjected to an on/off stress test for 24 h at room temperature and showed very little change of the insertion loss and isolation. It is evident from these data that the Cu metallization process developed is very reliable and can be used for the GaAs MMICs fabrication.
FIGURES
Figure 4.1 Insertion loss and isolation vs frequency of the SPDT switches with Cu and Au metallizations.
Figure 4.2 Transconductance and drain-to-source current versus VGS bias
characteristics of the Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches for 0.5-µm gate length before and after annealing at 250 for 20 h.
Figure 4.3 I–V characteristics of the Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches for 0.5-µm gate length before and after annealing at 250 for 20 h.
Figure 4.4 Insertion loss and isolation of the Cu-metallized SPDT switches at 2.5 GHz after annealing at 150 for different hours.
Figure 4.5 Insertion loss of the Cu-metallized SPDT switches with different input power levels at 2.5 GHz after annealing at 150 for different annealing periods.
Figure 4.6 Input IP3 and control current of the Cu-metallized SPDT switches with different input power levels at 2.5 GHz after annealing at 150 for different annealing periods.
Figure 4.7 Insertion loss and isolation versus frequency of the Cu-metallized AlGaAs/InGaAs 0.5-µm PHEMT SPDT switches before and after on/off stress test for 24 h at room temperature.
Chapter 5
Evaluation of Electrical Characteristics of the Copper-Metallized SPDT
GaAs Switches at Elevated Temperatures
5.1 Introduction
Cu has been used instead of Al as the interconnect metal for Si integrated circuit technology since IBM adapted Cu metallization in the Si 0.18-µm technology [1, 2, 3]. The advantages of using Cu metallization for Si technology include low resistivity and high electromigration resistance; however, there are only a few reports on the Cu metallization of GaAs devices. Ti/Au interconnect metal has been extensively used for the manufacture of GaAs-based field-effect transistors and MMICs, and the reliability of the metal system has been well proven. The application of Cu as the metallization metal for GaAs devices has several superior advantages over Au, such as lower resistivity, higher thermal conductivity, and lower cost, as compared with Au. In this paper, we characterized the electrical performance of the Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches and compare the performance with the Au-metallized GaAs SPDT switches.
Cu diffuses very fast into GaAs if without any diffusion barrier and forms a deep acceptor in GaAs, which leads to the failure of the electrical properties of the GaAs devices. It was previously demonstrated that TaN can be used as the diffusion barrier for the backside Cu metallization on GaAs MESFETs [9, 10] and that WNx can be
used as the diffusion barrier for Cu airbridges on low-noise GaAs HEMTs [11]. Furthermore, Pt was used as the diffusion barrier layer for Cu-metallized switches [13], and an Au-free fully Cu-metallized InP HBT was also realized using Ti/Pt/Cu nonalloyed ohmic contacts with Pt as the diffusion barrier [14]. It has also been demonstrated that the Ti/Pt/Cu system structure was very stable even after being
annealed up to 350 and that Cu started to diffuse through the Pt diffusion barrier and formed a Cu4Ti phase after being annealed at 400 , as investigated by X-ray
diffraction data, Auger electron spectroscopy depth profiles, and the sheet resistance measurement [12]. In this paper, the temperature-dependent characteristics of the Cu-metallized switches are studied. The thermal stability of the Pt diffusion barrier and the electrical reliability are also investigated.
5.2 Results and discussion
The HEMTs in the switch fabricated using Cu metallization showed similar DC characteristics in comparison with those in the switch fabricated with traditional Au metallization. As shown in Figs. 5.1 and 5.2, a drain saturation current density of 160 mA/mm and an extrinsic transconductance of 140 mS/mm at VDS = 3 V were
measured both for the Cu- and the Au-metallized switches. The devices had a threshold voltage (Vth) of −1.5 V. The insertion loss, return loss, and isolation
characteristics of the SPDT switches with Cu metallization and with Au metallization measured at 2.5 GHz are shown in Figs. 5.3 and 5.4, respectively. The Cu-metallized switch had an insertion loss of 0.33 dB, a return loss of 23.3 dB, and an isolation of 36.7 dB (control voltage = +3/0 V; input power = 0 dBm) at 2.5 GHz. There is very little difference in the RF characteristics for the switches with Cu interconnects and with Au interconnects. The small differences of these two switches were due to the nonuniformity of the wet chemical etch in the gate recess process. The nonuniformity of the wet chemical etch could cause the fluctuation of the on-state resistance and off-state capacitance of the transistors which dominate insertion loss and isolation [13]. It appears from these data that Cu metallization does not affect the SPDT HEMT switch performance.
characteristics of the Cu-metallized switches, the switches were evaluated at different temperatures. The DC characteristics of the device were measured at different temperatures from 300 °K to 500 °K. Fig. 5.5 shows the current–voltage (I–V) characteristics at different high-temperature ambients. The extrinsic transconductance and the drain-to-source current versus the temperature for the Cu-metallized SPDT switches were shown in Fig. 5.6. A drain saturation current density of 188 mA/mm and an extrinsic transconductance of 159 mS/mm at VDS = 3 V at 300 °K were
measured for the devices. While the background carrier concentration from the substrate rises exponentially with temperature, causing the 2-DEG concentration (n2DEG) to increase in the active layer, the carrier velocity (ν) degraded seriously by
the lattice scattering and carrier–carrier scattering mechanisms [35]. Therefore, IDSS0
drops at high temperatures due to the enhanced scattering mechanisms even though the carrier concentration increases at high temperatures.
Furthermore, the gate leakage current (IG) as a function of the gate-to-drain
voltage (VGD) is shown in Fig. 5.7. When the gate-to-drain voltage was biased at −22
V, the gate leakage currents were 430, 450, and 490 µA/mm at the temperatures of 300 °K, 380 °K, and 500 °K, respectively. The gate leakage current increases with increasing temperature mainly due to the tunneling mechanism with thermionic emission and partly caused by the reduction of barrier height [36].
Fig. 5.8 shows that the Vth decreases with increasing temperature. The Vth of a
δ-doped HEMT can be obtained by solving the 1-D Poisson’s equation (5.1) as follows [35, 37]: ε ) ( 2 d d n q E q V B c DEG d h t = Φ −∆ − +∆ (5.1) Among the aforementioned parameters, ΦB is the Schottky gate barrier height, ∆Ec is
![Figure 2.3 Typical I-V characteristics of a depletion mode field-effect transistor [15]](https://thumb-ap.123doks.com/thumbv2/9libinfo/8747380.205228/30.892.193.704.128.654/figure-typical-characteristics-depletion-mode-field-effect-transistor.webp)
![Figure 2.4 Equivalent circuit of a switching FET [15].](https://thumb-ap.123doks.com/thumbv2/9libinfo/8747380.205228/31.892.139.750.115.349/figure-equivalent-circuit-switching-fet.webp)
![Figure 2.6 Output power spectrum of the two-tone input signal [27].](https://thumb-ap.123doks.com/thumbv2/9libinfo/8747380.205228/33.892.180.711.143.562/figure-output-power-spectrum-tone-input-signal.webp)
