Chapter 1 Introduction
1.2 Outline of the Dissertation
This dissertation covers the related studies of the novel SPDT switch technologies including the Cu-metallized AlGaAs/InGaAs PHEMT switches and the MOS-PHEMT switches. The contents are divided into 7 chapters. In Chapter 2, the introduction to the GaAs switch characteristics and the device equivalent circuit schematic are briefed. Then, the detailed fabrication process of the Cu-metallized switch and the MOS-PHEMT switch is described in Chapter 3.
In Chapter 4, the Cu-metallized AlGaAs/InGaAs PHEMT SPDT switches utilizing Pt (70 nm) as the diffusion barrier is reported. In comparison with the Au-metallized switches, the RF performance and the power handling capability of the Cu-metallized switches at 2.5 GHz were evaluated. To test the thermal stability of the Pt diffusion barrier, these switches were annealed at 250 for 20 h. In addition, after the high temperature storage life (HTSL) environment test at 150 for 144 h was carried out for these Cu-metallized switches, the RF characteristics and the power handling capability were observed. To test the operation reliability of the Cu-metallized switches, the Cu-metallized switches were subjected to on/off (control voltage = +3/0 V exchange) stress test for 24 h at room temperature.
In Chapter 5, in order to evaluate the temperature-dependent impact on DC and RF characteristics of the Cu-metallized switches for high-temperature applications, the switches were tested at different temperatures. The low thermal threshold coefficients (δVth/δT) of the device were evaluated from 300 °K to 500 °K, the microwave performance at 380 °K at 2.5 GHz was evaluated.
In Chapter 6, an AlGaAs/InGaAs MOS-PHEMT SPDT switch is fabricated using
Al2O3 high-κ gate dielectric by ALD for RF switch application. The MOS-PHEMT exhibited the comparable DC performance and much lower gate current as compared to the conventional PHEMT. The RF test and an input power for one dB compression (input P1dB) of the MOS-PHEMT switch at 2.5 GHz were measured. The MOS-PHEMT MMIC switch was realized using ALD Al2O3 gate dielectric in this study.
Chapter 7 is the conclusions of the dissertation.
TABLE
Table 1.1 Properties comparisons of the possible interlayer metals [8].
Property\Metal Cu Ag Au Al
Resistivity (µΩ cm) 1.67 1.59 2.35 2.66 Young’s modulus(10-11 dyn/cm2) 12.98 8.27 7.85 7.06 Thermal Conductivity (W/cm°K) 3.98 4.25 3.15 2.38
CTE(106) 17 19.1 14.2 23.5
Melting Point ( ) 1085 962 1064 660 Specific heat Capacity (J/Kg•K) 386 234 132 917 Corrosion in air Poor Poor Excellent Good
Deposition
Sputtering Yes Yes Yes Yes
CVD Yes No No No
Evaporation Yes Yes Yes Yes
Etching
Dry No No No Yes
Wet Yes Yes Yes Yes
Resistance to Electromigration High Very Low Very High Low
Delay Time (ps/mm) 2.3 2.2 3.2 3.7
Chapter 2
Theory of Filed-effect-transistor Based Switch
2.1 Comparisons between FET Swicth and PIN Switch
The transmitter/receiver (Tx/Rx) switches are important components as common as amplifiers and mixers in microwave systems as shown in Fig. 2.1. Because of the booming demands for RF switches in cellular handset, base station, bluetooth, and WLAN systems, high performance GaAs RF switches become very important. Tx/Rx
switch is for changing the RF signal path to transmitter or receiver. Therefore, a low insertion loss, high isolation and high power handling capability characteristics are needed for switches to improve the overall system performance for wideband frequency. Traditionally the PIN diode has been widely used for switching RF signals.
However, PIN diodes have high insertion loss with high bias current. Thus, the GaAs switches predominate over the commercial RF switches because of its low on resistances, low off capacitances and high linearity for the switch market. GaAs PHEMT has been commercially applied in RF switches and power amplifier for wireless communication applications. Owing to its higher charge density and higher saturated electron velocity in InGaAs channel compared to the GaAs MESFET, PHEMT performs lower insertion loss for switch, and higher power gain and power added efficiency for power amplifier [18]. For realizing practical RF switch based on AlGaAs/InGaAs PHEMTs, two major factors must be emphasized: First, reduction of the on-state-resistance (Ron) at Vgs = 0 V for insertion loss. Second, reduction of the off-state-capacitance (Coff) when the Vgs is below Vth for isolation [19]. Besides, the depletion mode PHEMT is used for most commercial RF switches. Although switches can also use the enhancement mode PHEMT device, the performance of the power handling capability is poor. Therefore, it is straightforward to design the depletion
mode PHEMT switches [15]. Therefore, PHEMT switches have become prevalent because the field effect transistor (FET) switches have advantages over diode switches for low power consumption, good RF performance, and easy monolithic circuit integration [20].
2.2 Antenna Switch Design
The typical circuit schematic of the antenna SPDT switch is shown in Figs. 2.2(a) and 2.2(b) for the transceiver construction and the SPDT switch is designed for two control voltages to inversely feed to the transistor pairs. One control voltage is high and the other control voltage is low. In transmit mode, the shunt FET in the transmit path is off, whereas the series FET is on. The transmit signal is flowing to the antenna.
Meanwhile, the shunt FET in the receiver stem is on, while the series FET is off preventing the transmit signal in the receiver. Oppositely, in the receive mode the control voltages are reversed. Therefore, switch isolation can easily be improved by joining shunt mounted FET without excessive increase of insertion loss [15]. As mentioned above, the gate widths of the series and shunt devices have to be detailed designed to optimize tradeoff between insertion loss in on-state and isolation in off-state [21].
2.3 Equivalent Circuit of a Switch Used FET
The drain-to-source resistance of the FET in the channel behaves as a voltage variable resistor for a switch, and the gate-to-source voltage (Vgs) controls the resistance. Therefore, the FET switch is a three-terminal device in which the Vgs
determines the on/off states. A FET for a switch is biased with the drain and source at zero voltage DC. The RF signal path is flowing from drain to source and the gate is the control terminal. Fig. 2.3 shows the typical current-voltage characteristics of a
depletion mode FET about Vds = 0 V at different Vgs. The Vds/Ids characteristic approaches a resistance (Ids/Vds) in the region of Vds= 0V. This is a low resistance at Vgs = 0 V. Oppositely, the FET is off as Vgs below pinch-off voltage with a high resistance. This simple equivalent circuit is shown in Fig. 2.4. The gate resistor (Rg) with the value of several kΩ is designed to provide extra isolation between the signal and control terminal. Very little gate current below 0.5 mA/mm for FETs can be obtained. Therefore, the FET switches have very low DC power consumption as compared to PIN diode switch [15].
Fig. 2.5(a) depicts an equivalent circuit schematic for a GaAs FET used in switching applications. The FET serves as a passive two-terminal device, which the gate terminal acts as the control signal port in passive mode. The RF signal flows between the drain and source. The gate terminal determines the RF impedance between the drain and source. The drain-to-source impedance varies from a low value under open channel when the gate is biased at zero voltage, to a high value when the gate is biased at pinch-off voltage to prevent current from flowing through the transistor.
When the low-impedance state of the FET switch is dominated by the fully open channel in passive mode, the device channel resistance is low. Owing to the low channel resistance, the insertion loss is independent of frequency [22]. The practical equivalent circuit is the “on” resistance for the transistor, and the reduction of on-state resistance and insertion loss can be improved by the large device width. In the high-impedance state, the PHEMT is dominated by the pinched-off channel or large
“off” resistance as shown the switch equivalent circuit in Fig. 2.5(b). While rg is much smaller than the reactance of Cg
[
rg ≤1/(ωCg)]
, the equivalent circuit of Fig. 2.5(a) can be substituted by a parallel combination of Roff and Coff as shown in Fig. 2.5(b),where Roff and Coff are expressed as shown in equation (2.1) and (2.2):
where ω is the operating frequency in radians/second [23]. The “off” state resistance Roff is an inverse function of the operating frequency ω, and reduces as frequency increases according to the equation (2.2). The off-state performance of the switch will degrade at high frequency [24]. Furthermore, the degradation of the isolation in the off-state would be also resulted from increases of gate-to-source, gate-to-drain capacitance, and source-to-drain fringing capacitance by large device width [22].
Therefore, the device gate width must be optimized for better RF performance.
2.4 RF Characteristics of a Switch 2.4.1 Insertion Loss (IL)
Insertion loss (IL) in the on state is defined as the difference (dB) between the power received at the load before and after the insertion of the switch [25]. In view of this definition, insertion loss for the switch in the on state is expressed as shown in equation (2.3):
P0= power delivered to the load with an ideal switch in the on state.
PL= power delivered to the load with the practical switch in the on state.
2.4.2 Isolation
Isolation in the off state is defined as the difference (dB) between the power
delivered to the load for an ideal switch in the on state and the actual power delivered to the load when the switch is in the off state [25]. In view of this definition, isolation is expressed as shown in equation (2.4):
)
P0 = power delivered to the load with an ideal switch in the on state.
P’L = power delivered to the load with the practical switch in the off state.
2.4.3 Power Handing Capability
The FET switch maximum handling power (Pmax) is evaluated in the on-state and in the off-state. Pmax is expressed in equation (2.5) and (2.6) [17]:
2
From the practical consideration for the power limitation of the switch operation is explained in [26], and the maximum input power Pmax is expressed by equation
threshold voltage.
2.4.4 Input third-order intermodulation intercept point and third-order intermodulation distortion
In wireless communication system, multi-channel transmission is practically used for signal transmission [27]. The transmission bandwidth of communication system was divided into multiple information bandwidths and used multiple frequencies for data transmission to increase the transmission capacity. Nevertheless, when the system operating frequencies are more than two and the neighboring frequencies are located closely to each other, the device used in system will generate intermodulation distortion.
For analyzing the intermodulation distortion, two-tone signal consists of two signals as the input with the same amplitude at two closely spaced signals 5-10 MHz apart as shown in Fig. 2.6. Among all the intermodulation distortions of the devices, third-order intermodulation distortion (IM3) and the third-order intercept point (IP3) will dominate the device linearity because of device gain compression. Therefore, IM3 and IP3 of the devices have become the important factors for wireless communication applications. Input third-order intermodulation intercept point (IIP3) is defined as shown in equation (2.8):
)
FIGURES
Figure 2.1 Radio frequency front-end system.
(a)
Vdd VCTRL1VCTRL2
RgRg RgRg
(b)
Figure 2.2 (a) Specific schematic of an antenna switch. (b) Circuit schematic of a single-pole-double-throw antenna switch [21].
Figure 2.3 Typical I-V characteristics of a depletion mode field-effect transistor [15].
Figure 2.4 Equivalent circuit of a switching FET [15].
C
gC
gr
gr
gC
dsS o u rc e D ra i n
r
dG a t e
(a)
(b)
Figure 2.5 (a) Equivalent circuit schematic for a GaAs FET for switching applications.
(b) Simplified off-state equivalent circuit for a FET switch in high-impedance state [23].
Figure 2.6 Output power spectrum of the two-tone input signal [27].
Chapter 3
Fabrication of Copper-Metallized GaAs Switch and MOS-PHEMT Switch
3.1 Introduction of PHEMT switch process
The five major steps of the series/shunt SPDT PHEMT switch process are device active region definition, ohmic metal deposition and annealing, gate formation by wet chemical recess and gate photolithography, device passivation, and interconnection formation [27]. The schematic cross section of the PHEMT switch is shown in Fig.
3.1. The detailed fabrication process of the Cu-metallized switch and the MOS-PHEMT switch will be described in the following section.
3.2 Cu-metallized switch process 3.2.1 Device active region definition
Device active region definition is to confine the electrically conductive part of the device to specific parts of its surface area so that electrical current is prevented from flowing to other active areas [28]. The electrically conductive region is called the “active region”. The GaAs PHEMT was etched to separate each device and to reduce the leakage current from the substrate for the isolation. The functions of the active region definition consist of the active region formation, device isolation, reduction of parasitic capacitance, parasitic resistance, leakage current, and back-gating effect.
The AlGaAs/InGaAs PHEMT SPDT switch wafer was grown by metal organic chemical vapor deposition (MOCVD) on a 4-in semi-insulating GaAs substrate. The structure, from bottom to top, is composed of a 600-nm GaAs/AlGaAs superlattice buffer, a 13-nm undoped InGaAs channel, a 3-nm undoped AlGaAs spacer, a delta-doped layer, a 37-nm undoped AlGaAs Schottky layer, and a 60-nm n+-GaAs
capping layer, as shown in Fig. 3.2. The Hall electron mobility and sheet carrier concentrations at room temperature are 6500 cm2/V s and 3.0 x 1012 cm-2, respectively.
The device fabrication was carried out by the use of traditional lithography and lift-off technique. In the PHEMT switch fabrication, the device active region and the epitaxial resistor formation are defined by photolithography. The wafer was etched to buffer layer to obtain a good isolation. Then the mesa isolation and epitaxial resistors were formed utilizing H3PO4/H2O2/H2O mixing solution. After mesa etching, we measured the etching depth by α-stepper to achieve the etch depth of about 400 nm, and checked the etched profile by scanning electron microscope (SEM).
3.2.2 Ohmic contact formation
The ohmic contact is formed by ohmic metal deposition and annealing. An ohmic contact is a low resistance junction between metal and semiconductor interface.
Lower contact resistance will reduce device on-resistance and device power consumption. Therefore, in order to obtain good ohmic contact with low parasitic resistance, the semiconductor is doped heavily to form good contacts. After the ohmic metals deposition, a high temperature alloying process using rapid thermal anneal (RTA) was conducted to form the ohmic contacts.
For the ohmic metal layer formation, the germanium (Ge) is used for doping the GaAs and the nickel (Ni) is acted as a wetting agent and prevents the AuGe metal from “balling up” during alloy. In the PHEMT switch fabrication, Au/Ge/Ni/Au was used as the ohmic metal with total thickness of 410 nm. The Au/Ge alloy at 410 is commonly used to form low ohmic contact resistance and has good reliability.
For the ohmic contact formation, the ohmic contact was defined by conventional photolithography with undercut profile. Then O2 plasma descum was applied to
remove the residual photoresist on the pattern. The wafer was dipped in 10 % HCl solution for 1 min to remove native oxide from the surface before the ohmic metal deposition. Finally, Au/Ge/Ni/Au ohmic metal was deposited by e-gun evaporation.
The ACE was used to lift-off for devices, and then the wafer was alloyed by RTA at 410 for 30 seconds to form ohmic contacts. The typical ohmic contact resistance was 0.12 Ωmm.
3.2.3 Recess and gate formation
The gate process includes wet chemical recess and gate photolithography. The gate recess process has two advantages. One is the gate is placed below the surface depletion layer of the surrounding material, preventing surface depletion from preventing current under forward gate bias, and the other one is gate recess will reduce channel thickness and drain-to-source saturation current. Consequently, gate recess process can increase device breakdown voltage, and decrease source-to-gate and gate-to-drain parasitic resistances. In the PHEMT switch fabrication, the wet chemical etching process was used for gate recess. The recess slot was defined by conventional photolithography. Then, a citric acid/H2O2/H2O solution was used to etch the cap layer and AlAs as the etch stop layer until it reaches the target current for the gate-recess process. The target current will influence the PHEMT RF performance.
The drain-to-source current is measured during the recess process to control the target current by curve tracer. After removing the recess photoresist, the gate openings were also defined by conventional lithography to form the gate lift-off photoresist profile.
Before the gate metal deposition, the wafer was dipped in 10 % HCl solution for 1 min to remove the native oxide from the surface. Then that gate metal was deposited by e-gun evaporation. The gate metal is Ti/Pt/Au= 100/100/300 nm and the gate length of the devices was 0.5 µm. Ti has good adhesion to GaAs, Pt has a barrier to
prevent Au diffusing into GaAs, and Au has high electrical conductivity. Finally the wafer was immersed into ACE to lift-off the undesired metal.
3.2.4 Device passivation
Plasma enhanced chemical vapor deposition (PECVD) silicon nitride (Si3N4) was used on the device for surface encapsulation because Si3N4 is less permeable to ions than silicon dioxide (SiO2). The major purpose of the Si3N4 protective encapsulation is simply for the surface passivation. This passivation protects the critical area of the originally exposed wafer surface from humidity, chemicals, gases, and particles. The Si3N4 film was grown at 300 . The precursors were SiH4/Ar, NH3, and N2. The film refractive index was about 2.0, which were measured by ellipsometer. In the PHEMT switch fabrication, the Si3N4 films were used for passivation and as the dielectric for capacitors and were deposited by PECVD. The capacitance per unit area of the MIM capacitor was 0.25 fF/µm2 and the thickness of the dielectric was 200 nm.
After the passivation process, the contact via was defined for interconnections.
Then the Si3N4 film was etched by reactive ion etching (RIE) system. The reactive plasmas are CF4 and O2. The RF power is 80 W, and the pressure is 60 mtorr.
3.2.5 Interconnect metal line
The first metal consists of the adhesion layer Ti (30 nm) and the diffusion barrier Pt (70 nm), which was also used as the top plate of a MIM capacitor and the bottom layer of the interconnects. [12, 13]. A 2-µm-thick electroplated Cu was formed on the first metal (Ti/Pt) layers with an electroplated Cu seeding layer for interconnects.
Then, the electroplated Cu was annealed at 200 for 2 h for eliminating the hydrogen embrittlement effect [29] and obtaining the film with the lowest resistivity
and the smoothest surface [30, 31]. Finally, a 100-nm-thick Si3N4 was deposited for between the signal and control paths. The circuit schematic of the series/shunt SPDT switch is shown in Fig. 3.3. The control current of the GaAs SPDT switch is typically
< 0.5 mA/mm.
The DC and RF electrical characteristics of the Cu switches were characterized to demonstrate the practicability of using the Cu interconnection on the SPDT switches. Thermal stability of the Pt diffusion barrier is a major concern in this study.
To demonstrate the reliability of the Cu switches with the Pt diffusion barrier, the devices with the Cu interconnects were furnace annealed at 250 for 20 h in the nitrogen atmosphere. The DC characteristics before and after thermal annealing were compared to verify the thermal stability of the Cu-metallized switches. Besides, the long-term thermal stress of Cu switches was evaluated by using HTSL method, which was carried out by annealing at 150 for 144 h with no bias [18, 19, 20, 32]. To test the operation reliability of the Cu-metallized switches, the Cu-metallized switches
To demonstrate the reliability of the Cu switches with the Pt diffusion barrier, the devices with the Cu interconnects were furnace annealed at 250 for 20 h in the nitrogen atmosphere. The DC characteristics before and after thermal annealing were compared to verify the thermal stability of the Cu-metallized switches. Besides, the long-term thermal stress of Cu switches was evaluated by using HTSL method, which was carried out by annealing at 150 for 144 h with no bias [18, 19, 20, 32]. To test the operation reliability of the Cu-metallized switches, the Cu-metallized switches