General Background and Motivation

Continually scaling down Si-transistors is always the way to sustain Moore’s law for last 30 years. But, it is expected that the dimension will reach about 10 nm by 2011 [1-1], which would be the ultimate limitation for Si CMOS. Fig. 1.1 [1-2, 1-3] lists the trend of transistor technology. Therefore, identifying a new logic device technology becomes an urgent issue.

Candidates, which are often mentioned, are carbon nanotube (CNT) transistors, semiconductor nanowires and spintronics [1-4], etc. While the majority of the technologies mentioned above are still in the prototyping stage. On the contrary, III-V devices especially the Quantum Well Field Effect Transistors (QWFETs) gradually unfold potential because of their relatively mature technology and excellent performance. In general, III-V materials own high carrier transport properties like high electron mobility, high electron peak velocity, low electron effective mass, reasonable energy band-gap and high quantum confinement in the channel region. For InAs material used in this research, the bulk electron mobility is around 40000 cm²V^-1S^-1 at room temperature. The detailed material properties of Si, Ge and III-V materials are listed in Table 1.1 [1-5]. Recently, many researches of III-V devices especially QWFETs with high indium concentration InxGa1-xAs channel materials exhibiting excellent DC and RF performance have been published [1-6, 1-7]. Endowed with these extraordinary electron transport properties, it seems imperative to evaluate the potential of InxGa1-xAs QWFETs for future beyond CMOS logic applications.

On the other hand, for future millimeter/sub-millimeter wave wireless-communication

applications including mobile radio systems and passive imaging systems etc., low noise amplifiers (LNAs) with extremely low noise figure, high gain and low DC power consumption are in highly demand. In order to meet the continuously growing requirement, the technique to improve devices performance becomes more and more rigid and challenging.

However, InxGa1-xAs QWFETs also show great potential in this field. InxGa1-xAs QWFETs have demonstrated the best noise/gain performance and low power dissipation under ultra high frequency operation [1-8, 1-9]. Therefore, using InxGa1-xAs QWFETs for future high-speed millimeter wave wireless-communication applications are the most promising.

Furthermore, with the further improvement of InxGa1-xAs QWFETs in frequency dependent performance, the applications expanding the radio spectrum resources to sub-millimeter wave (300 GHz - 3 THz) frequency region for new generation of military, telecommunications and radio astronomy applications are also worth expecting.

In this study, in order to exhibit the excellent performance of InAs QWFETs in high-speed, low-noise, low-power RF and logic applications, several approaches have been adopted. These efforts include the applications of exquisite electron beam lithography technique for 40 nm gate length, advanced two-step recess fabrication, platinum (Pt) gate sinking process, and other precise process adjustments. As a result of the good electronic transport properties of InAs materials, terrific band-gap engineering design of QWFET and advanced fabrication process, the InAs QWFETs in this study exhibit excellent DC, RF, noise and logic performance, which makes them feasible for future high-speed, low-voltage digital as well as high frequency millimeter/sub-millimeter wave applications.

1.2 Outline of this Thesis

This thesis focuses on the study of RF and logic evaluation of 40 nm InAs channel QWFETs.

In chapters 2, the overview including the basic mechanism and literature survey of III-V QWFETs is described. The detailed fabricating processes of the InAs QWFETs are introduced in chapter 3. In chapter 4, the fundamentals of electrical DC and RF characteristics of the device are described.

The experimental results and discussions are shown in chapter 5 and which are divided into three parts. The first part discusses the effect of advanced two-step recess process and Pt gate sinking process on 40 nm InAs QWFETs for RF application. Due to the narrow energy gap feature of InAs material, the impact ionization phenomena is easily occurred. So in the second part, the impact ionization phenomena of InAs QWFETs are studied and the optimum bias conditions for RF operation are also discussed. Beside the application of InAs QWFETs in high frequency millimeter-wave region, the logic characteristics of InAs QWFETs are also evaluated. In the third part of discussion, the important figures of merit relevant to logic such as gate delay, ION/IOFF, DIBL, and S of the InAs-channel QWFETs are studied.

Finally, the conclusion of the thesis is given in chapter 6. The 40 nm InAs QWFETs exhibit great potential both in low-voltage, high-speed, low-noise RF applications as well as high-performance logic applications.

Fig. 1.1 The trend of transistor technology.

Table 1.1 Physical properties of electron and hole of Si, Ge, and main III-V semiconductors.

Chapter 2

Overview of III-V Quantum-Well Field-Effect Transistors (QWFETs)

2.1 The Theory of III-V QWFETs

Quantum-well field-effect transistor (QWFET) or called High electron mobility transistor (HEMT) is one of the most mature III-V semiconductor transistors. The first demonstration of this device was made by Fujitsu Lab. in 1980 [2-1]. Fig. 2.1 represents a cross-sectional view of a conventional QWFET structure. The epitaxial layers of the QWFET structure are designed to form two-dimension electron gas (2-DEG) in the channel layer. The explanation of 2-DEG formation by energy band diagram of InxAl1-xAs/InxGa1-xAs Metamorphic HEMT is shown in Fig. 2.2 [2-2]. When the small electron affinity (χ) and high energy band-gap (Eg) InxAl1-xAs material connects to the large electron affinity (χ) and low energy band-gap (Eg) InxGa1-xAs material, due to the Fermi-level (Ef) of these two materials must reach the horizontal balance andχ as well as Eg must remind the same value for each materials, there will generate the discontinuity of conduction band (Ec) in the junction. This discontinuity will cause partial Ec of InxGa1-xAs below the Ef so the mass electrons will accumulate in this 2-DEG quantum well. These electrons move fast in 2-DEG because they were accumulated in intrinsic and high electron mobility InxGa1-xAs material channel. As a result of the terrific band-gap engineering design of QWFETs, the QWFETs can exhibit superior carrier transport characteristics. For the past few years, GaAs-based MHEMTs or InP-based HEMTs with remarkable device performance in high speed applications have been published frequently.

2.2 The Structure of III-V QWFETs

In general, the epitaxial layers of the InxGa1-xAs-channel QWFETs were grown by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) on InP/GaAs substrates, and the common expitaxial structures of the InxGa1-xAs-channel QWFETs for high frequency application are shown in Fig. 3.1.

As Fig. 2.3 shown, the structure layers from bottom to top are composed of a InxAl1-xAs metamorphic buffer layer, a InGaAs-based channel layer optionally combining with sub-channel, a In0.52Al0.48As spacer layer, a δ-doped carrier supply layer, a In0.52Al0.48As barrier layer, a InP etching stop layer and a highly Si-doped InxGa1-xAs cap layer.

The InxAl1-xAs metamorphic buffer layer is used to release the lattice mismatch between InxGa1-xAs channel and GaAs/InP substrate. Therefore, the high indium content (50%-100%) of the InxGa1-xAs channel layer can be achieved in spite of the large lattice mismatch between the active channel layer and the substrate. The adhesion of InxGa1-xAs sub-channels could enhance the electron confinement in the thin and low energy band-gap main channel layer and further improve the electron transport properties [2-3]. The In0.52Al0.48As spacer layer is applied to form heterostructure interface with InGaAs-based channel so that the band diagram discontinuity occurred, and the 2-DEG formed. A δ-doped layer with Si doping concentration could provide extra carriers to the channel layer. And an InP layer can provide a good gate recess etching stop layer as well as a good surface passivation of InxAl1-xAs layer to avoid kink effect and reduce the hot-electron surface damage [2-4]. Besides, with the use of the InP etching stop layer, the lateral recess length (Lr) can be easily controlled and RF performance can be improved [2-5, 2-6]. Finally, the highly Si-doped InxGa1-xAs cap layer is used to reduce the contact resistance.

2.3 III-V QWFETs for High Frequency Millimeter/Sub-Millimeter Wave Applications

In recent years, the millimeter-wave has shown large impact on our daily communication life. The applications of millimeter wave for communication include gigabit wireless system, cellular backbone, national weaponry, traffic guidance, radar, radio navigation device, etc.

Besides, other emerging applications such as homeland security, medical diagnosis, and high-resolution image sensor have even moved to sub-millimeter wave band. With the rapid progress of communication industries, the required performances for the high frequency components are getting more and more rigid.

Among all the electronic devices, III-V based compound semiconductor devices such as pseudomorphic GaAs HEMTs (PHEMTs), metamorphic GaAs HEMTs (MHEMTs), lattice-matched or pseudomorphic high indium mole fraction InxGa1-xAs channel InP HEMTs have shown great potential in millimeter/sub-millimeter wave applications. Recently, by advanced improvement of process, the InxGa11-xAs QWFETs in literature have achieved current-gain cutoff frequency (fT) of 628 GHz [2-7], maximum oscillation frequency (fmax) above 1 THz [2-8], extrinsic transconductance (gm) of 3 S/mm [2-9], and minimum noise figure (NFmin) of 0.8 dB at 90 GHz [2-10]. Consequently, they are regarded as key devices for next-generation millimeter/sub-millimeter wave systems. Table 2.1 [2-7~2-11] lists the best record of QWFETs in high speed and low noise catalog in the last three years.

2.4 Evaluations of III-V QWFETs for Beyond-CMOS Logic Applications

For the post-Si era of logic CMOS, III-V compound semiconductors have emerged as promising channel materials, which is not only for their potential in high-speed and low-power performance, but the III-V device technology is relatively mature and reasonably

reliable [2-12] compared to other novel devices such as carbon-nanotube transistors and semiconductor nanowires. Recently, nano gate length InxGa1-xAs QWFETs with outstanding logic performance at low supply voltage have been demonstrated [2-13]. Therefore, using III-V materials as channel for future logic CMOS applications have been noticeable.

In digital application, a transistor operates as a switch, which is different from analog for microwave or millimeter wave application. As seen from the Fig. 2.4, there’re some electrical figures of merit of a transistor as a switch in digital application [2-13], like drain-induced barrier lowering (DIBL), subthreshold slope (S), on-state and off-state current ratio (ION/IOFF), and the gate delay time (CV/I). But for non-optimized devices, arbitrary selections of threshold voltage (VT), ION and IOFF can easily result in an over-estimation of the logic parameters. In this study, the methodology proposed by Chau [2-12, 2-14] to analyze new devices which often feature non-optimized values of VT were adopted. The evaluation methodology is shown in Fig. 2.5. First, select gate-source voltage at drain-source current of 1 mA/mm as the VT. Then select ION as 2/3 VCC swing above VT, and IOFF as 1/3 VCC swing below VT. Based on this definition, the logic parameters, such as subthreshold slope, DIBL and ION/IOFF ratio of InxGa1-xAs QWFETs can be extracted.

The steepness of the device transition between the ON and OFF states is evaluated through the subthreshold slope and ION/IOFF ratio. And the tightness of the threshold voltage is evaluated by drain-induced barrier lowering (DIBL), for which measures the change in VT as a result of a change in VDS. If DIBL is small, VT is insensitive to circuit design details and manufacturing variations. Subthreshold slope and DIBL often go hand in hand and they reflect the overall electrostatic integrity of the device. Besides, device capacitance impacts the switching speed. An important figure of merit in this regard is the transistor delay (CV/I), which is a measure of the time that it takes for a transistor to switch an identical one.

Fig. 2.1 Conventional QWFET structure

Fig. 2.2 Band Diagram of InxAl1-xAs/InxGa1-xAs QWFET

Fig. 2.3 The common expitaxial structures of the InxGa1-xAs based QWFETs for high speed application.

Fig. 2.4 Electrical figures of merit of a transistor as a switch

Fig. 2.5 Evaluation methodology of QWFETs for logic performance

Devices In

Table 2.1 Best performance of InP HEMTs and GaAs MHEMTs in high speed and low noise aspect published in recent years.

Chapter 3

Fabrications of InAs-Channel Quantum-Well Field-Effect Transistors (QWFETs)

The fabricated QWFETs in this study bring together novel designs to enhance the electronic properties. For instance, the QWFETs with small gate length (Lg) of 40nm can increase the electronic field under the gate so the electron will accelerate; the tunneling cap layer with highly doping can efficiently minimize parasitic resistances [3-1]; the application of two-step recess process can scale-down gate electrode to channel thickness so that the short channel effect is released [3-2]; and the application of Pt gate sinking process can enhance the schottky gate work function. Besides, by the precise time control of Pt gate sinking annealing, the gate electrode can be further close to channel layer so as to speed up electron transport [3-3].

The process flows of QWFETs fabrication in this study are listed below.

1. Active region formation (Mesa isolation) 2. Ohmic contact formation

3. Electron Beam Lithography process for nano T-shaped gate 4. Gate recess process (Two-step recess process) and gate formation 5. Device passivation

6. Airbridge formation

3.1 Mesa Isolation

For III-V devices, the mesa isolation process is used for the definition of active region.

First, the active areas were masked by Shipley S1818 photoresist. Then the phosphoric based

solution was used to etch InGaAs/InAlAs layers and hydrochloric acid based solution was used to etch InP layer. According to the device structure, the mesa was etched to the buffer layer to provide good device isolation.The etching depth was approximately 2500Å measured by α-step. After the strip of photoresist, the etching profile was carefully checked by scanning electron microscopy (SEM).

3.2 Ohmic Contact Formation

The photoresist AZ5214E and I-line aligner were used to define the ohmic metal pattern.

Unlike the Si-based devices, the lift-off process is used for III-V based device because of the lack of appropriate etching selection between ohmic metals and III-V materials. The undercut profile of the photoresist AZ5214E will benefit the metal lift-off process. The HCl-based solution was used to remove the native oxide on the InGaAs surface before Ohmic metallization. Ohmic metal multilayer Au/Ge/Ni/Au, from the bottom to the top, was deposited by e-gun evaporation system and the thickness was 2400Å. After metal lift-off process, the devices were annealed by rapid thermal annealing (RTA) at 270 ^oC for 30 sec in forming gas atmosphere. During annealing, germanium atoms will diffuse into the InGaAs cap layer forming heavily doped status so the contact resistance decreased. The specific contact resistance between metal and cap layer can be extracted by the transmission line method (TLM) [3-4]. In general, the typical measured contact resistance must be less than 1 x 10^-6 Ω-cm².

3.3 Electron Beam Lithography Process for Nano T-shaped Gate

Decreasing gate length (Lg) can increase the electronic field under the gate so as to accelerate the transport property of channel electron. Therefore, it is benefit for devices in

high frequency and high speed applications. T-shaped gate structure was the most common approach for achieving low gate resistance and a small gate foot [3-4]. In this study, the Electron Beam lithography with tri-layer photoresists (ZEP-520/PMGI/ZEP-520) was applied for the T-shaped gate formation. Fig. 3.1 illustrates the process flow of the fabrication of nanometer T-shaped gate. The first E-beam exposure for top two layers was used to define the head (Tee-top) of the T-shaped gate. After that, the ZEP-520 and PMGI development were executed by using xylene and MF622, respectively. Then, high dosed single center exposure with xylene development was used to define the footprint of the bottom ZEP-520 layer. The SEM image of the 40 nm T-shaped gate resist profile is shown in Fig. 3.2-3.4.

3.4 Gate Recess Process (Two-step Recess Process) and Gate Formation

Through anisotropic CF4 RIE dry etching, the gate foot was precisely replicated on 600Å SiN layer which was deposited by plasma-enhanced chemical vapor deposition (PECVD) before the E-Beam photoresistor formation. Besides, these additional 600Å SiN layer can mechanically support the small Lg of T-shaped gate [3-5]. For gate recess etching, in order to suppress the short channel effect and enhance the electron mobility under the gate, a two-step recess process proposed by T.Suemitsu et al. [3-2] was used. By applying two-step recess process, gate electrode was much close to the channel. Fig. 3.5 illustrates the process flow of two-step recess. The first step of recess was cap layer etching performed by using PH-adjusted solution of succinic (S.A.) and H2O2. The target current after the cap layer recess is a critical parameter to affect the QWFET performance. In order to get the desired recess target, the recess process was controlled by monitoring the non-gated drain-to-source current (IDS). The second step of recess etching was removing the InP etching stop layer under the gate opening by inductive coupled plasma (ICP) with argon ambient. The second step of recess etching resulting gate structure has the gate metal deposited on InAlAs barrier layer

whereas the InP etching stop layer covers the recess region as illustrated in Fig. 3.6. After recess etching, Pt/Ti/Pt/Au (120/800/600/1800Å) gate metal was evaporated by e-gun evaporation system and lifted off by using ZDMAC remover (ZEON Corporation). For multilayer gate metal (Pt/Ti/Pt/Au), where titanium is a good adhesion layer; platinum acts as a barrier layer to prevent gold from diffusing into GaAs; and gold provides high electrical conductivity. Unlike the traditional GaAs-based QWFETs, in this study for proceeding Pt gate sinking process, the additional 120Å-thickness platinum was applied to the first gate electrode.

There’re several advantages of Pt gate sinking process for QWFETs. By precisely annealing time control, Pt can react with As and move toward channel. This function makes the gate electrode further close to channel layer, and it is benefit for device characteristics in high frequency as well as in logic aspects [3-3]. Additionally, Pt gate sinking process provides higher schottky gate work function of 0.8eV for PtAs4 on InAlAs than the traditional work function of 0.4eV and 0.6eV for Ti on InAlAs and InP respectively. Besides, slight reduction in the gate leakage current was also observed owing to the increase in the thickness of the amorphous layer under gate which diminished the leakage path because of the reduction of the grain boundaries [3-6, 3-7].

The final formation of 40nm T-shaped gate was pictured by SEM as shown in Fig. 3.7.

3.5 Device Passivation

To prevent the device from the mechanical damages and environmental contaminations such as chemicals, gases, and particles; surface passivation of device is necessary. The dielectric layer SiNx is a common choice for III-V device passivation. Before the passivation, the wafer was dipped in the solution of NH4OH:H2O=1:50 for 30 seconds to clean the surface and decrease the surface dangling bonds. And then PECVD system with process pressure of 900 mtorr, process temperature of 200°C, process time of 10 minutes, and process gases of

silane, ammonia, and nitrogen was used for depositing the silicon nitride film. The silicon nitride film thickness was about 600 Å and the reflection index was 2.0 as inspected by N&K anaylzer. After the passivation process, the contact via was opened by CF4 RIE etching for

silane, ammonia, and nitrogen was used for depositing the silicon nitride film. The silicon nitride film thickness was about 600 Å and the reflection index was 2.0 as inspected by N&K anaylzer. After the passivation process, the contact via was opened by CF4 RIE etching for