NF can be well approximated by the semi-empirical equation given by Fukui [4-4] and is shown as the following equation:
NF = 1+ k (f/fT) [gm (Rg+Rs)]1/2,
= 1+ 2πkf (Cgs + Cgd) [gm (Rg+Rs)]1/2 (4-19) , where k is a fitting parameter.
Generally, the reduction in Lg does not necessarily minimize the NFmin because Rg tends to increase due to a vertical resistance component of gate resistance, and also gm decreases due to a degraded gate drive so-called “short-channel effect”. Therefore, a reduction in Rg and suppression of the short-channel effect are necessary to minimize NFmin.
Fig. 4.1 Band diagrams of QWFET at three different locations along the channel.
Fig. 4.2 Drain current of III-V QWFETs predicted by Eq. (4-4).
Eq. (4.4)
Fig. 4.3 TLM pattern.
Fig. 4.4 The illustration of utilizing TLM to measure ohmic contact resistance.
Fig. 4.5 The equivalent two-port network schematic at low frequency.
Fig. 4.6 The equivalent two-port network schematic at high frequency.
Fig. 4.7 The device layout used in this study.
Fig. 4.8 The block diagram with determined parasitic elements for the overall device structure.
Fig. 4.9 Functional blocks of the equivalent circuit model, divided according to the scalability with device size.
Transmission line to accommodate for possible phase shift caused by probe positioning variation
Fig. 4.10 Analyzed electric field plot of the 2x50um device at 10 GHz. (a) with the source buses of the device (b) without the source buses of the device
(a) (b)
Chapter 5
Experimental results and discussions
5.1 40 nm InAs-Channel Based QWFETs for High-Speed and Low-Voltage RF Applications by using Two-Step Recess and Pt Gate Sinking Processes
5.1.1 Introduction
For commercial and military applications of millimeter wave and sub-millimeter wave systems such as wireless LANs, outer-space radars, mobile communications and hand-held imagers etc., the key component of the systems is the front-end amplifier in the receiver. And the system sensitivity is ultimately determined by the performance of the front-end amplifiers which should possess outstanding high frequency features and low noise characteristics. In addition to the requirements of high gain and low noise, low DC power consumption is also in highly demand. Among all the possible technologies to meet such stringent requirements, high indium content InGaAs-based QWFETs are particularly promising. Because the InGaAs material own significant transport properties like high electron mobility, high saturation velocity, high sheet electron densities, and large Γ to L valley separation even in low electric field. Besides the excellent electrical properties of InGaAs material, the superior band-gap design of QWFETs also leads InxGa1-xAs QWFETs incomparable in high speed and low voltage performances.
For devices operating in high frequency region, current-gain cutoff frequency (fT) is a significant index. fT is defined as the frequency which the current-gain becomes 0 dB. fT can also be expressed by using circuit elements as following：
)
G As shown in the above relations, in order to achieve high fT, it is necessary to enhance gm
and decrease total gate capacitance. In general, small total gate capacitance can be accomplished by shortening the gate length, and decreasing gate length can also increase the electronic field under the gate resulting in the accelerating of the transport property of the channel electrons. Therefore, shrinking the gate length is an effective way to get high gm and low Cg so as to attain high fT.
For the noise performance, minimum noise figure (NFmin) can be well approximated by the semi-empirical equation given by Fukui [5-1] andis shown as the following equation：
NFmin = 1+ k (f/fT) [gm (Rg+Rs)]1/2,
= 1+ 2πkf (Cgs + Cgd) [ (Rg+Rs)/gm]1/2 , where k is a fitting parameter.
It can be seen that the reduction of the parasitic capacitances and parasitic resistances are the keys to achieve low noise figure. And this can be accomplished by the shrinkage of gate length and the usage of low resistance structure layers and process.
Although the reduction of gate length seems to be a good approach both for high frequency and low noise performance, such approach may generate the performance degradation caused by the short channel effect. Thus, care must be taken in obtaining the optimal performance without the short channel effect. Therefore, two-step recess process [5-2]
and Pt gate sinking process were developed to solve this problem. Two-step recess process and Pt gate sinking technology have been widely used in the fabrication of QWFETs since they provide the promising solutions that enable vertical scaling shrinkage of gate-channel distance without increasing the access resistance. Meanwhile, the short-channel effect can be effectively minimized. By precise time control of the annealing time for Pt gate sinking process, Pt will diffuse toward channel. This reaction makes the gate electrode further close to channel layer, and it is beneficial for high frequency devices as well as for logic applications.
Another advantage of using Pt-based structure is the relatively large schottky barrier height which will suppress gate leakage current.
In this work, the electron beam lithography system was used to fabricate nanometer (40 nm) gate length for InAs QWFETs. Besides, two-step recess and Pt gate sinking processes were applied simultaneously to effectively reduce the gate-channel distance. The measured DC, RF and noise results will be presented here.
5.1.2 Experiment
The QWFET structure in this study was grown by molecular beam epitaxy (MBE) on a 2-in diameter InP substrate, and the schematic structure is shown in Fig. 5.1.1. The structure layers from bottom to top consist of a 500 nm In0.52Al0.48As metamorphic buffer layer, a 5 nm InAs channel layer combining with a 3 nm In0.53Ga0.47As lower sub-channel layer and 2 nm In0.53Ga0.47As upper sub-channel layer, then, a 8 nm In0.52Al0.48As Schottky barrier layer with Si planar doping (4x1012cm-2), a 5 nm InP etching stop layer and a 40 nm highly Si-doped In0.53Ga0.47As cap layer (1×1019cm-3). The In0.53Ga0.47As sub-channels here were applied to enhance the electron confinement in the thin InAs layer and improve the electron transport properties [5-3].
For the device fabrication, the active area of the device was isolated by wet etching.
Au-Ge-Ni-Au was deposited on heavily doped n-InGaAs cap layer and then alloyed in rapid thermal annealing (RTA) at 250℃ for 30 second to form source and drain ohmic contacts with low contact resistance and sheet resistance. Before the formation of T-shaped gate photoresist, the 600Å silicon nitride was deposited by plasma enhanced chemical vapor deposition (PECVD) as the support of the following 40nm gate foot. The T-shaped gate photoresist was carried out by using 50-kV JEOL electron beam lithography system (JBX 6000FS). The tri-layer EB photoresist system (ZEP/PMGI/ZEP) with double exposure and
development was used to define the 40nm gate length. The top layer of T-shaped gate was exposed with low dosage, and the fine footprint was written with high dosage. Through anisotropic CF4 RIE dry etching, the gate foot was precisely replicated on 600Å SiNx layer.
Then, the two-step recess technique was performed. The first step of recess was cap layer etching performed by using PH-adjusted solution of succinic (S.A.), NH4OH and H2O2. And the second step of recess etching was operated by inductive coupled plasma (ICP) with argon ambient to remove the InP etching stop layer under the gate. Schottky gate metal, which was composed of Pt(12nm) /Ti(80nm) /Pt(60nm) /Au(180nm), was then deposited by electron beam evaporation. Gate metal will form after lift-off procedure by acetone and ZDMAC. An adequate time of Pt sinking annealing at 250℃ was controlled to obtain the optimal performance for these devices. Finally, 100-nm-thick silicon nitride layer was deposited by PECVD at 200℃ for 10 min for devices passivation.
SEM image of the 40-nm T-shaped gate is shown in Figure 5.1.2. As can be seen from SEM image, the fabricated 40-nm T-gate shows structural stability, even though the gate foot is narrow.
5.1.3 Result and discussion
Fig. 5.1.3 and Fig. 5.1.4 show the DC I-V curves of the 40 nm InAs QWFETs with and without two-step recess and Pt gate sinking processes. Due to the high carrier concentration of the InAs/In0.53Ga0.47As composite channel material and the ultra low ohmic contact resistance of 0.02 Ω‧mm measured by TLM method, the 40nm InAs QWFETs exhibit high drain current density. Although the drain current 1050 mA/mm (VDS = 0.5 V, VGS = 0 V) of devices without two-step recess and gate sinking processes is higher than the device with these techniques of 390 mA/mm, the devices with these techniques exhibit much better pinch-off and current saturation characteristics compared to the devices without using these techniques.
The threshold voltage (VT) defined as the gate voltage at IDS of 1mA/mm shifts to more positive side from -1.0V to -0.4V for device with two-step recess and gate sinking processes.
Besides, due to the effective suppression of short channel effect by additional vertical shrinkage, the device with two-step recess and gate sinking processes shows better saturating current and lower output conductance characteristics.
The transconductance (gm) and the drain-source current plotted as functions of gate-source voltage are shown in Fig. 5.1.5 and Fig. 5.1.6. The 40 nm InAs QWFETs exhibit very high transconductance which result from the high electron mobility of the InAs channel material. As observed from the figures, the threshold voltage and peak gm of the devices with two-step recess and Pt gate sinking processes move toward more positive side, which are beneficial for devices of low power consumption applications. However, the trade-off of the reduction in gate-channel distance is the slightly lower gm,max. Gm,max for devices with and without two-step recess and gate sinking processes are 1650 mS/mm and 1750 mS/mm at VDS
= 0.5, respectively. The decrease in gm,max for devices with these two processes comes from the overall drops of drain-current density. And this phenomenon arises mainly from an increase in the source resistance as gate-channel thickness is scaled down, although other factors also appeared to be involved.
The S-parameters of the 40 nm InAs QWFETs were measured to 80 GHz using Cascade MicrotechTM on-wafer probing system with Anritsu 37369C vector network analyzer. Fig.
5.1.7 and Fig. 5.1.8 show the frequency dependence of the current gain (H21) and the power gain (MAG/MSG) of the devices with/without two-step recess and gate sinking processes measured at VDS = 0.5. The parasitic effects (mainly capacitive) due to the probing pads have been carefully removed from the measured S-parameters using the same method as in [5-4]
and the equivalent circuit model in [5-5]. Since the geometry of the probing pads are relatively large compared to the device itself, the S-parameters of the open probing pads have been carefully characterized through full-wave electromagnetic simulations with
measurement. The value of current gain cut-off frequency (fT) and maximum oscillation frequency (fmax) are extracted by extrapolating current gain (H21) and the power gain (MAG/MSG) with a -20dB/decade slope. A higher fT of 440 GHz and fmax of 190 GHz are obtained for device with two-step recess and gate sinking processes as compared to the device without these processes which shows fT of 395 GHz and fmax of 160 GHz. These improved RF performance mainly result from reduced gate-channel distance by the two-step recess and gate sinking processes. The reduction of gate-channel distance tends to suppress the short-channel effect and enhances the overshooting of electron velocity in channel. Table 5.1 summarizes the extracted intrinsic parameters for devices with/without two-step recess and gate sinking processes at same bias conditions. The increase of fT can also be attributed to the decrease of total gate capacitance (Cg,total) and increase of the RF transconductance.
From the above results, the excellent DC and RF characteristics of 40 nm InAs/In0.53Ga0.47As QWFETs can be achieved even at low applied voltage. Besides, by additional process improvements like two-step recess and gate sinking processes, the devices can exhibit much better performances. However, for millimeter wave and sub- millimeter wave applications, device with low noise generation is also a basic criterion. Therefore, the noise performance is required in this study. The noise performances for 40 nm InAs/In0.53Ga0.47As QWFETs with two-step recess and gate sinking processes at VDS = 0.5 V were measured and shown in Fig. 5.1.9. As seen from the figure, the overall minimum noise figure (NFmin) is below 2.5dB with frequency range from 1 GHz to 64 GHz, and the corresponding associated gain (Ga) is 7dB at 64GHz. The ultra-low dc power dissipation of 4.33mW was applied here.
Finally, the cutoff frequency (fT) versus DC power consumption of the 40nm InAs/In0.53Ga0.47As QWFETs with two-step recess and gate sinking processes are shown in Fig. 5.1.10. Meanwhile, the published data of 80 nm Si nMOSFETs [5-6] biased at 0.7 V are also included in this figure for comparison. We can conclude from the plot that InAs
channel-based QWFETs can achieve higher fT under the same level of DC power consumption than Si nMOSFETs, this is because the InAs channel can provide better electron transport properties.
Overall, these superior results show great potential of 40 nm InAs/In0.53Ga0.47As QWFETs for ultra low-power, high-frequency and low-noise RF applications.
5.1.4 Conclusion
In this study, the 40nm InAs/In0.53Ga0.47As QWFETs using two-step recess and Pt gate sinking technologies to enhance DC & RF performances is demonstrated. By applying these two advanced processes, the gate electrode becomes much closer to the channel layer, thus avoids short channel effect and the electrons in the channel are further accelerated. By applying these processes, the devices exhibit improved behaviors at low VDS such as better current saturation, lower output conductance (go), enhanced current driving capability, smaller negative threshold-voltage (VT) and higher fT and fmax (400 GHz and190 GHz).
The evaluations of InAs QWFETs with two-step recess and Pt gate sinking processes for high-gain and low-noise applications have also been investigated. The devices exhibit the minimum noise figure of lower than 2.5 dB up to 64GHz and with corresponding associated gain of 7 dB when biased at VDS of 0.5 V.
Overall, these experimental results demonstrate that superior device performance for high-speed, low-noise and low-power millimeter/sub-millimeter wave applications can be achieved by using 40 nm InAs QWFET with two-step recess and Pt gate sinking technologies.
Fig. 5.1.1 Epitaxial structure of InAs/In0.53Ga0.47As QWFETs in this study
Fig. 5.1.2 SEM images of the 40 nm T-shaped gate photoresist and the finished 40 nm gate after the two-step recess process.
0.0 0.1 0.2 0.3 0.4 0.5
Drain-source voltage, V
DS(V)
VGS= 0 V
Fig. 5.1.3 Drain-source current versus drain-source voltage curves of 40nm InAs QWFET without two-step recess and gate sinking processes.
0.0 0.1 0.2 0.3 0.4 0.5
40 nm InAs/In0.53Ga0.47As QWFETs VGS = 0 V
Drain-source voltage, V
DS(V) Dr ain-sour ce curr ent, I
DS(mA/mm)
Fig. 5.1.4 Drain-source current versus drain-source voltage curves of 40nm InAs QWFET with two-step recess and gate sinking processes.
-1.0 -0.8 -0.6 -0.4 -0.2 0.0
40 nm InAs/In0.53Ga0.47As QWFETs Gm,max = 1750 mS/mm @ VDS 0.5 V
Drain-source current, I DS (mA/mm)
Gate-source voltage, VGS (V)
Transconductance (mS/mm)
Fig. 5.1.5 Transconductance versus gate-source voltage of 40nm InAs QWFET without two-step recess and gate sinking processes.
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 40 nm InAs/In0.53Ga0.47As QWFETs 1600
Gm,max = 1650 mS/mm @ VDS 0.5 V Transconductance (mS/mm)
Gate-source voltage, VGS (V) Drain-source current, I DS (mA/mm)
Fig. 5.1.6 Transconductance versus gate-source voltage of 40nm InAs QWFET with two-step recess and gate sinking processes.
1 10 100 1000 0
5 10 15 20 25 30 35 40 45
fmax = 160 GHz
fT = 395 GHz 40 nm InAs/In0.53Ga0.47As QWFETs VDS = 0.5 V VGS = -0.65 V
Gain (dB)
Frequency (GHz)
H21
MAG/MSG
Fig. 5.1.7 Frequency dependence of the current gain (H21) and the power gain (MAG/MSG) of 40nm InAs/In0.53Ga0.47As composite channel QWFETs without two-step recess and gate sinking processes. The frequency range was from 4 to 40 GHz, and the device was biased at VDS = 0.5V and VGS = -0.65V.
1 10 100 1000 0
5 10 15 20 25 30 35 40 45 50
40 nm InAs/In0.53Ga0.47As QWFETs VDS = 0.5 V VGS = -0.2 V
fmax = 190 GHz
fT = 440 GHz
Gain (dB)
Frequency (GHz)
H21
MAG/MSG
Fig. 5.1.8 Frequency dependence of the current gain (H21) and the power gain (MAG/MSG) of 40nm InAs/In0.53Ga0.47As composite channel QWFETs with two-step recess and gate sinking processes. The frequency range was measured to 40 GHz, and the device was biased at VDS = 0.5V and VGS = -0.2V.
20 30 40 50 60 70 40 nm InAs/In0.53GaAs HEMT 20
VDS = 0.5 V VGS = 0 V PDC = 4.33mW
N F A ssociated G ain (dB)
Fig. 5.1.9 Measured minimum noise figure (NFmin) and the associated gain of the 40nm InAs QWFETs with two-step recess and gate sinking processes at VDS = 0.5V and the applying DC power was 4.33mW.
10 100 0
100 200 300 400
Si NMOS
Lg = 80 nm, VCC = 0.7 V Cutoff Frequency, f T (GHz)
Power Dissipation (mW/mm)
Lg = 40 nm InAs/In0.53Ga0.47As QWFETs VDS = 0.5 V
Fig. 5.1.10 Cutoff frequency of 40nm InAs QWFETs and 80 nm Si nMOSFETs as a function of the power dissipation
Gm.RF
(mS)
Cgs
(fF)
Cgd
(fF)
Cg,total
(fF)
H21
@40GHz (dB)
fT
(GHz)
fmax
(GHz)
Without 190 29 48.4 77.4 19.9 395 160
With 196 37.7 33.3 71 20.83 440 190
Table 5.1 Summary of extracted RF parameters for 40 nm InAs/In0.53Ga0.47As QWFETs at VDS of 0.5 V with/without two-step recess and Pt gate sinking processes.
5.2 Comprehensive Study of Impact Ionization Phenomena in 40 nm InAs-Channel Based QWFETs
5.2.1 Introduction
For the low-noise amplifier (LNA) monolithic microwave integrated circuit (MMICs) used in the next generation wireless communication systems [5-7], the devices with high speed, low-noise performances and low-power consumption are required. Among all electronic devices, InP-based InAlAs/InGaAs QWFETs with high indium content in transistor-channel are the most promising candidates for operating under millimeter-wave (30-300 GHz) and sub-millimeter wave (300 GHz- 3 THz) frequency bands, because of their extremely high channel electron mobility and high saturation velocity [5-8, 5-9]. Moreover, further reducing the gate length (Lg) and raising indium content in the InxGa1-xAs channel layer can improve the electron transport performance, because the average electron field under the gate is increased and the higher electron mobility characteristics of high indium content channel. K. Shinohara et al. reported a 562 GHz cutoff frequency (fT) for 25-nm-gate HEMT with a channel In content of 0.7 [5-10], and S.J Yeon et al. reported a 610 GHz 15-nm-gate HEMT with a channel In content of 0.75 [5-11].
However, because of the narrow energy band-gap of high indium content channel material, the electrons acquiring large energy under high electron field might strike other atoms and break the lattice bonding so as to generate extra electron-hole pairs. The excess electron-hole pairs will also obtain sufficient energy so continuously impact and generate more and more electron-hole pairs. This phenomenon is called impact ionization. The number of the electron-hole pairs generated by impact ionization is proportional to the product of carrier concentration in the channel and the electron field dependent ionization coefficient [5-12]. Impact ionization phenomena will degrade the performance of the devices. It will
make III-V QWFETs suffer from severe I-V kink effect, high output conductance, high gate leakage current, low breakdown voltage, and the excess channel noise [5-13, 5-14].
In this study, the 40 nm QWFETs were fabricated using two-step recess method and Pt-buried gate technique. The impact ionization phenomena of InAs/In0.53Ga0.47As QWFETs are investigated. The device characteristics such as DC characteristics, noise figure (NF) and the RF performances are used to verify the impact ionization phenomena in this study. In addition, the optimum bias of InAs/In0.53Ga0.47As QWFETs to prevent the impact ionization is also discussed.
5.2.2 Experiments
The epitaxial structure of QWFET in this study (Fig. 5.2.1) was grown by MBE on 2”
semi-insulating InP substrate and the structure layers from bottom to top are composed of a 500-nm-thick In0.52Al0.48As metamorphic buffer layer, a 3-nm-thick In0.53Ga0.47As lower
semi-insulating InP substrate and the structure layers from bottom to top are composed of a 500-nm-thick In0.52Al0.48As metamorphic buffer layer, a 3-nm-thick In0.53Ga0.47As lower