Evaluations of III-V QWFETs for Beyond-CMOS Logic Applications

For the post-Si era of logic CMOS, III-V compound semiconductors have emerged as promising channel materials, which is not only for their potential in high-speed and low-power performance, but the III-V device technology is relatively mature and reasonably

reliable [2-12] compared to other novel devices such as carbon-nanotube transistors and semiconductor nanowires. Recently, nano gate length InxGa1-xAs QWFETs with outstanding logic performance at low supply voltage have been demonstrated [2-13]. Therefore, using III-V materials as channel for future logic CMOS applications have been noticeable.

In digital application, a transistor operates as a switch, which is different from analog for microwave or millimeter wave application. As seen from the Fig. 2.4, there’re some electrical figures of merit of a transistor as a switch in digital application [2-13], like drain-induced barrier lowering (DIBL), subthreshold slope (S), on-state and off-state current ratio (ION/IOFF), and the gate delay time (CV/I). But for non-optimized devices, arbitrary selections of threshold voltage (VT), ION and IOFF can easily result in an over-estimation of the logic parameters. In this study, the methodology proposed by Chau [2-12, 2-14] to analyze new devices which often feature non-optimized values of VT were adopted. The evaluation methodology is shown in Fig. 2.5. First, select gate-source voltage at drain-source current of 1 mA/mm as the VT. Then select ION as 2/3 VCC swing above VT, and IOFF as 1/3 VCC swing below VT. Based on this definition, the logic parameters, such as subthreshold slope, DIBL and ION/IOFF ratio of InxGa1-xAs QWFETs can be extracted.

The steepness of the device transition between the ON and OFF states is evaluated through the subthreshold slope and ION/IOFF ratio. And the tightness of the threshold voltage is evaluated by drain-induced barrier lowering (DIBL), for which measures the change in VT as a result of a change in VDS. If DIBL is small, VT is insensitive to circuit design details and manufacturing variations. Subthreshold slope and DIBL often go hand in hand and they reflect the overall electrostatic integrity of the device. Besides, device capacitance impacts the switching speed. An important figure of merit in this regard is the transistor delay (CV/I), which is a measure of the time that it takes for a transistor to switch an identical one.

Fig. 2.1 Conventional QWFET structure

Fig. 2.2 Band Diagram of InxAl1-xAs/InxGa1-xAs QWFET

Fig. 2.3 The common expitaxial structures of the InxGa1-xAs based QWFETs for high speed application.

Fig. 2.4 Electrical figures of merit of a transistor as a switch

Fig. 2.5 Evaluation methodology of QWFETs for logic performance

Devices In

Table 2.1 Best performance of InP HEMTs and GaAs MHEMTs in high speed and low noise aspect published in recent years.

Chapter 3

Fabrications of InAs-Channel Quantum-Well Field-Effect Transistors (QWFETs)

The fabricated QWFETs in this study bring together novel designs to enhance the electronic properties. For instance, the QWFETs with small gate length (Lg) of 40nm can increase the electronic field under the gate so the electron will accelerate; the tunneling cap layer with highly doping can efficiently minimize parasitic resistances [3-1]; the application of two-step recess process can scale-down gate electrode to channel thickness so that the short channel effect is released [3-2]; and the application of Pt gate sinking process can enhance the schottky gate work function. Besides, by the precise time control of Pt gate sinking annealing, the gate electrode can be further close to channel layer so as to speed up electron transport [3-3].

The process flows of QWFETs fabrication in this study are listed below.

1. Active region formation (Mesa isolation) 2. Ohmic contact formation

3. Electron Beam Lithography process for nano T-shaped gate 4. Gate recess process (Two-step recess process) and gate formation 5. Device passivation

6. Airbridge formation

3.1 Mesa Isolation

For III-V devices, the mesa isolation process is used for the definition of active region.

First, the active areas were masked by Shipley S1818 photoresist. Then the phosphoric based

solution was used to etch InGaAs/InAlAs layers and hydrochloric acid based solution was used to etch InP layer. According to the device structure, the mesa was etched to the buffer layer to provide good device isolation.The etching depth was approximately 2500Å measured by α-step. After the strip of photoresist, the etching profile was carefully checked by scanning electron microscopy (SEM).

3.2 Ohmic Contact Formation

The photoresist AZ5214E and I-line aligner were used to define the ohmic metal pattern.

Unlike the Si-based devices, the lift-off process is used for III-V based device because of the lack of appropriate etching selection between ohmic metals and III-V materials. The undercut profile of the photoresist AZ5214E will benefit the metal lift-off process. The HCl-based solution was used to remove the native oxide on the InGaAs surface before Ohmic metallization. Ohmic metal multilayer Au/Ge/Ni/Au, from the bottom to the top, was deposited by e-gun evaporation system and the thickness was 2400Å. After metal lift-off process, the devices were annealed by rapid thermal annealing (RTA) at 270 ^oC for 30 sec in forming gas atmosphere. During annealing, germanium atoms will diffuse into the InGaAs cap layer forming heavily doped status so the contact resistance decreased. The specific contact resistance between metal and cap layer can be extracted by the transmission line method (TLM) [3-4]. In general, the typical measured contact resistance must be less than 1 x 10^-6 Ω-cm².

3.3 Electron Beam Lithography Process for Nano T-shaped Gate

Decreasing gate length (Lg) can increase the electronic field under the gate so as to accelerate the transport property of channel electron. Therefore, it is benefit for devices in

high frequency and high speed applications. T-shaped gate structure was the most common approach for achieving low gate resistance and a small gate foot [3-4]. In this study, the Electron Beam lithography with tri-layer photoresists (ZEP-520/PMGI/ZEP-520) was applied for the T-shaped gate formation. Fig. 3.1 illustrates the process flow of the fabrication of nanometer T-shaped gate. The first E-beam exposure for top two layers was used to define the head (Tee-top) of the T-shaped gate. After that, the ZEP-520 and PMGI development were executed by using xylene and MF622, respectively. Then, high dosed single center exposure with xylene development was used to define the footprint of the bottom ZEP-520 layer. The SEM image of the 40 nm T-shaped gate resist profile is shown in Fig. 3.2-3.4.

3.4 Gate Recess Process (Two-step Recess Process) and Gate Formation

Through anisotropic CF4 RIE dry etching, the gate foot was precisely replicated on 600Å SiN layer which was deposited by plasma-enhanced chemical vapor deposition (PECVD) before the E-Beam photoresistor formation. Besides, these additional 600Å SiN layer can mechanically support the small Lg of T-shaped gate [3-5]. For gate recess etching, in order to suppress the short channel effect and enhance the electron mobility under the gate, a two-step recess process proposed by T.Suemitsu et al. [3-2] was used. By applying two-step recess process, gate electrode was much close to the channel. Fig. 3.5 illustrates the process flow of two-step recess. The first step of recess was cap layer etching performed by using PH-adjusted solution of succinic (S.A.) and H2O2. The target current after the cap layer recess is a critical parameter to affect the QWFET performance. In order to get the desired recess target, the recess process was controlled by monitoring the non-gated drain-to-source current (IDS). The second step of recess etching was removing the InP etching stop layer under the gate opening by inductive coupled plasma (ICP) with argon ambient. The second step of recess etching resulting gate structure has the gate metal deposited on InAlAs barrier layer

whereas the InP etching stop layer covers the recess region as illustrated in Fig. 3.6. After recess etching, Pt/Ti/Pt/Au (120/800/600/1800Å) gate metal was evaporated by e-gun evaporation system and lifted off by using ZDMAC remover (ZEON Corporation). For multilayer gate metal (Pt/Ti/Pt/Au), where titanium is a good adhesion layer; platinum acts as a barrier layer to prevent gold from diffusing into GaAs; and gold provides high electrical conductivity. Unlike the traditional GaAs-based QWFETs, in this study for proceeding Pt gate sinking process, the additional 120Å-thickness platinum was applied to the first gate electrode.

There’re several advantages of Pt gate sinking process for QWFETs. By precisely annealing time control, Pt can react with As and move toward channel. This function makes the gate electrode further close to channel layer, and it is benefit for device characteristics in high frequency as well as in logic aspects [3-3]. Additionally, Pt gate sinking process provides higher schottky gate work function of 0.8eV for PtAs4 on InAlAs than the traditional work function of 0.4eV and 0.6eV for Ti on InAlAs and InP respectively. Besides, slight reduction in the gate leakage current was also observed owing to the increase in the thickness of the amorphous layer under gate which diminished the leakage path because of the reduction of the grain boundaries [3-6, 3-7].

The final formation of 40nm T-shaped gate was pictured by SEM as shown in Fig. 3.7.

3.5 Device Passivation

To prevent the device from the mechanical damages and environmental contaminations such as chemicals, gases, and particles; surface passivation of device is necessary. The dielectric layer SiNx is a common choice for III-V device passivation. Before the passivation, the wafer was dipped in the solution of NH4OH:H2O=1:50 for 30 seconds to clean the surface and decrease the surface dangling bonds. And then PECVD system with process pressure of 900 mtorr, process temperature of 200°C, process time of 10 minutes, and process gases of

silane, ammonia, and nitrogen was used for depositing the silicon nitride film. The silicon nitride film thickness was about 600 Å and the reflection index was 2.0 as inspected by N&K anaylzer. After the passivation process, the contact via was opened by CF4 RIE etching for interconnections.

3.6 Airbridge Formation

Airbridge process is used to interconnect the sources of FETs, to cross over a lower level of metallization, or to connect the top plate of a MIM capacitor for adjacent metallization.

And because of the lowest dielectric constant, low parasitic capacitance of air, and the high electronic conductance of gold; airbridge process is used extensively in III-V analog devices and MMICs for interconnections.

For airbridge procedure, firstly the photoresistor was coated on the metal pad, and followed by a whole wafer deposited with thin Ti/Au/Ti. Then, a second photoresistor was patterned, and the gold of 2μm was electroplated. After that, the top photoresist layer, thin Ti/Au/Ti metal, and bottom resist layer were removed individually, leaving only the plated air-bridge. The SEM image of the airbridge is shown in Fig. 3.8.

Fig. 3.1 E-Beam Lithography process flow for nano T-shaped gate

Fig. 3.2 The side view of tri-layer photoresist profile for 40 nm T-shaped gate

Fig. 3.3 The top view of tri-layer photoresist profile for 40 nm T-shaped gate

Fig. 3.4 The bottom photoresist profile of 40 nm T-shaped gate foot

Fig. 3.5 Illustration of two-step recess process flow Second recess ：

Ar ICP dry etching for InP stopper CF4 RIE dry etching for SiNx

Deposition of SiNx as hard mask

&

Tri-layer EB T-gate PR formation

First recess ：

SA wet etching for InGaAs cap layer (control the side recess spacing)

Fig. 3.6 Cross-sectional view of gate formation after two-step recess

Fig. 3.7 SEM images of 40 nm T-shaped gate

Fig. 3.8 SEM image of the airbridge

Chapter 4

Fundamentals of Electrical Characteristics for In_xGa_1-xAs QWFETs

After the device fabrication, DC and RF performance of the QWFETs were measured by using on-wafer measurement. For the DC measurement, the I-V characteristics were obtained by using an HP4142B Modular DC Source/Monitor and SUSS PA200 Semi-Auto Probe Station. The Transmission Line Model (TLM) method for determining specific contact resistance was adopted by using 4-wires measurement. The S-parameters were measured by HP8510XF Vector Network Analyzer using on-wafer GSG probes from Cascade MicroTech.

However, finding the RF behavior of a device on a wafer was a complicated process. For conventional RF measurement of a packaged device, the wafer needs to be diced and then an individual die should be mounted into a text fixture. Discriminating between the die’s and the fixture’s responses became an issue. Furthermore, fixturing die was a time-consuming process, and making it impractical for high-volume screening. Thus the need for on-wafer RF characterization was arisen [4-1]. In this study, de-embedding which must also be performed to discover the true RF performance of the device is discussed.

4.1 DC Characteristics [4-2]

The band diagrams at three different locations along the channel are illustrated in Fig.

4.1. There is a potential drop of channel charge density in the direction parallel to the channel, causing q’CH to be a function of the position x. In order to relate the QWFET equations to the well-developed MOSFET equations, a per area gate oxide capacitance was define as C^’OX. Therefore, the channel charge sheet density is expressed as：

)]

Here the channel-to-source potential is resulting from the applied Gate-Source voltage (VGS) and Drain-Source voltage (VDS). VT is threshold voltage and the x means the position along the channel. The additional potential VCS(x) is called the channel-source potential. When VDS ≠ 0, the channel-source potential varies with x and the potential difference is the potential between any point x along the channel with respect to the source.

The channel current equation I= qAμnε (A=area) is proportional to the cross-section area of the current conduction, the charge density, the mobility μn, and the electric field. Therefore, the form of the channel current equation in QWFET is obtained：



We note that q’CH is a negative quantity in QWFET, since electrons accumulated in the channel are negative charges. Besides, if we choose x = L at the drain, this constant channel current is equal to the negative of the drain current. Hence, we have ID =- ICH, and we find：

To carry out the integration in Eq. (4-3), we deal with the linear operating region first so that current saturation due to channel pinch off at the drain does not occur. In the linear region, the boundary conditions are VCS(L) = VDS and VCS(0) = 0. Hence, Eq. (4-3) leads to: value of VDS corresponding to the saturation drain current (ID,sat) is denoted as VDS,sat, the saturation voltage. The saturation voltage can be obtained by taking the derivative of ID with respect to VDS and setting the result to zero. And we find that:

T GS SAT

DS V V

V _,   (4-5)

At saturation voltage, q’CH calculated from Eq. (4-1) is identically zero at the drain (pinch off). However, we realize that this conclusion originates from the fact that we are extending the validity of Eq. (4-1) all the way to where q’CH(L). But physically the channel at the drain does not pinch off completely. Instead, there is a finite thickness of accumulation of charges at which q’CH x=L so it’s nonzero. The drift velocity is high, but nonetheless finite, so a constant current is maintained throughout the channel. Therefore, a complete model of the drain current is given by:

2 ]

And another important parameter for QWFET is transconductance (gm), which represents the amount of drain current increase with the increment of gate bias at constant drain voltage.

For QWFET, it is convenient to define the saturation index (α) as:

SAT

4.2 Transmission Line Model (TLM)

The specific contact resistance between contact metal and cap layer can be extracted by

the transmission line model (TLM) method [4-3]. The TLM pattern, as illustrated in Fig. 4.3, was designed in the process control monitor (PCM). In this particular approach, a linear array of contacts pad is fabricated with various spacing between them. The distances between TLM electrodes are 3 μm, 5 μm, 10 μm, 20 μm, and 36 μm, respectively. The resistance between the two adjacent electrodes can be plotted as a function of the space between electrodes and is expressed by the following equation

W L R R

R 2 _C  _S (4-11)

,where R is measured resistance, RC is contact resistance, RS is sheet resistance of channel region, W is electrode width, and L is the space between electrodes. As Fig. 4.4 shows, extrapolating the data to L=0, one can calculate a value for the term RC. And the specific contact resistance ρC can be further extracted by the following formula.

S

C R

R W^{2 2}

  (4-12)

In general, the typical measured contact resistance for InGaAs QWFET was < 1 x 10^-6 Ω-cm².

4.3 Scattering Parameters [4-2]

Field-effect transistor with the input and output terminals can be treated as a two-port network as shown in Fig. 4.5. Many characteristics such as gain, return loss and impedance matching can be calculated from relationship among the input and output signals. The impedance parameters (z-parameters), conductance parameters (y-parameters) and hybrid parameters (h-parameters) are used to characterize the devices. While the frequency is up to several GHz, the z-, y-, h- parameters can not be directly obtained by open or short circuits because of the reflected wave from the open or short terminations, which will induce the network oscillations. Therefore, the scattering parameters (S-parameters) are used to

characterize the performance of a device at high frequency. Fig. 4.6 shows the equivalent two-port network schematic at high frequency. Generally, the Scattering parameters, which referred to as s-parameters, are fundamental to microwave measurement. S-parameters are a way of specifying return loss and insertion loss. The relation of the microwave signals and s-parameters are defined as follows:

s-parameters: _

Microwave signals going into or coming out of the input port are labeled by a subscript 1.

Signals going into or coming out of the output port are labeled by a subscript 2. The electric field of the microwave signal going into the component port is designated a; that leaving the port is designated b. Therefore,

a1 is the electric field of the microwave signal entering the component input.

b1 is the electric field of the microwave signal leaving the component input.

a2 is the electric field of the microwave signal entering the component output.

b2 is the electric field of the microwave signal leaving the component output.

By definition, then,

Consequently, s11 is the electric field leaving the input divided by the electric field entering the input, under the condition that no signal enters the output. Because b1 and a1 are

electric fields, their ratio s11 is a reflection coefficient. Similarly, s21 is the electric field leaving the output divided by the electric field entering the input, when no signal enters the output. Therefore, s21 is a transmission coefficient and is related to the insertion loss or the gain of the device.s22 is similar to s11, but looks in the other direction into the device.

4.4 Current-Gain Cutoff Frequency (fT) and Maximum Oscillation Frequency (fmax)

Current-gain cutoff frequency (fT) is defined as the frequency at which the short-circuit current-gain becomes unity. The intrinsic s-parameters are extracted to determine the value of fT and which is determined by extrapolation of the short-circuit current gain h21 = 0 dB. Here h21 can be defined as fT can also be expressed by using circuit elements：

) The (Cgs + Cgd) is the total capacitance related to the schottky gate. From this relation,

we could see that in order to achieve high fT, enhancing gm and decreasing total gate capacitance must be achieved. Because small total gate capacitance is accomplished by short gate length, and decreasing gate length can increase the electronic field under the gate and then accelerate the channel electron transport property. Therefore, the shrinking of gate length

we could see that in order to achieve high fT, enhancing gm and decreasing total gate capacitance must be achieved. Because small total gate capacitance is accomplished by short gate length, and decreasing gate length can increase the electronic field under the gate and then accelerate the channel electron transport property. Therefore, the shrinking of gate length