Recently, CMOS devices have been aggressively scaled into sub-65 nm regime in order to enhance the device’s performance and increase the integrated circuit functionally. The accelerated downsizing rule of the transistor feature size is to scale the vertical horizontal dimensions simultaneously. With this scaling down, the gate oxide thickness of MOSFETs must be reduced. However, the continuous shrinking of gate dielectrics will face several limitations. According to the ITRS roadmap [1.1], the SiO2 gate dielectric film thickness should be scaled down to 1.0 nm for 45 nm node technology. Such an ultra-thin SiO2 thin film consists of only a few atomic layers will cause an unendurable large direct tunneling leakage current. This large direct tunneling current which depends on physical film thickness will cause an intolerable level of off-current, resulting in huge power dissipation and heat.
Figure 1.1 demonstrated the measured and simulated Ig-Vg characteristics under inversion region for nMOSFET [1.2]. We can see that the gate leakage current will exceed the limit of 1 A/cm2 set by the allowable stand-by power dissipation while the gate oxide thickness scaled down to 2 nm. Further scaling of oxide thickness to below 2 nm, which will cause intolerable power consumption resulted form the increase of large direct tunneling current [1.2]. In addition, the reliability issues will also become an important role for such a thin SiO2 gate dielectric. As a result, a variety of popular high-k materials such as HfO2, ZrO2, Al2O3, Gd2O3, La2O3, and HfSiON (Hf-silicate) have been studied as alternative gate dielectrics for 45 nm node and beyond technology to replace the conventional SiO2 or oxynitrides [1.3-1.5]. The electrical equivalent oxide thickness (EOT) of MOSFET will maintain the same gate
capacitance with a thicker physical thickness by using the high-k gate dielectrics.
Figure 1.2 illustrates basic properties of current high-k candidates.
The alternative high-k material should be thermodynamically stable on Si upon high temperature annealing (needed for dopant activation for poly-silicon gates).
Unstable dielectrics materials will form interfacial layers, which are between the high-k thin film and silicon substrate. The high-k film and its interfacial layer would affect various device parameters such as EOT, flat band voltage (Vfb), barrier height, gate leakage current, and channel mobility, and thus significantly affect the transistor behavior. Some of the metal oxides like Ta2O5, TiO2, and BST are known to degrade when annealed at temperature as low as 600 oC and have poor electrical properties for MOS devices [1.6-1.9]. The newer high-k materials including HfO2, ZrO2, Al2O3, Y2O3, and lanthanide oxides as well as their silicate and alumunate alloys have generated a lot of interest primarily due to their potential thermal stability in the presence of Si based on thermodynamic considerations.
To improve the dielectric performance of high-k gate dielectrics, some methods such as deuterium (D2) and forming gas (FG) annealing [1.10-1.11], surface nitridation pre-treatment [1.12], and formation of the aluminate, silicate and oxynitride [1.13-1.15] alloys, have been investigated recently. It is reported that high-temperature (500 oC~600 oC) post-metal-annealing (PMA) in forming gas prior to metallization improved the channel carrier mobility as well as subthreshold slope of HfO2 MOSFET [1.11]. Unlike the forming gas annealing, the deuterium annealing provided the hafnium oxide gate dielectrics MOSFET with better reliability characteristics such as threshold voltage (VT) stability under high voltage stress [1.10].
Besides, surface nitridation technique was found effective in preventing boron penetration with a possible drawback of mobility reduction and negative bias temperature instability (NBTI) degradation [1.12]. To further raise the dielectrics
properties, cosputtering of silicon aluminum with hafnium to deposit hafnium silicate and aluminate dielectrics [1.13], and the use of nitric gas for chemical vapor deposition (CVD) [1.14] or oxidizing sputtered metal nitride like HfN to form hafnium oxynitride (HfON) films [1.16], are commonly used.
1.2 Motivation
As the gate oxide thickness scaled continuously, and replacement of the SiO2 or oxynitride gate film by high-k materials are strongly demanded in order to suppress the direct tunneling current of the gate insulator. NO stack film [1.17], which suppresses the gate leakage current about 1.5 orders of magnitude, could be a good intermediate solution. However, further high-k materials are requested, as the EOT values reduce with downscaling as nearly 0.7 nm [1.18]. Among the candidates shown in Fig. 1.2, HfO2 and its aluminates, silicates or oxynitrides are now the most popular candidates in recent years.
Nevertheless, there are still various problems to be solved for high-k gate dielectrics before their use in IC technology. First, the poor interface with Si is commonly observed [1.19]. The high-k metal oxides are deposited on the surface of Si and thus do not passivate its surface. This results in a large number of interface traps and charges which is detrimental to metal-oxide-semiconductor (MOS) device performance such as flat band voltage shift and mobility degradation [1.20-1.21].
Second, there is contamination by metal atoms during the deposition of metal oxides (from precursor for CVD) [1.18]. The metal atoms used to form high-k oxides generate deep traps in the silicon band gap. Third, the compatibility of high-k materials with gate electrode needs to be considered [1.22]. Many of the metal oxides mentioned above may not be compatible with traditional gate electrodes used today,
such as poly-Si. The may react with the gate electrode during the subsequent processing and charge its properties, e.g., work function. In addition, one of the main problems is that common high-k dielectrics will crystallize at a fairly low temperature (much less than 900 oC) [1.23]. Crystal grain boundaries then act as high dopant diffusivity paths and may also be the cause of device failure and high leakage. In order to further apply the high-k materials into the CMOS devices, all the problems mentioned above need to be effectively solved.
For the reasons mentioned above, the main purpose of this research is to develop high quality high-k gate dielectrics. CF4 plasma treatment is widely used to improve the SiO2 gate dielectrics [1.24] and thin film transistor (TFT) [1.25-1.27]. The plasma treatment processes are also general used in ultra large scale integration (ULSI) technology especially on annealing steps. To further realize the dielectrics properties of these high-k materials, some reliability issues such as hysteresis, charge trapping and temperature dependence are extensively studied. Although the C-V hysteresis mechanism of high-k gate dielectrics has been widely investigated [1.28-1.30], there is still no research about the hystersis phenomenon for the fluorinated high-k gate dielectrics by using CF4 plasma treatment. Besides, the thermal stability of HfO2 gate dielectrics would be improved for the nitrogen incorporation [1.31-1.33], the characteristics of HfO2 thin film with fluorine incorporation by high temperature annealing are still not studied. Therefore, the C-V hysteresis phenomenon, charge trapping characteristics, thermal stabilities for the fluorinated HfO2 gate dielectrics by using the CF4 plasma treatment and fluorine implantation are entirely studied. A physical model is proposed to well explain the mechanism for electron and hole trapping in fluorinated HfO2 thin film.