Chapter 6 Conclusions and Recommendations for Future Works
6.2 Recommendations for Future Works
There are some topics that are suggested for future works.
As described in this work, CF4 plasma treatment provides a good passivation of trap states near the HfO2/Si interface. However, in this thesis, the CF4 plasma is generated by a conventional PECVD system. High-density plasma (HDP) and electron cyclotron resonance (ECR) plasma are suggested to further dissociate the fluorine atoms and thus improve the efficiency of fluorine passivation. Furthermore, remote-plasma is believed that it can avoid plasma-induced damage in the Si-substrate
during plasma treatment, especially for the pre-CF4 plasma treatment technique. Some further studies of this CF4 plasma treatment can be done by adopting these three plasma systems.
We have demonstrated the high-performance and excellent-reliability HfO2
nMOSFET fluorinated by CF4 plasma treatment. However, the novel HfO2 pMOSFET fluorinated by CF4 plasma treatment can be further studied. The negative bias temperature instability (NBTI) is also an important issue for HfO2 pMOSFET.
Although fluorine incorporation into HfO2 gate dielectrics can effectively passivate the dielectric vacancies, resulting in a deeper trapping cross section and a lower concentration of generated traps. The NBTI mechanism of HfO2 pMOSFET with post-deposition or pre-CF4 plasma treatment will be an interesting research topic.
Besides, the applications of HfO2 gate dielectrics with or without post-deposition and pre-CF4 plasma treatment to other fields such as silicon-oxide-nitride-oxide-silicon (SONOS) flash memory and Si-based thin film transistors (TFT) could be investigated. A novel SONOS memory structure used HfO2
gate dielectrics as tunneling, blocking layer, or the charge trapping layer can be extensively studied. Suitable high-k materials and thickness, additional plasma treatment and annealing should be seriously considered.
We have studied the post and pre CF4 plasma treatment, fluorine implantation and CESL induced strain technique can improve the HfO2 gate dielectric characteristics. Other high-k gate materials such as ZrO2, Al2O3, Gd2O3, La2O3, and HfSiON (Hf-silicate) with these advanced passivation technology and strain engineering can be aggressively investigated.
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Publication List
International Journal:
[1] Chao Sung Lai, Woei Cherng Wu, Kung Ming Fan, Jer Chyi Wang, and Shian Jyh Lin, “Effects of Post CF4 Plasma Treatment on the HfO2 Thin Film,” Japanese Journal of Applied Physics, Vol. 44, No. 4B, pp. 2307–2310, 2005.
[2] Chao Sung Lai, Woei Cherng Wu, Jer Chyi Wang, and Tien Sheng Chao,
“Characteristics of Fluorine Implantation for HfO2 Gate Dielectrics with High-Temperature Postdeposition Annealing,” Japanese Journal of Applied Physics, Vol. 45, No. 4B, pp. 2893-2897, 2006.
[3] Woei Cherng Wu, Chao Sung Lai, Jer Chyi Wang, Ming Wen Ma, and Tien Sheng Chao, “High Performance HfO2 Gate Dielectrics Fluorinated by Post-deposition CF4 Plasma Treatment,” Journal of the Electrochemical Society, Vol.
154, No. 7, pp. H561-H565, 2007.
[4] Woei Cherng Wu, Tien Sheng Chao, Wu Ching Peng, Wen Luh Yang, Jian Hao Chen, Chao Sung Lai, and Tsung Yu Yang, Chien Hsing Lee, Tsung Min Hsieh, Jhyy Cheng Liou, Tzu Ping Chen, Chien Hung Chen, Chih Hung Lin, Hwi Huang Chen, and Joe Ko, “Optimized ONO Thickness for Multi-level and 2-bit/cell Operation for Wrapped-Select-Gate (WSG) SONOS Memory,” Semiconductor Science and Technology, vol. 23, p. 015004, 2008.
[5] Woei Cherng Wu, Chao Sung Lai, Zhu Ming Wang, Jer Chyi Wang, Ming Wen Ma, and Tien Sheng Chao “Carrier Transportation Mechanism of TaN/HfO2/IL/Si Structure with Silicon Surface Fluorine Implantation (SSFI)” had been revised to IEEE Trans. on Electron Device.
International Letter:
[1] Chao Sung Lai, Woei Cherng Wu, Jer Chyi Wang, and Tien Sheng Chao,
“Characterization of CF4-Plasma Fluorinated HfO2 Gate Dielectrics with TaN Metal Gate,” Applied Physics Letters, 86, pp. 222905-222907, 2005.
[2] Chao Sung Lai, Woei Cherng Wu, Tien Sheng Chao, Jian Hao Chen, Jer Chyi Wang, Li-Lin Tay, and Nelson Rowell, “Suppression of Interfacial Reaction for HfO2
on Silicon by Pre-CF4 Plasma Treatment,” Applied Physics Letters, 89, pp.
072904-072906, 2006.
[3] Woei Cherng Wu, Tien Sheng Chao, Wu Chin Peng, Wen Luh Yang, Jer Chyi Wang, Jian Hao Chen, Chao Sung Lai, and Tsung Yu Yang, “Highly Reliable Multi-level and 2-bit/cell Operation of Wrapped-Select-Gate (WSG) SONOS Memory,” IEEE Electron Device Letters, vol. 28, pp. 214-216, 2007.
[4] Woei-Cherng Wu, Chao-Sung Lai, Zhu Ming Wang, Jer-Chyi Wang, Ming Wen Ma, and Tien-Sheng Chao “Current Transport Mechanism of HfO2 Gate Dielectric with Fluorine Incorporation,” Electrochemical and Solid-State Letters, Vol. 11, No. 1, pp. H15-H18. 2008.
[5] Woei Cherng Wu, Tien Sheng Chao, Te Hsin Chiu, Jer Chyi Wang, Chao Sung Lai, Ming Wen Ma, Wen Cheng Lo, and Yi Hsun Ho “Performance Enhancement for Contact Etch Stop Layer (CESL) Strained nMOSFET with HfO2 Gate Dielectrics under Pulsed-IV Measurement,” had been revised to Electrochemical and Solid-State Letters.
International Conference:
[1] Chao Sung Lai, Woei Cherng Wu, Kung Ming Fan, Jer Chyi Wang and Shian Jyh Lin, “Hysteresis Improvements for HfO2 by CF4 Plasma Treatment,”
International Solid State Devices and Materials (SSDM), pp. 742-743, 2004.
[2] Chao Sung Lai, Woei Cherng Wu, Hui Hsin Hsu, Pai Chi Chou and Shu Jen Wu,
“The Polarity Dependence of Capacitances for HfO2 Affected by Post-CF4 Plasma Treatment,” IEEE International Conference on Semiconductor Electronics (ICSE) proceedings, pp. 565-568, 2004.
[3] Chao Sung Lai, Woei Cherng Wu, Jer Chyi Wang and Tien Sheng Chao,
“Thermal Stability Improvements for HfO2 by Fluorine Implantation,” International Solid State Devices and Materials (SSDM), pp. 234-235, 2005.
[4] Jer Chyi Wang, Woei Cherng Wu, Chao Sung Lai, Jam Wem Lee, Kuo Cheng Chiang, De Ching Shie, Tan Fu Lei and Chung Len Lee, “Characterization of Novel HfTiO Gate Dielectrics Post-treated by NH3 Plasma and Ultra-violet Rays,”
International Solid State Devices and Materials (SSDM), pp. 242-243, 2005.
[5] Woei Cherng Wu, Chao Sung Lai, Kuan Ti Wang, Jer Chyi Wang and Tien Sheng Chao, “Current Transportation Mechanism and Interface States Characterization of Sputtered Gd2O3 Gate Dielectrics for ULSI Application,”
International Solid State Devices and Materials (SSDM), pp. 1100-1101, 2006.
[6] Woei Cherng Wu, Tien Sheng Chao, Wu Chin Peng, Wen Luh Yang, Jer Chyi Wang, Jian Hao Chen, Chao Sung Lai, and Tsung Yu Yang, “Highly Reliable Multi-level and 2-bit/cell Operation of Wrapped-Select-Gate (WSG) SONOS Memory
[6] Woei Cherng Wu, Tien Sheng Chao, Wu Chin Peng, Wen Luh Yang, Jer Chyi Wang, Jian Hao Chen, Chao Sung Lai, and Tsung Yu Yang, “Highly Reliable Multi-level and 2-bit/cell Operation of Wrapped-Select-Gate (WSG) SONOS Memory