General Background

In recent years, dimension scaling down of integrated circuits is necessary in order to achieve better performance in silicon-based devices. Gate engineering is one of the most important issues of integrated circuits during scaling down [1]-[3]. There are some problems using polysilicon as the gate material, such as poly depletion, high resistance, and boron penetration into the channel region in submicron CMOS technology node [4]. Polysilicon gate depletion increases the equivalent gate dielectric thickness by about 0.3 nm and degrades channel current drive capability [5], [6]. High gate resistance increases the RC delay and degrades the performance of the devices in high frequency [7]. Although using salicide can release the high gate resistance problem, it is difficult for salicide to maintain a proper aspect ratio of gate stacks whiles the devices continuously scaling down [8]. Boron penetration in p-channel metal oxide semiconductor field effect transistors (p-MOSFETs) reduces the gate oxide reliability and the control ability of threshold voltage [9]. On the other hand, metal gate has been investigated to replace the polysilicon gate to solve the problems we mentioned above. To choose a suitable material to be the metal gate, several issues should be considered

to satisfy the manufacturability and performance. High temperature processes must be kept off, because high temperature processes will cause the instability of the metal film. Thus, low temperature or low thermal budget processes must be developed. The requirements of metal gate are low resistivity, suitable work function, high thermal dynamic stability, and good chemical durability under wet chemical processing [10].

The resistivity of copper (1.67 µΩ-cm) is smaller than aluminum (2.66 µΩ-cm) which is

the most often used metal in conventional IC fabrication. And the resistance electromigration of copper (0.97 eV) is larger than aluminum (0.62 eV) [11]. Because of the low resistivity, copper is a potential material as the gate metal. Nevertheless, there are still some problems with copper in ultra-large-scale integration (ULSI) circuits. The problems are high diffusivity, susceptibility to oxidation and corrosion, high chemical reactivity, and hard to be dry etched in process [12].

By the reasons we mentioned above, the diffusion barrier is significant to the reliability of integrated circuits with copper metallization. Before the selection of the material of diffusion barrier, the knowledge of what kind of the properties are diffusion barrier needed should be learned. Below is the list of the notion of diffusion barriers [13], [14]:

(1) If the barrier layer X is between materials A and B (Fig. 1-1), the barrier should be thermal dynamically stable when in contact with both A and B.

(2) X should prevent harmful interdiffusion between A and B. Thus, diffusivity of both materials A and B in barrier layer should be as low as possible. It means that the X becoming a kinetic barrier to A and B. The most preferred structure would be single-crystalline, but this solution lies generally beyond the capabilities of current technology. A practical second choice is the amorphous structure. However, the amorphous structure is negation with the requirement for the thermodynamic stability.

(3) The barrier layer should form low resistance contacts with materials A and B and be at least a reasonable thermal conductor. The resistivity of the barrier layer itself is usually smaller than 2500 µΩ-cm because of its small thickness compared to that of material A

and B.

(4) X should have excellent adhesion to all materials which can be used in the metallization scheme. However, appropriate reactivity is required in order to establish good adhesion between the barrier and the surrounding materials.

Many kinds of diffusion barrier have been investigated [14]. They are generally divided into four types: sacrificial barrier, stuffed barrier, passive compound barrier, and amorphous barrier. In Fig.1-2, we show the schematic illustration of diffusion barriers. The sacrificial barrier is that the diffusion barrier X reacts with material A and material B, so the material A and B can diffusion into diffusion layer X when the device is operate in operation temperature.

If the reaction rate of diffusion layer with material A and B are slowly enough, the lifetime of the diffusion layer will be longer than that of the device. In such case the sacrificial barrier will be effectiveness. Thus, the reaction rate between X/A, and X/B should not be too high to keep the effectiveness of diffusion barrier. When X and A, B reacts to form compound, the barrier layer X will be ineffective. So the lifetime of the diffusion barrier layer will become the major limitation of the life time of the device. The stuffed barrier is to add some materials into the diffusion barrier. The grain boundary of the diffusion barrier will be occupied by atoms of the material which we add before. The atoms will then block the fast diffusion path.

Thus, the material A and B can not diffuse across the diffusion barrier. The passive compound barrier is to employ the chemical stability of barrier layer X. In case that the reaction at the interface of X/A as well as the interface of X/B are not violently, and the solid solubility for A and B to the X are low. This type of barrier layer is called passive compound barrier. The amorphous barrier is to utilize the amorphous structure has less fast diffusion path, so it can slow down the copper ions diffusion into the dielectrics. But there is a drawback with the amorphous barrier layer. That is, the amorphous barrier layer will be crystallized at high temperature, and then the grain boundaries are again present in the barrier. So, the crystallization temperature of the amorphous film is very important to the amorphous diffusion barrier.

1.2 The choice of copper diffusion barrier

Over the past few years, a considerable number of studies have been made on copper diffusion barriers [15]. In these studies, the refractory metal is the best choice as the barrier layer. Because the refractory metals do not miscible with the copper atom. So the TiN, TaN, Ta, TaSiN, TaO, Ta2N, W, WN, W2N, and TiSiN are choices to be the copper diffusion barrier [16]. The structure of TaSiN, TaO, and TiSiN is amorphous, and that of the others is crystallized [17]. In crystallized structure the copper will diffuse by the grain boundary which forms the fast diffusion path. For the thermal stability, the TaSiN and TiSiN can block the copper atoms diffusion up to 900°C, and make the diffusion path to become longer [18].

However, the resistivities of TaSiN and TiSiN are higher than other materials, and the crystallization of TaSiN and TiSiN will occur at high temperature. On the other hand, Ta and W have lower resistivity than TaSiN and TiSiN. But the sheet resistance of Ta and W will dramatically increase after 400°C annealing because of the diffusion of copper ions into the Si

substrate [19]. And the structure of Ta and W are crystallized. The grain boundary will make copper diffuse across the barrier layer, even at low temperature situation [19]. We can add some impurities, such as nitrogen, oxygen, carbon or silicon to be the crystallization nuclear.

When we add the impurities as the nuclear, the structure of the barrier layer will become amorphous or crystal structure with smaller grain. The fast diffusion path will be therefore eliminated. In addition to the thermal stability, the resistivity is an important parameter of the

barrier layer. In Table 1-1, we list the resistivity of several materials which can be the copper diffusion barrier. As we had mentioned in above section, we must choose a barrier layer which have lower resistivity to reduce the effect of RC delay.

There are two major methods to deposit the copper diffusion barrier: Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD). The diffusion barrier deposited by PVD method has many advantages, such as low cost, easy to fabricate, low resistivity, low impurity concentration, and high density [17]. But there are still one disadvantage using PVD method that is, the worse step coverage. When the dimension of integrated circuits is scaling down, the aspect ratio will be increased. Therefore, the PVD method will cause overhang to appear. As the deposition thickness increased, the overhang will seal the hole and keep a void in the hole. The void in the hole will induce the reliability reduce, and limit the scaling down of the dimension of integrated circuits [20]. The ionized physical vapor deposition (IPVD) and ionized metal plasma (IMP) have been brought up to modify this problem. When the dimension scales down to 0.13 µm, however, the improvement of these methods is restricted.

The diffusion barrier deposited by CVD method has better step coverage than the barrier layer made by PVD method. The CVD method to fabricate the copper diffusion barrier is suitable for scaling down the dimension of integrated circuits [21]. But the process temperature of CVD method is higher than PVD method. Thus the CVD method is not easy to be integrated with back-end-of-line (BEOL) process. The MOCVD has lower process temperature than

general CVD method. Nevertheless, the resistivity of MOCVD fabricated diffusion barrier is higher than that of the others. The ALD method to fabricate the diffusion barrier has been brought up in recent years [22]-[25]. The ALD method has the characteristic of ability to achieve nearly perfect conformity or step coverage. Using this technique, high quality films of superior conformity, in addition to uniform and precisely controlled thickness, can be deposited over various morphologies on a wafer [22].

1.3 Motivation

Hafnium nitride (HfN) is a famous material for metal gate MOSFETs in past few years [26]. Due to the larger negative heat of formation of HfN (-88.2 kcal/mol) compared with titanium nitride (TiN) (-80.4 kcal/mol) and tantalum nitride (TaN) (-60.3kcal/mol), it is expected that the thermal stability of HfN is better than TiN and TaN, and exhibit negligible variation for EOT on RTA treatments up to 1000°C. The work function of HfN is 4.65 eV, it is the mid-gap work function respect to silicon substrate and no obvious change after 1000°C

RTA treatments. Mid-gap work function makes the application of HfN at n-type MOS structure or p-type MOS structure as gate electrode [27]. HfN also has many advantages such as excellent barrier against oxygen diffusive and leakage current stability makes it an ideal gate electrode for MOS device application [28]. But there is one problem using HfN as gate material of MOSFETs or MOS capacitors structure. That is the high sheet resistance of HfN.

High sheet resistance will cause the RC delay becoming more serious. So we need a low resistance material capping on HfN to lowering the sheet resistance of gate. Copper is a low resistance material which is generally used as the interconnection to lower the effect of RC delay. Capping copper on HfN can effectively lower the sheet resistance of gate electrode. But the premise is HfN can block the copper atoms diffusion into the dielectrics and the silicon substrate.

Because of the compact atomic structure, TaN and TiN are regularly used to be the copper diffusion barrier. The high density of HfN (13.8 g/cm³) is larger than that of TaN (13.7 g/cm³) and TiN (5.43 g/ cm³), which conforms to the requirement of copper diffusion barrier:

excellent thermal stability, high melting point, and good adhesion [28]. So we use Cu as the electrode and HfN as the copper diffusion barrier to fabricate the MOS capacitor to investigate the copper diffusion barrier efficiency of HfN, the electric characteristics, and reliability of copper gate MOS capacitor.

1.4 Organization of the Thesis

The investigation includes five chapters. In chapter 1, we make an introduction to describe the issues of gate material we may meet during the dimensions scaling down. And we would talk about using Cu gate to overcome the problems we met in conventional polysilicon gate MOSCAPs. Then, the requirements of diffusion barrier layer to block Cu ions

diffusion were discussed.

In chapter 2, we will investigate the process procedures, measurement methods of electrical properties, and the methods of material analysis.

In chapter 3, we will investigate the electrical properties and reliability of the Cu gate MOSCAPs with different thickness of HfN diffusion barrier. The electrical properties and reliability comparison of TaN and HfN diffusion barrier will discussed in this chapter, too.

In chapter 4, we will investigate the thermal stability of Cu gate MOSCAPs with 28-nm-thick HfN diffusion barrier. The electrical properties and reliability of the MOSCAPs annealed in different annealing temperature will be compared in this chapter.

Finally, in chapter 5, we will make a conclusion in the whole thesis. We will also recommend the best condition for the Cu gate MOSCAPs with HfN diffusion barrier.

Chapter 2

Experimental Procedure

2.1 Standard process

Cu/HfN/SiO2/p-Si MOS capacitors (MOSCAPs) of an area of 4.45×10^-4 cm² were fabricated on 6-inch p-type (100)-oriented Si wafers, which with resistivity of 15-25 Ω-cm.

Fig. 2-1 shows the key process flow of this structure. All wafers were initially cleaned by RCA (Radio Corporation of America) clean process. And 10-nm thermal gate oxide was subsequently deposited on the Si wafers by furnace at 925°C. Afterwards wafers were split

into three groups. Different thickness of HfN films from 20 nm to 60 nm were then deposited on first group of the samples through the metal mask as the Cu diffusion barrier by sputtering.

The sputtering condition is Ar/N2 = 60/1.5 sccm mixed gas ambient and at a sputtering DC power of 200 W. The total gas pressure was kept at 7.6×10^-3 torr during the HfN sputtering

process. Immediately, 300-nm-thick Cu was deposited on these samples as gate electrode.

34-nm-thick TaN film was deposited on the second group of the wafers, and the sputtering condition is in the same manner with the first group of wafers with HfN diffusion barrier.

300-nm-thick Cu film was subsequently deposited on TaN as the gate electrode. The Cu film is directly deposited on the last group of wafers as the control (no barrier) samples. Finally, all

wafers received a 500-nm-thick Al deposition on the wafer backside by the thermal coater to form the ohmic contact.

2.2 Thermal treatments

Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN were fabricated to study the thermal stability of the HfN diffusion barrier and the reliability of Cu gate MOSCAPs. After standard process, the Cu/HfN/SiO2/p-Si MOS capacitors were treated by furnace at 400~600°C for 30 minutes in N2 ambient.

2.3 Measurements

2.3.1 Electrical measurements

Capacitance-Voltage (C-V) characteristics were measured by the Agilent-4284A precision LCR system, and the equivalent oxide thickness (EOT) was estimated by the high frequency (100 KHz) capacitance versus voltage curves in the strong accumulation region.

Current-Voltage (I-V) characteristics were measured by the Keithley Model 4200-SCS semiconductor characterization system.

2.3.2 Time dependent dielectric breakdown (TDDB), lifetime & charge to

breakdown (Q

) measurements

Constant-Voltage-Stress (CVS) was conducted to evaluate reliability. The measurements were performed at room temperature, and the voltages of -13.6V, -13.9V, and -14.2V were applied to the capacitors. In Fig. 2-2, the dielectric breakdown was defined at the point which current density increases more than three orders of magnitude. The lifetime was extracted from the 63% of the time to breakdown in the CVS measurements with different voltages mentioned above. The QBD was calculated from the integrated current density before dielectric breakdown.

2.3.3 Bias temperature stress (BTS) measurements

To investigate the thermal stability of HfN films as the Cu diffusion barrier, BTS measurements were utilized to define the mobile ion quantity in the dielectric by the flat band voltage shift. The BTS measurements were performed at +1MV/cm for 1000 sec with temperatures of 50°C, 100°C, and 150°C.

2.3.4 Elevated temperature measurements

To investigate the conduction mechanism and the electrode work function variation of Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN after different temperature treatments.

I-V characteristics with various temperatures were measured at room temperature, 50°C, 75°C, 100°C, 125°C, and 150°C.

2.3.5 Material analysis

Scanning Electron Microscopy (SEM) was used to determine the exact thickness of HfN diffusion barrier. Secondary-Ion-Mass-Spectrometer (SIMS) was used to evaluate the Cu diffusion barrier efficiency of the HfN films.

Chapter 3

Electrical Characteristics and Reliability of Copper Gate MOSCAPs with HfN Diffusion Barrier

3.1 Electrical characteristics of Cu gate MOSCAPs with different thickness of HfN

Fig. 3-1 to Fig. 3-4 shows the SEM pictures of different thickness of HfN diffusion barrier. We can define the physical thicknesses of HfN diffusion barrier by these pictures as 20 nm, 25 nm, 42 nm, and 60 nm. Fig. 3-5 is the comparison of C-V curves for Cu gate MOSCAP with different thickness of HfN diffusion barrier. In this figure we can find an obviously flat band voltage shift between no barrier control sample and HfN diffusion barrier samples. The flat band voltage shift is caused by the work function difference of Cu and HfN.

The ideal work function of Cu is about 5.1 eV and that of HfN is about 4.65 eV. The comparison of I-V curves of Cu gate MOSCAP with different thickness of HfN diffusion barrier is shown at Fig. 3-6. In this figure, we can find the leakage currents of different thickness of HfN diffusion barrier and no barrier control samples are almost at the same level around the low voltage bias region. But there seems a little difference at the region neighboring breakdown voltage. So we make a Weibull plot of effective breakdown field

(EBD(eff)) in Fig. 3-7. In the Weibull plot, we can see that the absolute value of EBD(eff)

distribution for no barrier control sample is larger than that for the other samples with HfN diffusion barrier. The EBD(eff) for Cu gate MOSCAPs with 20-nm-thick HfN diffusion barrier is smaller than that for Cu gate MOSCAPs with 25-nm-thick and 60-nm-thick HfN diffusion barriers. Cu diffusion into the dielectric and influence on the EBD(eff) are perhaps the reasons why the EBD(eff) for 20-nm-thick HfN is smaller than the other two samples. For no barrier control sample, the quantity of diffusion of Cu ions is random. Thus, the degree of influence of EBD(eff) for Cu ions is random in different MOSCAPs. By this reason, the EBD(eff)

distribution of control sample in Weibull plot is larger than the other HfN diffusion barrier samples.

3.2 Reliability of Cu gate MOSCAPs with different thickness of HfN

The charge to breakdown was measured at applied biases of -13.6V, -13.9V, and -14.2V on the gate electrode. The exhibitions of charge to breakdown at these voltage biases are almost the same. So we compare the charge to breakdown for different thickness of HfN diffusion barrier at voltage biases of -13.6V. Fig. 3-8 is the Weibull plot of the charge to breakdown for Cu gate MOSCAPs with 20-nm-thick to 60-nm-thick HfN diffusion barriers and no barrier control sample. On the Weibull plot of the charge to breakdown for Cu gate

MOSCAPs with 25-nm-thick to 60-nm-thick HfN diffusion barrier, the values of the charge to breakdown are almost the same. As to no barrier control sample, the charge to breakdown is apparently smaller than the other samples with HfN diffusion barrier. We can also find that the charge to breakdown for Cu gate MOSCAPs with 20-nm-thick HfN diffusion barrier is smaller than that for the Cu gate MOSCAPs with 25-nm-thick to 60-nm-thick HfN diffusion barrier. Fig. 3-9 shows the Weibull plot of TDDB of Cu gate MOSCAP with 25-nm-thick to 60-nm-thick HfN diffusion barrier and no barrier control sample. The electric field of -13.06 MV/cm was applied to the gate electrode to measure the TDDB characteristics. The TDDB exhibition of Cu gate MOSCAPs with 25-nm-thick to 60-nm-thick HfN diffusion barrier are almost the same. In Fig.3-10, the TDDB of Cu gate MOSCAP with 20-nm-thick and 28-nm-thick HfN diffusion barrier was compared. The TDDB characteristics were degraded at 20-nm-thick HfN diffusion barrier sample. Fig.3-11 shows the comparison of lifetime of Cu gate MOSCAPs with 20-nm-thick, 25-nm-thick HfN diffusion barrier, and no barrier control sample. The lifetime was measured at -13.6V, -13.9V, and -14.2V to make the Weibull plot of

MOSCAPs with 25-nm-thick to 60-nm-thick HfN diffusion barrier, the values of the charge to breakdown are almost the same. As to no barrier control sample, the charge to breakdown is apparently smaller than the other samples with HfN diffusion barrier. We can also find that the charge to breakdown for Cu gate MOSCAPs with 20-nm-thick HfN diffusion barrier is smaller than that for the Cu gate MOSCAPs with 25-nm-thick to 60-nm-thick HfN diffusion barrier. Fig. 3-9 shows the Weibull plot of TDDB of Cu gate MOSCAP with 25-nm-thick to 60-nm-thick HfN diffusion barrier and no barrier control sample. The electric field of -13.06 MV/cm was applied to the gate electrode to measure the TDDB characteristics. The TDDB exhibition of Cu gate MOSCAPs with 25-nm-thick to 60-nm-thick HfN diffusion barrier are almost the same. In Fig.3-10, the TDDB of Cu gate MOSCAP with 20-nm-thick and 28-nm-thick HfN diffusion barrier was compared. The TDDB characteristics were degraded at 20-nm-thick HfN diffusion barrier sample. Fig.3-11 shows the comparison of lifetime of Cu gate MOSCAPs with 20-nm-thick, 25-nm-thick HfN diffusion barrier, and no barrier control sample. The lifetime was measured at -13.6V, -13.9V, and -14.2V to make the Weibull plot of