Reliability

Fig. 4-23 is the Weibull plot of the charge to breakdown for Cu gate MOSCAP with

28-nm-thick HfN diffusion barrier with regard to as-deposition, 400°C, 500°C, and 600°C annealing. The charge to breakdown was measured at the bias of -13.6V, -13.9V, and -14.2V applied on the gate electrode. The exhibitions of charge to breakdown at these voltage bias conditions are almost the same. So we compare the charge to breakdown for the samples with different annealing temperature at the applied voltage of -13.6V. In the Weibull plot of the charge to breakdown for the as-deposited and the 400°C annealed samples, the values of the charge to breakdown are almost the same. However, the value of the charge to breakdown is decreased with annealing temperature. The slope for the 600°C annealed sample in the Weibull plot is larger than that for the other two annealed ones.

Fig. 4-24 shows the Weibull plot of TDDB for the Cu gate MOSCAP with 28-nm-thick HfN diffusion barriers with regard to as-deposition, 400°C, 500°C, and 600°C annealing. An electric field of -12.82MV/cm was applied for the gate electrode to measure the TDDB characteristics. A slightly decrease can be seen when the annealing temperature was increased.

Fig. 4-25 shows the lifetime for the as-deposited, 400°C, 500°C, and 600°C annealed samples.

The lifetime was measured at -13.6V, -13.9V, and -14.2V to depict the Weibull plot of TDDB.

The 63% of TDDB was selected to depict the plot of lifetime. In Fig. 4-25, we can find that the lifetimes for the as-deposited sample and after 400°C annealed sample are almost the same. But the lifetime was degraded for the samples receiving either 500°C or 600°C annealing.

At chapter two, we showed the degradation of the charge to breakdown and lifetime, which means the barrier efficiency of HfN layer was lowered down and the Cu diffusion into the dielectric occurred. Therefore, it implies the 28-nm-thick HfN barrier efficiency was not degraded after 400°C annealing with respect to almost the same charge to break down and lifetime. For the 500°C annealed sample, a little degradation of charge to breakdown and lifetime was observed. This result indicates the barrier efficiency of the 500°C annealed 28-nm-thick HfN diffusion barrier starts to lower down, and a small amount of Cu ions diffuses into the dielectric. When the annealing temperature was increased to 600°C, a great degradation of charge to breakdown and lifetime was observed. That shows the 600°C annealed sample has larger number of Cu ions diffusion into the dielectric than the 500°C annealed one. The main reason of the HfN barrier efficiency lowering down maybe is the structure changes after annealing. The structure of the as-deposited HfN layer is amorphous.

When we increase the annealing temperature, the grain size of the HfN diffusion barrier will become larger than that with lower temperature annealing. With the increased grain size, the quantity of fast diffusion path will be increased and the barrier efficiency will be lowered down.

4.5 Summary

In this chapter, we investigate the thermal stability of the Cu gate MOSCAPs with

28-nm-thick HfN diffusion barrier. For the sample with 400°C annealing in N2 ambient for 30 minutes, a positive flat band voltage shift has been found related with the as-deposited sample.

By the change of sheet resistance and extracted barrier height from the conduction mechanism fitting, the positive flat band voltage shift is due to the work function difference of gate electrode and the plasma induced oxide charge removal by annealing. After bias-temperature stressing, obvious flat band shift was not found up to 150°C means the quantity of mobile ions in dielectric is small. The reliability issues for the Cu gate MOSCAP with 28-nm-thick HfN diffusion barrier after 400°C annealing are almost the same compared with that for the as deposited sample. As the results we mentioned above, 400°C annealing in N2 ambient for 30 minutes is a suitable annealing condition.

For the samples after 500°C annealing in N2 ambient for 30 minutes, we found a flat band voltage shift after BTS with the temperature increased to 100°C and above. It means the barrier efficiency lowering and the mobile ion injection into the dielectric. The degraded reliability issues show the same results. For the samples after 600°C annealing in N2 ambient for 30 minutes, the Cu diffusion into the dielectric was observed through a flat band voltage shift after BTS and a negative flat band voltage shift in the C-V curve related with 400°C annealed sample. The worse reliability also indicates the Cu diffusion into the dielectric. So, it will cause the degradation of the barrier efficiency of HfN and not suitable for the Cu gate MOSCAPs with either 500°C or 600°C annealing in N2 ambient for 30 minutes.

Chapter 5

Conclusions

HfN, deposited by PVD, is suitable to be the diffusion barrier of Cu. As compared with TaN, the well-known material to be the Cu diffusion barrier, HfN shows the better reliability.

When the thickness of HfN is over 25 nm, the electrical characteristics and reliability are almost unchanged. We can observe the barrier efficiency of Cu gate MOSCAP with over 25-nm-thick HfN diffusion barrier through the SIMS analysis. When the thickness of HfN diffusion barrier is down to 20 nm, the reliability and the barrier efficiency were lowered down. Thus, 25 nm is a suitable thickness condition for HfN to be the Cu diffusion barrier.

For the Cu gate MOSCAP with 28-nm-thick HfN diffusion barrier receiving 400°C furnace annealing in N2 ambient for 30 minutes, we can find a positive flat band voltage shift compared with that for the as-deposited sample. Through the changed sheet resistance and extracted barrier height from the conduction mechanism fitting, the positive flat band voltage shift is due to the work function difference of the gate electrode and the plasma induced oxide charge removal by annealing. After bias-temperature stressing, obvious flat band voltage shift was not found up to 150°C. This implies the quantity of mobile ions in the dielectric is small.

The reliability issues for the Cu gate MOSCAP with 28-nm-thick HfN diffusion barrier after

400°C annealing is almost identical with that for the as-deposited sample. As the results we mentioned above, 400°C annealing in N2 ambient for 30 minutes is a suitable annealing condition.

For the samples with either 500°C or 600°C annealing in N2 ambient for 30 minutes, we found visible flat band voltage shifts after bias-temperature stressing. It implies the barrier efficiency lowered and the mobile ion injection into the dielectric occurred. The same results were shown in the degraded reliability issues. For the sample with 600°C annealing in N2

ambient for 30 minutes, the Cu diffusion into the dielectric was observed through a negative flat band voltage shift in the C-V curve compared with that for the 400°C annealed sample.

Therefore, either 500°C or 600°C annealing in N2 ambient for 30 minutes will cause the degraded barrier efficiency of HfN diffusion barrier such as to not suitable for HfN to be the Cu diffusion barrier in the Cu gate MOSCAPs.

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Table 1-1 The resistivity of various barrier layers

Material Resistivity (µΩ-cm) Ta (bcc) 13-80 (PVD)

Ta

2

N 200-250 (PVD) TaN 250 (PVD), 920 (CVD)

TaSiN 600 (PVD)

Ti 50 (PVD)

TiN 50 (PVD), 1000 (CVD)

TiSiN 400~1000 (PVD) W (bcc) 10-170 (PVD, CVD)

W

₂

N 200 (PVD, CVD)

HfN 100-800 (PVD)

Table 4-1 Comparison of barrier height, work function, flat band, and charge concentration under gate injection for the as deposited, 400ºC, 500ºC, and 600ºC annealed Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier

F-N tunneling

Gate

electrode Flat band Charges in

barrier height (eV)

work

function (eV) voltage (V) dielectric (1/cm²)

As

deposition 2.698 3.608 -2.1 2.65×10¹²

400°C

anneal 3.260 4.170 -0.8 1.36×10¹²

500°C

anneal 3.343 4.253 -0.8 1.50×10¹²

600°C

anneal 3.297 4.207 -1.1 1.96×10¹²

Fig. 1-1 The barrier layer X is between material A and B

Fig. 1-2 (a) sacrificial barrier, (b) stuffed barrier, (c) passive compound barrier, (d) amorphous barrier.

Time (sec)

0 100 200 300 400

10^-4 10^-3 10^-2 10 10¹

defined at the point which current density increases more

10⁰

Current Density (A/m2 )c

-1

Fig. 2-2 Dielectric breakdown was than three orders of magnitude.

Fig. 3-1 SEM picture of 20-nm-thick HfN diffusion barrier

Fig. 3-2 SEM picture of 25-nm-thick HfN diffusion barrier 25 nm 20 nm

42 nm

Fig. 3-3 SEM picture of 42-nm-thick HfN diffusion barrier

60 nm

Fig. 3-4 SEM picture of 60-nm-thick HfN diffusion barrier

-5 -4 -3 -2 -1 0 1

Fig. 3-5 C-V curves for the Cu gate MOSCAP with 20-nm-thick, 25-nm-thick, 42-nm-thick, and 60-nm-thick HfN diffusion barrier and no barrier sample

s

Fig. 3-6 I-V curves for the Cu gate MOSCAPs with 20-nm-thick, 25-nm-thick, 42-nm-thick, and 60-nm-thick HfN diffusion barrier and no barrier sample

Effective Breakdown Field (MV/cm)

Fig. 3-7 Weibull plot of effective breakdown field for the Cu gate MOSCAP with 20-nm-thick, 25-nm-thick, and 60-nm-thick HfN diffusion barrier and no barrier sample

Fig. 3-8 Weibull plot of charge to breakdown for the Cu gate MOSCAPs with 20-nm-thick, 25-nm-thick, 42-nm-thick, and 60-nm-thick HfN diffusion barrier and no barrier

Time (sec)

ick to 60-nm-thick HfN diffusion barrier and no barrier control samples The Weibull plot of TDDB at 13.06 MV/cm for the Cu gate MOSCAPs with 20-nm-th

Fig. 3-10 The Weibull plot of TDDB at 12.82 MV/cm for the Cu gate MOSCAPs with 20-nm-thick and 28-nm-thick HfN diffusion barrier

1/E (cm/MV)

-0.20 -0.15

-0.10 -0.05

0.00

Lifetime (sec)

10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸ 10⁹

No barrier HfN 20nm HfN 25nm

Fig. 3-11 Lifetime of the Cu gate MOSCAPs with 20-nm-thick and 28-nm-thick HfN diffusion barrier

Sputtering time (sec)

0 200 400 600 800 1000 1200 1400

Secondary ion counts

Fig. 3-12 SIMS analysis of the Cu gate MOSCAPs without diffusion barrier

Sputtering time (sec)

0 200 400 600 800 1000 1200

Secondary ion counts

Fig. 3-13 SIMS analysis of the Cu gate MOSCAPs with 20-nm-thick HfN diffusion barrier

Sputtering time (sec)

0 200 400 600 800 1000 1200 1400

Secondary ion counts

Fig. 3-14 SIMS analysis of the Cu gate MOSCAPs with 25-nm-thick HfN diffusion barrier

Sputtering time (sec)

0 200 400 600 800 1000 1200 1400

Secondary ion counts

Fig. 3-15 SIMS analysis of the Cu gate MOSCAPs with 60-nm-thick HfN diffusion barrier

Fig. 3-16 SEM picture of 28-nm-thick HfN diffusion barrie r

Fig. 3-17 SEM picture of 34-nm-thick TaN diffusion barrier 28 nm

34 nm

-5 -4 -3 -2 -1 0 1

Fig. 3-18 The C-V curves for Cu gate MOSC -thick HfN and 34-nm-thick TaN diffusion barrier

Fig. 3-19 The I-V curves for Cu gate MOSCA -thick HfN and 34-nm-thick TaN diffusion barrier

Ps with 28-nm

Charge to Breakdown (C/cm2)

Fig. 3-20 The charge to breakdown for Cu gate MOSCAPs with 28-nm-thick HfN and 34-nm-thick TaN diffusion barrier

Time (sec)

Fig. 3-21 TDDB of the Cu gate MOSCAPs with 28-nm-thick HfN and 34-nm-thick TaN diffusion barrier

1/E (cm/MV)

-0.20 -0.15

-0.10 -0.05

0.00

Lifetime(sec)

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸ 10⁹

HfN 28nm TaN 34nm

Fig. 3-22 Lifetime of the Cu gate MOSCAPs with 28-nm-thick HfN and 34-nm-thick TaN diffusion barrier

Anneal Temperature (^oC)

As deposition 400 500 600

Sheet Resistance (mΩ)

10¹ 10² 10³

Fig.4-1 Sheet resistance for the as deposited, 400°C, 500°C, and 600°C annealed Cu/HfN/SiO2 /p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier

Applied Voltage (V)

Fig.4-2 C-V curves of 100 KHz for the as deposited, 400°C, 500°C, and 600°C annealed Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier

Applied Voltage (V)

Fig.4-3 C-V curves of different frequencies for the as deposited Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier

Applied Voltage (V)

Fig.4-4 C-V curves of different frequencies for Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 400°C annealing

Applied Voltage (V)

Fig.4-5 C-V curves of different frequencies for Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 500°C annealing

Applied Voltage (V)

Fig.4-6 C-V curves of different frequencies for Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 600°C annealing

Applied Voltage (V)

Fig.4-7 Hysteresis of C-V curves for the as deposited Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier

Applied Voltage (V)

Fig.4-8 Hysteresis of C-V curves for Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 400°C annealing

Applied Voltage (V)

Fig.4-9 Hysteresis of C-V curves for Cu/HfN/SiO2 /p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier for 500°C annealing

Applied Voltage (V)

Fig.4-10 Hysteresis of C-V curves for Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 600°C annealing

Applied Voltage (V)

Fig.4-11 I-V curves for the as deposited, 400°C, 500°C, and 600°C annealed Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier

Effective Breakdown Field (MV/cm)

Fig.4-12 Weibull plot of effective breakdown electric field for Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 400°C, 500°C, and 600°C annealing

1/E (cm/MV)

Fig.4-13 Conduction mechanism fitting under gate injection for the as deposited Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier

1/E (cm/MV)

Fig.4-14 Conduction mechanism fitting under gate injection for the Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 400°C annealing

1/E (cm/MV)

Fig.4-15 Conduction mechanism fitting under gate injection for the Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 500°C annealing

1/E (cm/MV)

Fig.4-16 Conduction mechanism fitting under gate injection for the Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 600^oC annealing

Anneal Temperature (^oC)

As deposition 400 500 600

Barrier height (eV)

2.4 2.6 2.8 3.0 3.2 3.4 3.6

Fig.4-17 Barrier height under gate injection for the as deposited, 400°C, 500°C, and 600°C annealed Cu/HfN/ SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier

Fig.4-18(a) Band diagram under gate injection for as deposited Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier

Fig.4-18(b) Band diagram under gate injection for Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 400°C annealing

3.26eV

3.3eV 2.698eV

3.3eV

Applied Voltage (V)

Fig.4-19 C-V curves before and after 1000 sec BTS at 50°C, 100°C, and 150°C for u/HfN/SiO

C thick HfN diffusion barrier after 400^oC

annealing. The field applied was +1 MV/cm.

2/p-Si MOSCAPs with

28-nm--3 -2 -1 0 1

Fig.4-20 C-V curves before and after 1000 sec BTS at 50°C, 100°C, and 150°C for Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 500°C

Applied Voltage (V)

C-V curves before and after 1000 sec BTS at 50°C, 100°C, and 150°C for Cu/HfN/SiO

Fig.4-21

ick HfN diffusion barrier after 600 C annealing. The field applied was +1 MV/cm.

2/p-Si MOSCAPs with 28-nm-th ^o

Temperature (^oC)

Fig.4-22 Flat band shift before and after 1000 sec BTS at 50°C, 100°C, and 150°C for Cu/HfN/SiO2/p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier after 400°C,

Charge to Breakdown (C/cm )²

Charge to breakdown of as deposited, 400°C, 500°C, and 600°C annealed Cu/HfN/SiO

Fig.4-23

ck HfN diffusion barrier

2/p-Si MOSCAPs with 28-nm-thi

10¹ 10² 10³ 10⁴ 10⁵

TDDB of as deposited, 400°C, 500°C, and 600°C annealed Cu/HfN/SiO

Fig.4-24 2 /p-Si

1/E (cm/MV)

-0.15 -0.10

-0.05 0.00

Lifetime (sec)

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸ 10⁹

As deposition 400^oC anneal 500^oC anneal 600^oC anneal

Fig.4-25 Lifetime of as deposited, 400°C, 500°C, and 600°C annealed Cu/HfN/SiO2 /p-Si MOSCAPs with 28-nm-thick HfN diffusion barrier

簡 歷

姓 名: 王 凱 立 性 別: 男

出生日期: 中華民國六十四年九月七日 籍 貫: 台 北 縣

地 址: 台北縣板橋市明德街 12 號五樓 學 歷: 國立中央大學 物理系

(83 年 9 ～ 87 年 6 月)

國立交通大學 電子工程研究所碩士班 (91 年 9 ～ 93 年 6 月)

碩士論文: 銅閘極搭配氮化鉿擴散阻擋層之金氧半

電容研究

A Study on MOSCAPs With Cu Gate Electrode

and HfN Diffusion Barriers

在文檔中 銅閘極搭配氮化鉿擴散阻擋層之金氧半電容研究 (頁 45-0)