As mention above, reduction of gate oxide thickness always accompanies with the downscaling of CMOS technology. So far, we had no problem with the scaling thickness of SiO2 or SiON as gate oxides and that had achieved MOSFET’s devices with excellent performance. However, when the thickness of oxide reduces to smaller than 1.2 nm, the leakage problem becomes serious. At that thickness the leakage current becomes too high due to the direct tunneling of electrons through oxide (Fig. 1.3) [5, 6]. This high value of leakage current does not meet fully the requirement given by ITRS. Moreover, the reliability of the device is hampered by the time-dependent dielectric breakdown of ultra-thin oxide layer [7, 8], as well as by bias temperature instabilities [9].
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Figure 1.3. Leakage current versus voltage for various thickness of SiO2 layers [5, 6]
A MOSFET is a capacitance-operated device, where the source-drain current depends on the gate capacitance:
(1.1)
where o is the permittivity of free space, k is the relative permittivity, A is the area and t is oxide thickness. Since the leakage current is much dependent on the oxide thickness, to maintain the high value of capacitance with thick gate oxide, the value of k need to increase. That means the gate oxide of silicon device has to be replaced by other materials with higher k value, called high k oxides. High k value, in other words, can be described as physical thick but electrically thin materials [10]. Fig 1.4 shows the direct tunneling problem can be solved by replacing SiO2 (SiON) with a physically thicker layer of high k materials [5, 10].
Figure 1.4. At the gate oxide thickness of 1.2 nm (5 layer of atoms), the wave describing the probable location of an electron is broader than the gate oxide and the electron can simply appear on the other side of gate oxide, meaning that direct tunneling of electrons through the insulation.
New high k gate oxide is needed to plug the leak [10]
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The concept of equivalent thickness oxide (EOT) is used to define an “electrical thickness” of new high k gate oxide [11]. The EOT refers to the thickness of any dielectric (tk) scaled by the ratio of its dielectric constant (k) to that of SiO2 ( )
(1.2)
The extraction of EOT requires to fit capacitance-voltage (C-V) characteristics of the MOS structure, taking into account quantum confinement effect in accumulation and inversion layer [12]. Besides, another useful quantity for comparison between gate dielectrics is the capacitance equivalent thickness (CET), which is defined as [12]:
(1.3)
where C is the capacitance (per unit area) of MOS structure measured at a given gate bias.
The extraction of CET does not require to fit C-V data, but depends on the chosen gate bias. CET can also be influenced by gate leakage in leaky devices [12].
The interest in high k dielectric research to replace SiO2 started in the 1980s and renewed in the mid-1990s when the problem of leakage has become more serious. Figure 1.5 shows the parameters (dielectric constant versus band gap) of the candidate oxides [5, 13].
Figure 1.5. Static dielectric constant versus band gap for candidate gate oxides [5, 13]
In general, the relationship between dielectric constant and the band gap is reverse as shown in Fig. 1.5. Thus, the selected high k oxide has to be trade-off between dielectric
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constant and band gap. Band gap must be large enough to have conductance band (CB) and valence band (VB) offsets with semiconductor over 1 eV to minimize the carriers’
injection into its bands [5, 12]. In practice, the CB offset is smaller than VB offset, so that this limits the choice of oxide to those with band gaps over 5 eV [5, 12, 13]. The relative dielectric constant should be somewhere between 10 and 30. Besides, other important requirements for selecting high k also have to be considered, including: thermodynamic stability with Si (and also future channel materials), low interface charge traps (typically less than 1011 eV-1cm-2), low bulk electrically active defects, and kinetically stable and compatible to process at high temperature [5, 12].
In terms of band gap and k values, many high k materials have been selected for study for gate oxide application including Al2O3, ZrO2, HfO2, Y2O3, La2O3, and various lanthanides as well as their silicates and aluminates [13-16]. After thorough research, HfO2 and its silicate, HfSiOx have emerged as promising candidates because of their excellent thermal stability with Si. HfO2 with a k value between 16-20, energy band gap of about 5.4 eV, CB and VB offsets with Si of 1.5 eV and 3.4 eV respectively, has been used for the 45 nm and the recent 32 nm generations.
Transistors with high k gate dielectric were processed with pretty much identical to the existing transistor with SiO2 (SiON) gate dielectric. However, it was found that, high k gate dielectric transistors had suffered a few problems including (1) it took more voltage to turn them on than it should have, and (2) once the transistor was on, the charge move sluggishly though them, slowing the device’s switching speed [10]. The first problem is known as Fermi level pinning (FLP) at polysilicon gate and high k dielectric interface [10, 17]. The effective work function (EWF) of polysilicon could not be altered easily by doping when it was used with high k dielectric. It was found that the EWF of polysilicon/HfO2 stack is determined by Si-Hf bonds instead of Fermi level of polysilicon gate [17]. The EWF of polysilicon in that case was fixed at certain point near the Si conductance band edge, resulting in very high threshold voltage Vth in PMOS devices.
The second problem is known as low charge-carrier mobility or the channel mobility degradation when using high k gate dielectrics [18, 19]. Essentially, high k materials are made up of dipoles and having a large polarization. This large polarization leads to strong vibrations in a semiconductor’s crystal lattice (phonons), resulting in the increase of electron-scattering (Fig. 1.6.a) and thus, reducing their mobility [20]. Research by M. V.
Fischetti et al. also showed that the metal gate with high electron density can screen out
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the effect of phonons on channel electrons (Fig. 1.6.c) [10, 20]. Experimental data by R.
Chau et al. shows clearly effect of phonon-electron scattering by using high k/polySi gate stack (Fig. 1.6.b) and the electron mobility can be improved by using high k/metal gate stack (Fig. 1.6.d) [21]. Besides, the bond between the high k dielectric and the metal gate would be so much better than that between high k and polySi. Thus, the use of gate metal with sufficient value of work function can eliminate the FLP problem of polysilicon gate and allow moderating the threshold voltage of devices. By using gate metal, it is also possible to achieve lower CET value at inversion regime, lower gate resistance, and eliminate the boron penetration into the dielectric and transistor channel as suffering in case of polySi gate.
Figure 1.6. a-Electron density in PolySi gate is not large enough to screen the effect of high k dipoles on semiconductor lattice points, lead to strong phonon-electron scattering; b-Experimental evidence of phonon scattering in the high k dielectric. The net value of the temperature (T) sensitivity factor, d(1/eff)/dT, is negative when coulombic scattering dominates and positive when phonon scattering dominates. [21]; c-Metal gate with high electron density can screen out the vibrations, reduce effect of phonon scattering; d-Experimental (symbols) and simulation (dash lines) data show the improvement of electron mobility by using high k/metal gate stack [21].
So far, we have discussed about the replacement of high k dielectric for SiO2 (SiON) to solve leakage problem. Then, the problems suffering from high k/ Si channel and high k/polySi contact have been also discussed and gate metal replaces for polySi is a solution for these problems. For conclusions, let us take a look to see how good the improvements of devices are for the generations of high k metal gate MOSFETs (Fig. 1.7) [22-24].
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Figure 1.7. The improvements of leakage current and drive currents by using high k metal gate generations [22-24]
1.3. Scaling challenges and future trends