1.4.1. Motivation
The key advantage of III-V compound semiconductors as compared to Si is their high electron mobility and high low-field saturation velocity. The electron mobility enhancement in III-V compounds comes from their lower electron effective mass than that of Si. Figure 1.10 and table 1.1 show electron drift velocities versus electric field and the parameters (carrier mobility, band gap, intrinsic density) of Si, Ge and III-V compounds.
Figure. 1.10. Electron velocities as a function of field of Si, Ge and III-V compound semiconductors.
III-V compound semiconductors exhibit high saturation velocity at low electric field
12 Intrinsic concentration cm-3 1010 21013 2.1106 6.31011 1013 1015 21016 Conduction band DOS cm-3 3.21019 1.01019 4.71017 2.11017 - 8.71016 4.21016
In very short channel length MOSFETs, the carriers exhibit quasi-ballistic transport.
In this case the drive current is not depended on saturation velocity but is determined by carrier injection from the source to drain, i.e. injection velocity, vinj [30]. The carrier injection relates directly to the carrier mobility at low field and thus, the concept of mobility continues to have relevance to ultra-short channel MOSFETs [30]. The use of III-V materials as an alternative channel for Si is due to their advantages in two major requirements for high-performance logic devices: increased speed and reduced power consumption while the integration density keeps increasing [31].
In term of device’s speed, the intrinsic delay time i can be approximated as:
(1.4)
which assumes switching the channel charge Q on the gate capacitance CG by a constant
“ON” drain current IDsat between two logic states with a voltage swing across the channel equal to power supply voltage. The current is measured in saturation with equal gate and drain voltage, VGS=VDS=VD. For channel materials comparison, it is good enough to approximate the intrinsic delay time as:
(1.5) The extrinsic delay time ext can be estimate as:
(1.6)
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where Cext is total capacitance including gate capacitance CG and interconnect parasitic capacitance. Because III-V compound have low effective mass and high electron mobility, the injection velocity in these materials is much higher than that of silicon, as shown in Fig. 1.10 and table 1.1 (injection velocity was measured ~ 2.5-3 107 cm/s in InGaAs and InAs, at least two time higher than strain n-Si MOSFETs [32, 33]). According to equations (1.4), (1.5) and (1.6), this high injection velocity explains why III-V MOSFETs are expected to get higher switching speed, higher drive current than Si MOSFETs.
In term of power, MOSFETs have mostly capacitive input impedance and a certain energy is require to recharge the gate capacitance [31]. The charging energy depends on distribution of carrier in the channel and capacitance change below threshold. Therefore, it is assumed that the dynamic energy is proportional to per bit and it combines with intrinsic delay time i to become intrinsic energy-delay product (EDPi):
(1.7)
From here, it is clear to see that the III-V channel is considerably more favorable than Si in reducing energy-delay products even in the architectures with large parasitic. This because in the ballistic regime (ultra-short channel) with large parasitic, EDP improvement results from the ability to get high drain current at low voltage overdrive VD-VT where VT is threshold voltage. Due to high low field electron mobility in III-V compounds, the supply voltage VD can be reduced while the value of VT can keep relative high to maintain low threshold leakage current i.e., low static power [31].
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Figure. 1.11. III–V HEMTs characteristics compared with standard silicon MOSFETs a, Intrinsic gate delay. b, Normalized energy-delay product of n-channel InSb and InGaAs HEMTs [28, 34]
For highlight the advantages of III-V compounds in speed and power improvements, recent work on InGaAs, InSb n-channels high electron mobility transistors (HEMTs) have demonstrated the significantly reduction of gate intrinsic delay as well as EDPs as compared to standard Si MOSFETs (Fig. 1.11) [28, 34]. Both n- and p- channel InSb HEMTs have been demonstrated very high speed at a low supply voltage of only 0.5 V [35, 36]. Compared with state-of-the-art silicon transistors, these n-channel III–V transistors show either a 1.5-fold improvement in intrinsic speed performance at the same power, or 10-fold reduction in power for the same speed performance [35]. The p-channel HEMTs also show either a 2-fold improvement in intrinsic speed performance at the same power, or 10-fold reduction in power for the same speed performance as compared to p-channel Si MOSFETs [36].
Another advantage of III-V materials is the band structure. InGaAs, InAs compounds have large band off-set with the barrier and large separation between high electron-effective-mass L- and X-valleys and low electron-electron-effective-mass -valley. This allows to get high number of electrons in the -valley and consequently get high drive current [31].
1.4.2. Challenges
Although III-V based MOSFETs give a significantly advantages for future CMOS technology, there are some challenges which need to be addressed. Although band structure have large separation between valleys, III-V materials have low density of state (DOS) in the low effective-mass -valley (Tab. 1.1) [29]. This low DOS tends to reduce inversion charge (Qinv) and hence reduce drive current. The small direct band gap of III-V
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MOSFETs inherently gives rise to very large band to band tunneling (BTBT) leakage current as compared to Si. They also have a high permittivity and hence are more prone to short channel effect (SCE). Non-planar technique may also need to be applied to III-V MOSFETs to improve the electrostatics with scaling [28].
The integration of high k on III-V for future MOSFETs is an indispensable progress for research since high k/ Si MOSFETs had been introduced for 45 nm and 32 nm generations. Even the current researches on III-V HEMTs have been shown very significant merits for future transistors [28, 34-36], the leakage is still a serious problem and the architecture of MOSHEMTs with the introduction of high-k materials on top of channel seems to be a good solution. It was recognized that at III-V surfaces, Fermi level is always pinned at a fixed position, called surface Fermi level pinning (FLP) [37]. It has been then realized the FLP problem has related to the poor native oxides at III-V’s interfaces [38]. For instance, GaAs native oxide consists of As- and Ga-related oxides (As2O3, As2O5, Ga2O3, Ga2O5, Ga2O, etc). These poor native oxides lead to very high interface traps density which consequently pins Fermi level at a fixed position. When introducing high k on III-V, the FLP at high k/ III-V interface has imposed a key challenge to the development of surface-channel inversion-model III-V MOSFETs. For more than four decades, to solve FLP issue, research efforts have been focused on the surface treatments i.e. reducing/eliminating and passivation the re-oxidation of III-V’s native oxides before/during the high k deposition. Although some significant results have been achieved, the understanding of interface problems is still limited and FLP issue is still a hot topic for researchers working on III-V MOSFETs.
1.4.3. Current progress
Since FLP issue is a key challenge to the development of high k/ III-V MOSFETs, various in-situ and ex-situ passivation methods have been developed in order to improve high k/ III-V interface and let the free-movement of Fermi level. The first in-situ approach is the deposition of the gate dielectric on freshly grown III-V’s surfaces (GaAs, InGaAs). For instance, in a multi-chamber molecular beam epitaxy (MBE) system, III-V epi-layers are transformed from III-V chamber to oxide chamber without exposed to air [39-41]. The in-situ process with ultra-high vacuum (UHV) e-beam deposition of Ga2O3/Gd2O3 (GGO) gate dielectric has shown remarkable improvement of GGO/GaAs interface with low interface density, smaller than 1011 eV-1cm-2 [39, 40]. The use of this
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process for 1m gate length InGaAs MOSFETs devices have achieved outstanding performance with maximum drain current of 1.05 A/mm, transconductance of 714 mS/mm, and a peak mobility of 1300 cm2/V.s [42]. In-situ gases treatment is another interesting approach [43-45]. Period to gate dielectric deposition, III-V’s surfaces are treated by gases (such as H2, N2, NH3, H2S, etc), using thermal or plasma processes.
Although some significant results were achieved [43], the use of this method is still limited. This may be due to the effect of the surface damage during plasma process.
The ex-situ processes widely used for research due to it is simpler than in-situ process.
Moreover, from manufacturing perspective, an ex-situ process flow has its incentive.
There are many ex-situ approaches have been demonstrated for research but they can be divided into two groups: using chemical solutions and using interfacial passivation layers (IPLs). For the first approach, chemical solution such as HCl, HF, NH4OH, (NH4)2S, HBr, etc., have been used before the deposition of gate dielectric [46-48]. By using chemical solutions, III-V native oxides could be eliminated. Moreover, the use of sulfide treatment can prevent the re-oxidation of native oxides at surface. By using this method, the improvement of high k/III-V interface with the unpinning of Fermi level has been clearly demonstrated. High performance inversion-mode InGaAs MOSFETs based on this surface treatment method have been demonstrated with high drain current of 1.1 A/mm and extrinsic transconductance of 1.1 S/mm [48, 49]. Interfacial passivation layers (IPL) is another interesting approach. This method has been developed by using very thin layers of Si, Si/Ge, Ge, SiN, AlN, etc., [50-58] between gate dielectric and III-V channels. The use of IPLs has shown the improvement of interface quality and gave a promising device performance. However, the contribution to increasing EOT may limit the use of IPLs for future MOSFETs.
Atomic layer deposition (ALD) has been a mainstream method for high k deposition.
This is an ex-situ, robust, and manufacturable process, which attracts wider interests in academia and industry. Besides good oxide quality, well thickness control, the ALD is also known with a “self-cleaning” effect of precursors and provide a high quality of high k/III-V interfaces [59]. Up to now, all high performance inversion-mode high k/III-V MOSFETs devices were based on or related to this high k deposition method [42, 48, 49].
The ALD method, which had been used in manufacturing for 45 nm and 32 nm high k/ Si generations, is believed to be a mainstream technique for future high k/III-V MOSFETs.
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After a long time research, considerable progress have been made in MOSFETs performance. However, there are still many problems need to be overcome. For instance, the smallest gate length of the working devices is still limited at above 100 nm; the Ion/Ioff ratio, subthreshold slope (SS), anddrain-induced barrier lowering (DIBL) values are still high when scaling down gate length into deep submicron [60]. In future, like Si, non-planar technique needs to be applied for III-V MOSFETs. Besides, efforts must be continued to improve high k/III-V interface quality, source/drain junction engineering, etc.
Besides the study on MOSFETs, III-V HEMTs device is the other promising and interesting approach for the future devices. These devices with two dimensional electron gas (2DEG) transport on an almost perfect channel allow to get a very high performance.
In fact, the p- and n- short channel high In-content InGaAs, InAs, InSb HEMTs have shown very high drain current at very low supply voltage (as low as 0.5 V) [35, 36, 61, 62]. Based on these significant results, efforts are continuing in order to realize the performance of HEMTs (MOSHEMTs) for future high speed, low power digital application.